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CD54/74HC03, CD54/74HCT03
Data sheet acquired from Harris Semiconductor SCHS126A
February 1998 - Revised May 2000
High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain
Description
The 'HC03 and 'HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally as well as pin compatible with the standard LS logic family. These open drain NAND gates can drive into resistive loads to output voltages as high as 10V. Minimum values of RL required versus load voltage are shown in Figure 2.
Features
* Buffered Inputs
[ /Title (CD74H C03, CD74H CT03) /Subject High peed MOS ogic uad 2nput
* Typical Propagation Delay: 8ns at VCC = 5V, CL = 15pF, TA = 25oC * Output Pull-up to 10V * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD54HC03F CD54HC03F3A CD74HC03E CD74HC03M CD54HCT03F3A CD74HCT03E CD74HCT03M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC
Pinout
CD54HC03, CD54HCT03 (CERDIP) CD74HC03, CD74HCT03 (PDIP, SOIC) TOP VIEW
1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2000, Texas Instruments Incorporated
1
CD54/74HC03, CD54/74HCT03 Functional Diagram
1A 1B 2A 2B 3A 3B 4A 4B
1 2 4 5 9 10 12 13
3 6 8
1Y 2Y
3Y 11 4Y
GND = 7 VCC = 14
TRUTH TABLE A L H L H NOTES: 3. Requires pull-up (RL to VL) 4. Without pull-up (high impedance) B L L H H Z (Note 4) Z (Note 4) Z (Note 4) L Y H (Note 3) H (Note 3) H (Note 3) L
Logic Symbol
nA nY
nB
2
CD54/74HC03, CD54/74HCT03
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC Drain Current, per Output, IO For -0.5V < VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 5) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 5. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage VIH VIL 4.5 to 5.5 4.5 to 5.5 2 0.8 2 0.8 2 0.8 V V II ICC VCC or GND VCC or GND VOL VIH or VIL 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 2 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 20 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 40 V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC03, CD54/74HCT03
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 6. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 4 SYMBOL VOL VI (V) VIH or VIL IO (mA) VCC (V) 0.02 4.5 4.5 MIN 25oC TYP MAX 0.1 0.26 -40oC TO 85oC MIN MAX 0.1 0.33 -55oC TO 125oC MIN MAX 0.1 0.4 UNITS V V
5.5
-
0.1
-
1
-
1
A
ICC ICC (Note 6)
0 -
5.5 4.5 to 5.5
-
100
2 360
-
20 450
-
40 490
A A
HCT Input Loading Table
INPUT nA, nB UNIT LOADS 1
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360A max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, Input to Output (Figure 1) tPLH, tPHL CL = 50pF 2 4.5 6 Propagation Delay, Data Input to Output Y Transition Times (Figure 1) tPLH, tPHL tTLH, tTHL CL = 15pF CL = 50pF 5 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 7, 8) HCT TYPES Propagation Delay, Input to Output (Figure 1) Propagation Delay, Data Input to Output Y Transition Times (Figure 1) Input Capacitance tPLH, tPHL tPLH, tPHL tTLH, tTHL CI CL = 50pF CL = 15pF CL = 50pF 4.5 5 4.5 9 24 15 10 30 19 10 36 22 10 ns ns ns pF CI CPD 5 8 6.4 100 20 17 75 15 13 10 125 25 21 95 19 16 10 18 150 30 26 110 22 19 10 ns ns ns ns ns ns ns pF pF SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
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CD54/74HC03, CD54/74HCT03
Switching Specifications Input tr, tf = 6ns
PARAMETER Power Dissipation Capacitance (Notes 7, 8) NOTES: 7. CPD is used to determine the dynamic power consumption, per gate. 8. PD = CPD VCC2 fi + (CL VCC2 fo) + (VL2/RL) (Duty Factor "Low") where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage, Duty Factor "Low" = percent of time output is "low", VL = output voltage, RL = pull-up resistor. SYMBOL CPD (Continued) VCC (V) 5 25oC MIN TYP 9 MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS pF
TEST CONDITIONS -
Test Circuits and Waveforms
INPUT LEVEL RL MIN, PULLUP RESISTOR () VS tPLZ 90% nY 10% tTHL OUTPUT LOW nA(nB) OUTPUT OFF OPEN DRAIN NAND GATE VCC OUTPUT LOW 1k VCC 50pF 0 1 2 3 4 5 6 7 VL, LOAD VOLTAGE (V) 8 9 10 VS tPZL VOH VOL 800 700 600 500 400 300 200 100 HC/HCT03 VCC = 5V 10% VL HC RL VO VL 0.8V (HCT VIL MAX) 1.35V (HC VIL MAX) RL 0.26V MAX = R = 4mA VO ON oC 65 AT 25 RON
HCT
nB(nA)
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY TIMES, AND TEST CIRCUIT
tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
tr = 6ns INPUT GND tTHL 2.7V 1.3V 0.3V
tf = 6ns 3V
GND tTLH 90%
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V 10%
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
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Copyright (c) 2000, Texas Instruments Incorporated

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