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CD54/74HC75, CD54/74HCT75
Data sheet acquired from Harris Semiconductor SCHS135A
March 1998 - Revised May 2000
Dual 2-Bit Bistable Transparent Latch
Description
The 'HC75 and 'HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected.
Features
* True and Complementary Outputs
[ /Title (CD74 HC75, CD74 HCT75 ) /Subject Dual -Bit istabl
* Buffered Inputs and Outputs * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD54HC75F3A CD74HC75E CD74HC75M CD54HCT75F3A CD74HCT75E NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP
Pinout
CD54HC75, CD54HCT75 (CERDIP) CD74HC75, CD74HCT75 (PDIP, SOIC) TOP VIEW
1Q0 1 1D0 2 1D1 3 2E 4 VCC 5 2D0 6 2D1 7 2Q1 8
16 1Q0 15 1Q1 14 1Q1 13 1E 12 GND 11 2Q0 10 2Q0 9 2Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2000, Texas Instruments Incorporated
1
CD54/74HC75, CD54/74HCT75 Functional Diagram
16 (10) 2 (6) D0 3 (7) D1 1 OF 2 LATCHES 1 (11) Q0 14 (8) Q1 15 (9) 13 (4) E Q1
Q0
TRUTH TABLE INPUTS D L H X E H H L Q L H Q0 OUTPUTS Q H L Q0
NOTE: H = High Level L = Low Level X = Don't Care Q0 = The level of Q before the transition of E.
Logic Diagram
LATCH 0 2 (6) D0 16 (10) D LE 13 (4) E Q LE Q0 1 (11) Q0 LE P Q N LE Q LE P N LE
14 (8) Q1 LE 3 (7) D1 D LATCH 1 5 12 VCC GND Q LE 15 (9) Q1
FIGURE 1. LOGIC DIAGRAM
FIGURE 2. LATCH DETAIL
2
CD54/74HC75, CD54/74HCT75
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 2 4.5 6 -4 -5.2 0.02 4.5 6 2 4.5 6 4 5.2 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD54/74HC75, CD54/74HCT75
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II VCC and GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) VCC (V) 0 6 MIN 25oC TYP MAX 4 -40oC TO 85oC MIN MAX 40 -55oC TO 125oC MIN MAX 80 UNITS A
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
-4 0.02
4.5 4.5
-
-
0.1 0.26
-
0.1 0.33
-
0.1 0.4
V V
4
5.5
-
0.1
-
1
-
1
A
ICC ICC (Note 4)
0 -
5.5 4.5 to 5.5
-
100
4 360
-
40 450
-
80 490
A A
HCT Input Loading Table
INPUT D0, D1 1E, 2E UNIT LOADS 0.8 1.2
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360A max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES Pulse Width Enable Input tW 2 4.5 6 Setup Time D to Enable tSU 2 4.5 6 80 16 14 60 12 10 100 20 17 75 15 13 120 24 20 90 18 15 ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54/74HC75, CD54/74HCT75
Prerequisite For Switching Specifications
PARAMETER Hold Time Enable to D SYMBOL tH (Continued) VCC (V) 2 4.5 6 HCT TYPES Pulse Width Enable Input Setup Time D to Enable Hold Time Enable to D tW tSU tH 4.5 4.5 4.5 16 12 3 20 15 3 24 18 3 ns ns ns 25oC MIN 3 3 3 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 3 3 3 MAX MIN 3 3 3 MAX UNITS ns ns ns
TEST CONDITIONS -
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay, Data to Q tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, Data to Q tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, Enable to Q tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Propagation Delay, Enable to Q tPLH, tPHL CL = 50pF CL = 50pF CL = 15pF CL = 50pF Output Transition Time tTLH, tTHL CL = 50pF CL = 50pF CL = 50pF Input Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay, Data to Q Propagation Delay, Data to Q Propagation Delay, Enable to Q tPLH, tPHL CL = 50pF CL = 15pF tPLH, tPHL CL = 50pF CL = 15pF tPLH, tPHL CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 11 11 11 28 28 28 35 35 35 42 42 42 ns ns ns ns ns ns CI CPD 2 4.5 5 6 2 4.5 5 6 2 4.5 5 6 2 4.5 5 6 2 4.5 6 5 9 10 10 11 46 110 22 19 130 26 22 130 26 22 130 26 22 75 15 13 10 140 28 24 165 33 28 165 33 28 165 33 28 95 19 16 10 165 33 28 195 39 33 195 39 33 195 39 33 110 22 19 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
5
CD54/74HC75, CD54/74HCT75
Switching Specifications Input tr, tf = 6ns
PARAMETER Propagation Delay, Enable to Q Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per latch. 6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. SYMBOL tPLH, tPHL (Continued) VCC (V) 4.5 5 4.5 5 25oC MIN TYP 12 46 MAX 30 15 10 -40oC TO 85oC -55oC TO 125oC MIN MAX 38 19 10 MIN MAX 45 22 10 UNITS ns ns ns pF pF
TEST CONDITIONS CL = 50pF CL = 15pF
tTLH, tTHL CI CPD
CL = 50pF -
Test Circuits and Waveforms
trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK 2.7V 0.3V trCL = 6ns tWL + tWH = tfCL = 6ns I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
tr = 6ns INPUT GND 2.7V 1.3V 0.3V
tf = 6ns 3V
GND tTLH 90%
tTHL
tTLH 90% 50% 10% tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V 10%
FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
6
CD54/74HC75, CD54/74HCT75 Test Circuits and Waveforms
trCL CLOCK INPUT 90% 10% tH(H) 50% GND tH(L) VCC DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL tREM 3V SET, RESET OR PRESET 50% GND tSU(H) tTLH OUTPUT 90% 1.3V tPLH 90% 1.3V 10% tPHL tSU(L) tTHL DATA INPUT tfCL VCC CLOCK INPUT
(Continued)
trCL 2.7V 0.3V tH(H) 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V GND tfCL 3V
50% GND
1.3V GND
IC
CL 50pF
IC
CL 50pF
FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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Copyright (c) 2000, Texas Instruments Incorporated

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