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CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237
Data sheet acquired from Harris Semiconductor SCHS146A
March 1998 - Revised May 2000
High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches
Description
The CD74HC137, CD74HCT137, 'HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the 'HC237 and CD74HCT237 the selected output is a "High".
Features
[ /Title (CD74 HC137 , CD74 HCT13 7, CD74 HC237 , CD74 HCT23 7) /Subject High peed
* Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for 'HC237 and CD74HCT237 * l/O Port or Memory Selector * Two Enable Inputs to Simplify Cascading * Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD74HC137E CD74HCT137E CD54HC237F CD54HC237F3A TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld PDIP
Pinout
CD54HC237 (CERDIP) CD74HC137, CD74HCT137, CD74HC237, CD74HCT237 (PDIP, SOIC) TOP VIEW
A0 1 A1 2 A3 3 LE 4 OE1 5 OE0 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
CD74HC237E CD74HC237M CD74HCT237E NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2000, Texas Instruments Incorporated
1
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237 Functional Diagram
1 2 3 4 LE 3-BIT LATCH HC/HCT HC/HCT 237 137 15 Y0 Y0 14 1 OF 8 DECODER 13 12 11 10 5 6 GND = 8 VCC = 16 9 7 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A0 A1 A2
OE1 OE0
'HC137, 'HCT137 TRUTH TABLE INPUTS LE X X L L L L L L L L H OE0 X L H H H H H H H H H OE1 H X L L L L L L L L L A2 X X L L L L H H H H X A1 X X L L H H L L H H X A0 X X L H L H L H L H X Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H OUTPUTS Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L
Depends upon the address previously applied while LE was at a logic low.
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care 'HC237, 'HCT237 TRUTH TABLE INPUTS LE X X L L L L L L L L H OE0 X L H H H H H H H H H OE1 H X L L L L L L L L L A2 X X L L L L H H H H X A1 X X L L H H L L H H X A0 X X L H L H L H L H X Y0 L L H L L L L L L L Y1 L L L H L L L L L L Y2 L L L L H L L L L L OUTPUTS Y3 L L L L L H L L L L Y4 L L L L L L H L L L Y5 L L L L L L L H L L Y6 L L L L L L L L H L Y7 L L L L L L L L L H
Depends upon the address previously applied while LE was at a logic low.
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care
2
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237 Functional Block Diagram
A0 LE 1 A0 p n LE LE p n LE A1 2 A1 A1 LATCH A0 11 Y4 10 3 A2 A2 LATCH A2 A2 9 Y6 LE 4 LE LE 7 Y7 Y5 12 Y3 13 Y2 A0 15 Y0 14 Y1
5 OE1
6 OE0
3
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC (Note) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC VI (V) VCC or GND IO (mA) 0 25oC MIN TYP MAX 8 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 MIN MAX 160 UNITS A
VCC (V) 6
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
0.1 8 360
-
1 80 450
-
1 160 490
A A A
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT All UNIT LOADS 1.5
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC.
Prerequisite For Switching Specifications
PARAMETER HC TYPES An to LE Setup Time SYMBOL tSU VCC (V) 2 4.5 6 An to LE Hold Time tH 2 4.5 6 25oC MIN 50 10 9 30 6 5 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 65 13 11 40 8 7 MAX MIN 75 15 13 45 9 8 MAX UNITS ns ns ns ns ns ns
5
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237
Prerequisite For Switching Specifications
PARAMETER LE Pulse Width SYMBOL tW (Continued) VCC (V) 2 4.5 6 HCT TYPES An to LE Setup Time An to LE Hold Time CD74HCT137 CD74HCT237 LE Pulse Width tH tH tW 4.5 4.5 4.5 7 5 10 9 5 13 11 5 15 ns ns ns tSU 4.5 25oC MIN 50 10 9 10 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 65 13 1 13 MAX MIN 75 15 13 15 MAX UNITS ns ns ns ns
Switching Specifications Input tr, tf = 6ns
TEST CONDITIONS 25oC VCC (V) 2 4.5 6 Propagation Delay 'HC237, CD74HCT237 An to any Y tPLH, tPHL CL = 50pF 2 4.5 6 Address to Output CD74HC137 'HC237 OE0 to any Y or Y tPLH, tPHL CL = 15pF tPLH, tPHL CL = 15pF tPLH, tPHL CL = 50pF 5 5 2 4.5 6 OE1 to any Y or Y tTLH, tTHL CL = 50pF 2 4.5 6 LE to any Y or Y tTLH, tTHL CL = 50pF 2 4.5 6 Power Dissipation Capacitance, (Notes 4, 5) CD74HC137 'HC237 Output Transition Time 5 15 13 145 29 25 145 29 25 190 38 32 180 36 31 180 36 31 240 48 41 220 44 38 220 44 38 285 57 48 ns ns ns ns ns ns ns ns ns ns ns MIN TYP MAX 180 36 31 160 32 27 -40oC TO 85oC MIN MAX 225 45 38 200 40 34 -55oC TO 125oC MIN MAX 270 54 46 240 48 41 UNITS ns ns ns ns ns ns
PARAMETER HC TYPES Propagation Delay CD74HC137, CD74HCT137 An to any Y
SYMBOL
tPLH, tPHL CL = 50pF
CPD CPD
CL = 15pF CL = 15pF
5 5 2 4.5 6
-
19 23 -
75 15 13 10
-
95 19 16 10
-
110 22 19 10
pF pF ns ns ns pF
tTLH, tTHL CL = 50pF
Input Capacitance
CI
-
-
6
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237
Switching Specifications Input tr, tf = 6ns (Continued)
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HCT TYPES Propagation Delay An to any Y or Y Address to Output OE0 to any Y (HC137) OE0 to any Y (HC237) OE1 to any Y (HC137) OE1 to any Y (HC237) LE to any Y (HC137) LE to any Y (HC237) Power Dissipation Capacitance, (Notes 4, 5) CD74HC137 'HC237 Output Transition Time Input Capacitance NOTES:
SYMBOL
tPLH, tPHL CL = 50pF tPLH, tPHL CL = 15pF tPLH, tPHL CL = 50pF tPLH, tPHL CL = 50pF tTLH, tTHL CL = 50pF tTLH, tTHL CL = 50pF tTLH, tTHL CL = 50pF tTLH, tTHL CL = 50pF
4.5 5 4.5 4.5 4.5 4.5 4.5 4.5
-
16 -
38 35 33 37 35 44 42
-
48 44 41 46 44 55 53
-
57 53 60 56 53 66 63
ns ns ns ns ns ns ns ns
CPD CPD
CL = 15pF CL = 15pF
5 5 4.5 -
-
19 23
15
-
19
-
22
pF pF ns pF
tTLH, tTHL CL = 50pF CI -
-
-
10
-
10
-
10
4. CPD is used to determine the dynamic power consumption, per gate. 5. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
tr = 6ns INPUT GND 2.7V 1.3V 0.3V
tf = 6ns 3V
GND tTLH 90%
tTHL
tTLH 90% 50% 10% tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V 10%
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
7
CD74HC137, CD74HCT137, CD54/74HC237, CD74HCT237 Test Circuits and Waveforms
(Continued)
trCL CLOCK INPUT 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT
trCL 2.7V 0.3V tH(H)
tfCL 3V 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 90% 1.3V 10% tPHL GND
DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL
50% GND
OUTPUT
90% 1.3V tPLH
50% GND
tREM 3V SET, RESET OR PRESET
1.3V GND
IC
CL 50pF
IC
CL 50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
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Copyright (c) 2000, Texas Instruments Incorporated

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