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CD74HC390, CD54/74HCT390
Data sheet acquired from Harris Semiconductor SCHS185A
September 1997 - Revised May 2000
High Speed CMOS Logic Dual Decade Ripple Counter
Description
The CD74HC390 and 'HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divideby-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the "1" and "2" prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low.
Features
* Two BCD Decade or Bi-Quinary Counters
[ /Title (CD74 HC390 , CD74 HCT39 0) /Subject High peed MOS
* One Package Can Be Configured to Divide-by-2, 4, 5,10, 20, 25, 50 or 100 * Two Master Reset Inputs to Clear Each Decade Counter Individually * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC
Pinout
CD54HCT390 (CERDIP) CD74HC390, CD74HCT390 TOP VIEW
1CP0 1 1MR 2 1Q0 3 1CP1 4 1Q1 5 1Q2 6 1Q3 7 GND 8 16 VCC 15 2CP0 14 2MR 13 2Q0 12 2CP1 11 2Q1 10 2Q2 9 2Q3
CD74HC390E CD74HC390M CD54HCT390F3A CD74HCT390E CD74HCT390M NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) 2000, Texas Instruments Incorporated
1
CD74HC390, CD54/74HCT390 Functional Diagram
1 (15) nCP0 2 (14) nMR 3 (13)
COUNTER
/2
nQ0
5 (11) 4 (12) nCP1 GND = 8 VCC = 16
COUNTER
/5
6 (10) 7 (9)
nQ1 nQ2 nQ3
TRUTH TABLE INPUTS CP X MR L L H ACTION No Change Count All Qs Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level, = Transition from High to Low.
BCD COUNT SEQUENCE FOR 1/2 THE 390 OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 Q0 L H L H L H L H L H Q1 L L H H L L H H L L Q2 L L L L H H H H L L Q3 L L L L L L L L H H
B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390 OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 Q0 L L L L L H H H H H Q1 L H L H L L H L H L Q2 L L H H L L H H H L Q3 L L L L H L L L L H
NOTE: Output nQ0 connected to nCP1 with counter input on nCP0.
NOTE: Output nQ3 connected to nCP0 with counter input on nCP1.
2
CD74HC390, CD54/74HCT390 Logic Diagram
4(12) nCP1
Q 1(15) nCP0
Q
Q
Q
2(14) nMR
R
R
R
R
VCC = 16 GND = 8
3(13) nQ0
5(11) nQ1
6(10) nQ2
7(9) nQ3
3
CD74HC390, CD54/74HCT390
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD74HC390, CD54/74HCT390
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
VCC (V)
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
0.1 8 360
-
1 80 450
-
1 160 490
A A A
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT nCP0 nCP1, MR UNIT LOADS 0.45 0.6
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360A max at 25oC.
Prerequisite for Switching Specifications
25oC CHARACTERISTIC HC TYPES Maximum Clock Frequency fMAX 2 4.5 6 Clock Pulse Width, nCP0, nCP1 tW 2 4.5 6 Reset Removal Time tREM 2 4.5 6 6 30 35 80 16 14 70 14 12 5 24 28 100 20 17 90 18 15 4 20 24 120 24 20 105 21 18 MHz MHz MHz ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
5
CD74HC390, CD54/74HCT390
Prerequisite for Switching Specifications
CHARACTERISTIC Reset Pulse Width SYMBOL tW VCC (V) 2 4.5 6 HCT TYPES Maximum Clock Frequency Clock Pulse Width, nCP0, nCP1 Reset Removal Time Reset Pulse Width fMAX tW tREM tW 4.5 4.5 4.5 4.5 27 19 15 13 22 24 19 16 18 29 22 20 MHz ns ns ns (Continued) 25oC MIN 50 10 9 TYP MAX -40oC TO 85oC MIN 65 13 11 MAX -55oC TO 125oC MIN 75 15 13 MAX UNITS ns ns ns
Switching Specifications Input tr, tf = 6ns
PARAMETER HC TYPES Propagation Delay (Figure 1) nCP0 to nQ0 TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
tPLH, tPHL
CL = 50pF
2 4.5
-
14 15 16 28
175 35 30 185 37 31 245 49 42 180 36 31 365 73 62 190 38 32 75 15 13 10 -
-
220 44 37 230 46 39 305 61 52 225 45 38 455 91 77 240 48 41 95 19 16 10 -
-
265 53 45 280 56 48 370 74 63 270 54 46 550 110 94 285 57 48 110 22 19 10 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
CL =15pF CL = 50pF nCP1 to nQ1 tPLH, tPHL CL = 50pF
5 6 2 4.5 6
nCP1 to nQ2
tPLH, tPHL
CL = 50pF
2 4.5 6
nCP1 to nQ3
tPLH, tPHL
CL = 50pF
2 4.5 5 6
nCP0 to nQ3 (nQ0 connected to nCP1)
tPLH, tPHL
CL = 50pF
2 4.5 6
MR to Qn
tPLH, tPHL
CL = 50pF
2 4.5
CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF
5 6 2 4.5 6
Input Capacitance Power Dissipation Capacitance (Notes 4, 5)
CIN CPD
CL = 50pF CL =15pF
5
6
CD74HC390, CD54/74HCT390
Switching Specifications Input tr, tf = 6ns
PARAMETER HCT TYPES Propagation Delay (Figure 1) nCP0 to nQ0 nCP1 to nQ1 nCP1 to nQ2 nCP1 to nQ3 (Continued) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
TEST SYMBOL CONDITIONS
tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL
CL = 50pF CL =15pF CL = 50pF CL = 50pF CL = 50pF CL =15pF
4.5 5 4.5 4.5 4.5 5 4.5 4.5 5 4.5 5
-
17 18 18 32
40 43 55 42 84 42 15 10 -
-
50 51 69 53 105 53 19 10 -
-
60 65 83 63 126 63 22 10 -
ns ns ns ns ns ns ns ns ns ns pF pF
nCP0 to nQ2 (nQ0 connected to nCP1) MR to Qn
tPLH, tPHL tPLH, tPHL
CL = 50pF CL = 50pF CL =15pF
Output Transition Input Capacitance Power Dissipation Capacitance (Notes 4, 5) NOTES:
tTLH, tTHL CL = 50pF CIN CPD CL =15pF CL =15pF
4. CPD is used to determine the dynamic power consumption, per multiplexer. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
tf = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% 3V
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
tr = 6ns INPUT GND
GND
tTHL
tTLH 90% 50% 10% tPHL tPLH
tTHL
INVERTING OUTPUT
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
7
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Copyright (c) 2000, Texas Instruments Incorporated

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