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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
D D D D D D D D
Synchronous Counting and Loading Two Count-Enable Inputs for n-Bit Cascading Asynchronous Reset (CD54HC160) Synchronous Reset (CD54HC162) Look-Ahead Carry for High-Speed Counting Operating Range 2-V to 6-V VCC EPICTM (Enhanced-Performance Implanted CMOS) Process Packaged in Ceramic (F) DIPs
CD54HC160, CD54HC162 . . . F PACKAGE (TOP VIEW)
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RCO QA QB QC QD ENT LOAD
description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix), and are characterized for operation over the full military temperature range of -55C to 125C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
logic symbol
CD54HC160 BINARY COUNTER WITH DIRECT CLEAR 1 9 10 7 2 3 4 5 6 CTRDIV10 CT=0 M1 M2 G3 G4 C5/2,3,4+ 1,5D [1] [2] [4] [8] CD54HC162 BINARY COUNTER WITH SYNCHRONOUS CLEAR 1 9 10 7 2 3 4 5 6 CTRDIV10 5CT=0 M1 M2 G3 G4 C5/2,3,4+ 1,5D [1] [2] [4] [8] 14 13 12 11 QA QB QC QD 15 14 13 12 11 QA QB QC QD 15
CLR LOAD ENT ENP CLK A B C D
3CT=9
RCO
CLR LOAD ENT ENP CLK A B C D
3CT=9
RCO
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
CD54HC160 logic diagram (positive logic)
CLR LOAD ENT 1 9 10 15 RCO
ENP 7
CLK 2 C1 1D R A 3 14 QA
C1 1D R B 4
13
QB
C1 1D R C 5
12
QC
C1 1D R D 6
11
QD
CD54HC162 decade counter is similar; however, the clear is synchronous.
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
logic diagram, each D/T flip-flop (positive logic)
ENT
Q
Q CL p LOAD n CL p p n n p CL CLR D CL CL p n CL CL CLR CL CL p n CL n
CLK Connect to VDD for CD54HC162.
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence: 1. Clear outputs to zero (CD54HC160 is asynchronous; CD54HC162 is synchronous) 2. Preset BCD to seven 3. Count to eight, nine, zero, one, two, and three 4. Inhibit
CD54HC160, CD54HC162 CLR
LOAD A
Data Inputs
B C
D
CLK ENP
ENT QA QB Outputs QC QD RCO 7 8 9 0 1 Count Sync Preset Clear 2 3 Inhibit
Async Clear
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < -0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < -0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = -0.5 V to VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation, PD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265C Lead temperature, unit inserted into a PC board (minimum thickness 1,6 mm, 1/16 inch) with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 100C, derate linearly at a factor of 8 mW/C.
recommended operating conditions (see Note 3)
MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tr, tf Low-level input voltage Input voltage Output voltage Input transition rise or fall times VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 0 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V MAX 6 UNIT V
TA Operating free-air temperature -55 125 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN 2V IOH = -20 mA VOH IOH = -4 mA IOH = -5.2 mA IOL = 20 mA VOL IOL = 4 mA IOL = 5.2 mA II ICC CIN VI = VCC or GND VI = VCC or GND, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8 10 TA = 25C TYP MAX CD54HC160 CD54HC162 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1 160 10 V V MAX UNIT
mA mA
pF
timing requirements over recommended operating free-air temperature range, VCC = 2 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN fmax tw Maximum frequency Pulse duration CLK CLK low CLR low ('160 only) Data (A, B, C, and D) ENP, ENT tsu Setup time before CLK LOAD low CLR ('162 only) CLR high ('160 only) Data (A, B, C, and D) th Hold time after CLK ENP, ENT LOAD low 6 80 100 60 50 60 65 75 3 0 3 MAX CD54HC160 CD54HC162 MIN 4 120 150 90 75 90 100 110 3 0 3 ns ns MAX MHz ns UNIT
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
timing requirements over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN fmax tw Maximum frequency Pulse duration CLK CLK low CLR low ('160 only) Data (A, B, C, and D) ENP, ENT tsu Setup time before CLK LOAD low CLR ('162 only) CLR high ('160 only) Data (A, B, C, and D) th Hold time after CLK ENP, ENT LOAD low 30 16 20 12 10 12 13 15 3 0 3 MAX CD54HC160 CD54HC162 MIN 20 24 30 18 15 18 20 22 3 0 3 ns ns MAX MHz ns UNIT
timing requirements over recommended operating free-air temperature range, VCC = 6 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN fmax tw Maximum frequency Pulse duration CLK CLK low CLR low ('160 only) Data (A, B, C, and D) ENP, ENT tsu Setup time before CLK LOAD low CLR ('162 only) CLR high ('160 only) Data (A, B, C, and D) th Hold time after CLK ENP, ENT LOAD low 35 14 17 10 9 10 11 13 3 0 3 MAX CD54HC160 CD54HC162 MIN 24 20 26 15 13 15 17 19 3 0 3 ns ns MAX MHz ns UNIT
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
switching characteristics over recommended operating free-air temperature range, VCC = 2 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPHL tTLH tTHL FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25C MIN MAX 185 185 185 185 120 120 210 210 75 75 CD54HC160 CD54HC162 MIN MAX 280 280 280 280 180 180 315 315 110 110 ns ns ns UNIT
CLK CLK ENT
RCO Q RCO Q ('160 only)
CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
CLR
ns
RCO ('160 only)
ns
switching characteristics over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPHL tTLH tTHL FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25C MIN MAX 37 37 37 37 24 24 42 42 15 15 CD54HC160 CD54HC162 MIN MAX 56 56 56 56 36 36 63 63 22 22 ns ns ns UNIT
CLK CLK ENT
RCO Q RCO Q ('160 only)
CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
CLR
ns
RCO ('160 only)
ns
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
switching characteristics over recommended operating free-air temperature range, VCC = 6 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPHL tTLH tTHL FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25C MIN MAX 31 31 31 31 20 20 36 36 13 13 CD54HC160 CD54HC162 MIN MAX 48 48 48 48 31 31 54 54 19 19 ns ns ns UNIT
CLK CLK ENT
RCO Q RCO Q ('160 only)
CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
CLR
ns
RCO ('160 only)
ns
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CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 - JUNE 2000
PARAMETER MEASUREMENT INFORMATION
VCC S1 RL = 1 k PARAMETER ten tPZH tPZL tPHZ tPLZ tpd or tt LOAD CIRCUIT CLR Input VCC 50% VCC 0V trec VCC VOH 50% VCC 10% V OL tf 90% tr tPZL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B) 50% VCC tPLZ VCC 50% 10% tPHZ 90% VOH 0 V VOH VOL Output Control 50% VCC 50% VCC 0V VCC VOL CLK 50% VCC 0V VOLTAGE WAVEFORMS RECOVERY TIME VCC S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open
From Output Under Test CL (see Note A)
Test Point
tdis S2
VCC Input 50% VCC tPLH In-Phase Output 50% VCC 10% tPHL Out-of-Phase Output 90% 50% VCC 10% tf 90% tr tPLH 50% VCC 10% 50% VCC 0V tPHL 90%
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Input
50% 10%
90%
90%
VCC 50% VCC 10% 0 V tf
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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