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SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
A B QA QB QC QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC QH QG QF QE CLR CLK
SN54LV164A . . . FK PACKAGE (TOP VIEW)
B A NC VCC QH QA NC QB NC QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
The 'LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation.
QG NC QF NC QE
NC - No internal connection
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. The SN54LV164A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV164A is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
QD GND NC CLK CLR
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SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
FUNCTION TABLE INPUTS CLR L H H H H CLK X L A X X H L X B X X H X L QA L QA0 H L L OUTPUTS QB . . . QH L QB0 QAn QAn QAn L QH0 QGn QGn QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = the level of QA or QG before the most recent transition of the clock: indicates a 1-bit shift
logic symbol
CLR CLK 9 8 SRG8 R C1/
A B
1 2
& 1D
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
CLK 8
A B
1 2
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
CLR
9 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
typical clear, shift, and clear sequences
CLR Serial Inputs A B CLK QA QB QC Outputs QD QE QF QG QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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3
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV164A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 0 0 0 0 0 MAX 5.5 SN74LV164A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV164A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 0V 3.3 V 2.2 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 2.2 TYP MAX SN74LV164A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 A A A pF V TYP MAX UNIT
VOH
V
VOL
II ICC Ioff Ci
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data before CLK Setup time Hold time CLR inactive Data after CLK 6 6.5 6.5 3 -0.5 SN54LV164A MIN 6.5 7.5 8.5 3 0 MAX SN74LV164A MIN 6.5 7.5 8.5 3 0 MAX UNIT ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data before CLK Setup time Hold time CLR inactive Data after CLK 5 5 5 2.5 0 SN54LV164A MIN 5 5 6 2.5 0 MAX SN74LV164A MIN 5 5 6 2.5 0 MAX UNIT ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw tsu th Pulse duration CLR low CLK high or low Data before CLK Setup time Hold time CLR inactive Data after CLK 5 5 4.5 2.5 1 SN54LV164A MIN 5 5 4.5 2.5 1 MAX SN74LV164A MIN 5 5 4.5 2.5 1 MAX UNIT ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd tPHL tpd tPHL CLK CLR CLK CLR Q Q Q Q CL = 50 pF CL = 15 pF FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN 55* 45 TA = 25C TYP MAX 105* 85 9.2* 8.6* 11.5 10.8 17.6* 16* 21.1 19.5 SN54LV164A MIN 50* 40 1* 1* 1 1 20* 18* 24 22 MAX SN74LV164A MIN 50 40 1 1 1 1 20 18 24 22 ns MAX UNIT MHz
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd tPHL tpd CLK CLR CLK Q FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF MIN 80* 50 TA = 25C TYP MAX 155* 120 6.4* 6* 8.3 12.8* 12.8* 16.3 16.3 SN54LV164A MIN 65* 45 1* 1* 1 1 15* 15* 18.5 18.5 MAX SN74LV164A MIN 65 45 1 1 1 1 15 15 18.5 18.5 MAX UNIT MHz
ns ns
tPHL CLR 7.9 * On products compliant to MIL-PRF-38535, this parameter is not production tested.
Q
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd tPHL tpd CLK CLR Q FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF CL = 50 pF CL = 15 pF MIN 125* 85 TA = 25C TYP MAX 220* 165 4.5* 4.2* 9* 8.6* 11 10.6 SN54LV164A MIN 105* 75 1* 1* 1 1 10.5* 10* 12.5 12.5 MAX SN74LV164A MIN 105 75 1 1 1 1 10.5 10 12.5 12.5 MAX UNIT MHz
ns ns
CLK 6 Q CL = 50 pF tPHL CLR 5.8 * On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 SN74LV164A MIN TYP 0.28 -0.22 3.09 MAX 0.8 -0.8 UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation ca acitance dissi ation capacitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz VCC 3.3 V 5V TYP 48.1 47.5 UNIT pF F
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403C - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 50% VCC tPHZ VOH - 0.3 V VOH 0V 50% VCC 0V VCC VOL + 0.3 V VOL
tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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