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SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
* * * * * *
10KH Compatible ECL and TTL Control Inputs Noninverting Outputs Flow-Through Architecture Optimizes PCB Layout Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include "Small Outline" Packages and Standard Plastic 300-mil DIPs
DW OR NT PACKAGE (T0P VIEW)
1Q 2Q 3Q 4Q VCC GND GND GND 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
1D 2D 3D 4D OE (TTL) VEE GND LE (ECL) 5D 6D 7D 8D
description
This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The eight latches of the SN10KHT5573 are transparent D-type latches. While latch enable (LE) is low, the Q outputs follow the data (D) inputs. When LE is high, the Q outputs are latched at the levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Output-enable OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN10KHT5573 is characterized for operation from 0 to 75C.
FUNCTION TABLE OUTPUT CONTROL OE L L L H LE L L H X DATA INPUT D L H X X OUTPUT (TTL) Q L H Q0 Z OE 1D 2D 3D 4D 5D 6D 7D 8D
logic symbol
LE 17 20 24 23 22 21 16 15 14 13 ECL/TTL EN 1D ECL/TTL 1 2 3 4 4Q 9 10 11 12 5Q 6Q 7Q 8Q 1Q 2Q 3Q C1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1990, Texas Instruments Incorporated
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* DALLAS, TEXAS 75265
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SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
logic diagram (positive logic)
OE LE 20 17 ECL/TTL 1 C1 1D 24 ECL/TTL 1D 2 C1 2D 23 ECL/TTL 1D 3 C1 3D 22 ECL/TTL 1D 4 C1 4D 21 ECL/TTL 1D 9 C1 16 5D ECL/TTL 1D 10 C1 15 6D ECL/TTL 1D 11 C1 7D 14 ECL/TTL 1D 12 C1 8D 13 ECL/TTL 1D 7Q 6Q 5Q 4Q 3Q 2Q 1Q
8Q
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 8 V to 0 V Input voltage range, TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.2 V to 7 V Input voltage range, ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range, TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA to 5 mA Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN VCC VEE VIH VIL IIK VIH TTL supply voltage ECL supply voltage TTL high-level input voltage TTL low-level input voltage TTL input clamp current 0C ECL high-level input voltage (see Note 2) 25C 75C 0C VIL IOH IOL ECL low-level input voltage (see Note 2) High-level output current Low-level output current 25C 75C - 1170 - 1130 - 1070 - 1950 - 1950 - 1950 4.5 - 4.94 2 0.8 - 18 - 840 - 810 - 735 - 1480 - 1480 - 1450 - 15 48 mA mA mV mV NOM 5 - 5.2 MAX 5.5 - 5.46 UNIT V V V V mA
TA Operating free-air temperature 0 75 C NOTE 2: The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
POST OFFICE BOX 655303
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SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK II IIH IIL IIH OE only OE only OE only OE only Data inputs and LE VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, IIL Data inputs and LE VCC = 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS VEE = - 4.94 V, VEE = - 5.46 V, VEE = - 5.46 V, VEE = - 5.46 V, VEE = - 5.46 V, VEE = - 5.46 V, VEE = - 5.46 V, VEE = - 5.46 V, IOH = - 3 mA, IOH = - 15 mA, IOL = 48 mA, VO = 2.7 V, VO = 0.5 V, VO = 0 V, VEE = - 5.46 V VEE = - 5.46 V VEE = - 5.46 V VEE = - 5.46 V II = - 18 mA VI = 7 V VI = 2.7 V VI = 0.5 V VI = - 840 V VI = - 810 V VI = - 735 V VI = - 1950 V VEE = - 5.2 V 5% VEE = - 5.2 V 5% VEE = - 5.2 V 5% VEE = - 5.46 V VEE = - 5.46 V VEE = - 5.46 V - 100 62 78 75 - 34 5 7 0C 25C 75C 0C 25C 75C VOH VOL IOZH IOZL IOS ICCH ICCL ICCZ IEE Ci 0.5 0.5 0.5 2.4 2 3.3 3.1 0.38 0.55 50 - 50 - 225 89 111 108 - 48 V V A A mA mA mA mA mA pF pF A MIN TYP MAX - 1.2 0.1 20 - 0.5 350 350 350 A UNIT V mA A mA
VCC = 5 V, VEE = - 5.2 V Co VCC = 5 V, VEE = - 5.2 V All typical values are at VCC = 5 V, VEE = - 5.2 V, and TA = 25C. Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements
VCC = 4.5 V to 5.5 V, VEE = - 4.94 V to - 5.46 V, TA = MIN to MAX MIN tw tsu Pulse duration, LE high Setup time, data before LE 4 1 MAX ns ns ns
UNIT
th Hold time, data after LE 1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1)
FROM (INPUT) TO (OUTPUT) CL = 50 pF, R1 = 500 , R2 = 500 , TA = MIN to MAX MIN TYP MAX 1.9 2.3 2.2 2.6 1.1 2.3 1.8 0.6 3.9 4.2 4 4.5 3.2 4.6 4 3.4 6.4 6.8 6.7 7.2 5.9 7.8 5.9 6.5
PARAMETER
UNIT
tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ
D LE OE OE
Q Q Q Q
ns ns ns ns
All typical values are at VCC = 5 V, VEE = - 5.2 V, and TA = 25C.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN10KHT5573 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE TRANSPARENT LATCHES AND 3-STATE OUTPUTS
SDZS015 - MAY 1990 - REVISED OCTOBER 1990
PARAMETER MEASUREMENT INFORMATION
7V Open S1 R1 From Output Under Test CL (See Note A) R2 Test Point SWITCH POSITION TABLE TEST tPLH tPHL tPZH tPZL tPHZ tPLZ S1 Open Open Open Closed Open Closed
LOAD CIRCUIT tr ECL Input (See Note B) 80% 80% 50% 20% tPHL Out-of-Phase TTL Output 1.5 V tPLH In-Phase TTL Output 1.5 V tf -890 mV 50% 20% tPLH VOH 1.5 V VOL tPHL VOH 1.5 V VOL VOLTAGE WAVEFORMS ECL-INPUT PROPAGATION DELAY TIMES tr Timing Input tsu Data Input 20% tr VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 80% 80% 50% 20% 80% 80% 50% 50% Output Control (Low-Level Enabling) (See Note C) 3V 1.5 V tPZL tPLZ tf 20% -890 mV -1690 mV tPZH -890 mV 50% 20% tf -1690 mV Output Waveform 2 (See Note D) tPHZ Output Waveform 1 (See Note D) 1.5 V VOL 0.3 V VOH 1.5 V 0.3 V 0 3.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATION -1690 mV Low-Level Input 50% High-Level Input -890 mV 50% tw -890 mV 50% -1690 mV 50% -1690 mV
th
VOLTAGE WAVEFORMS TTL ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr 1.5 ns, tf 1.5 ns. C. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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