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TLV320AIC27 EVM
User's Guide
August 2000
AAP Data Conversion
SLAU051
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Trademarks
Preface
Read This First
About This Manual
This manual presents the user's guide for the TLV320AIC27 evaluation module.
How to Use This Manual
This document contains the following chapters and appendixes: Chapter 1 - System Description Chapter 2 - Modes of Operation Appendix A -TLV320AIC27 Register Block Diagram Appendix B -DSP Interface Appendix C -Audio Control Block Diagram Appendix D -EVM Shared Clock Configuration Appendix E -Serial Interface Register Map Appendix F -Software Drivers Appendix G -PC Board and Bill of Materials Appendix H -Schematics
Trademarks
All trademarks are the property of their respective owners.
Read This First
iii
Running Title--Attribute Reference
Contents
1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TLV320AIC27 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 TLV320AIC27 Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.1 Summary of the Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.2 Jumper List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.1 DSP DSK Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.2 TLV320AIC27 EVM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.6 DSP-CODEC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction to the TLV320AIC27 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Basic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Six-Channel I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Quad Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Modem Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Power Supply Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 DSP Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Power Connections When not Using the DSP as a Controller . . . . . . . . . . . . . 2-1 2-2 2-2 2-3 2-4 2-5 2-6 2-6 2-6
2
A B
TLV320AIC27 Register Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 DSP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 DSP Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Audio Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1 Audio-Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 EVM Shared Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1 Shared Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 Serial Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1 F.1 Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 PC Board and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1 G.1 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-2 G.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-8 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1
C
D
E F
G
H
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 2-4 TLV320AIC27 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Pin 96 to DSK J9-13 Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Connection of J9-17 to 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 DSP-CODEC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Basic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Six-Channel I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Quad Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Modem Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Tables
1-1 2-1 E-1 Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 TLV320AIC27 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Serial Interface Register Map Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
vi
Chapter 1
System Description
Topic
1.1 1.2 1.3 1.4 1.5 1.6
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TLV320AIC27 Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 TLV320AIC27 Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 DSP-CODEC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
System Description
1-1
Introduction
1.1 Introduction
The TLV320AIC27 EVM is designed to be a daughterboard that directly plugs into the peripheral connector of any or TI's DSP DSK or EVM boards that have the 80-pin common-connector configuration. The TLV320AIC27 EVM also has an AMR connector available for use without the need of a DSP as a controller. The AIC27 EVM board is populated with one TLV320AIC27 device. The EVM is powered by either a 3.3-V or a 5-V power supply. The TLV320AIC27 is a high-performance, AC'97 compliant audio CODEC specifically designed for use with TIs digital-signal processors (DSPs). This new 18-bit linear DSP codec transmits data at up to 48 kilosamples per second, contains a powerful serial interface, has four modes of operation, allows for variable sampling rates, and consumes only 139 mW of power at 3.3 V. This CODEC is well suited for audio applications such as telecommunications, surround sound, teleconferencing, and USB. The TLV320AIC27 EVM manual assumes that the user has a working knowledge of Revision 2.1 of the AC97 CODEC standard.
1-2
TLV320AIC27 Device Block Diagram
1.2 TLV320AIC27 Device Block Diagram
Figure 1-1 shows the block diagram of the TLV320AIC27.
Figure 1-1. TLV320AIC27 Block Diagram
VOL/ MUTE VOL/ MUTE VOL/ MUTE
REV. 2.1 SWITCH
VOL/ MUTE
(35,36) LINEOUT (FRONT)
VOL/ MUTE
MUX
VOL/ MUTE
(39,41) LINEOUT (REAR) (37) MONOOUT
VOL/ MUTE
VOL/ MUTE KEY: MONO STEREO VOL/ MUTE
REAR STEREO DAC
SRC (40) MODE1
FRONT STEREO DAC
(30) MODE0 SRC (47) EAPD
VOL/ MUTE VOL/ MUTE VOL/ MUTE VOL/ MUTE VOL/ MUTE
3D
TLV320AIC27 CODEC
SERIAL I/F
(6) BITCLK (10) SYNC (8) SDATAIN (5) SDATAOUT
STEREO ADC
(11) RESETB
CD (18,20) LINEIN (23,24) VIDEO (16,17) AUX (14,15) PHONE (13) PCBEEP (12) MIC[1] (21) MIC[2] (22) MUX
VOL RECORD MUX AND MUTE 0dB/ 20dB
SRC
MASTER/ SLAVE SELECT General IO Supprt
(45) CID[0] (46) CID[1] (43,44,48) GPIO[1:3]
OSC
(2) XTLIN (3) XTLOUT
System Description
1-3
EVM Layout
1.3 EVM Layout
Figure 1-2 shows the EVM layout
Figure 1-2. EVM Layout
J45 J46 J1 J5 J9 J15
GND MITSUMI_CD EXTERNAL DACS +5V MIC2 VIDEO +3.3V J22 +12V SYNC RESET SDATA_IN SDATA_OUT BITCLK J18 J21 J19 J20 AIC 27 AUX SONY_CD
PHONE DIVIDE-DOWN CIRCUITRY J35 J38 MONO_OUT MASTERCLK
BREADBOARD AREA DSP/CODEC CLOCK GENERATION
GPIO
J17
HEADPHONE AMP
AMR CONN.
1-4
TLV320AIC27 Jumper Description
1.4 TLV320AIC27 Jumper Description
The TLV320AIC27 EVM is designed to provide maximum flexibility to end users. It can be used with any DSP design kit that uses the common 80-pin connector as the controller. However, this EVM can also be used with a controller other than the DSP by using the AMR connector that allows access to critical signals and clocks. Control signals and clocks are also available to users via connectors and jumpers.
1.4.1
Summary of the Jumpers
Refer to the EVM schematics in Appendix H for the desired position of jumpers. Quad and six-channel I2S mode (jumpers J1-J12): The quad and six-channel I2S modes use external DACs. These jumpers offer users the flexibility to use these external DACs and to configure the surroundsound options as desired. SYNC pulse generation (jumpers J13-J15, J29-J31): There is more than one way to configure the DSP and CODEC. These jumpers provide flexibility in creating the SYNC pulse from BITCLOCK, and provide reset capability. Mode selection (jumpers J19-J20): These jumpers provide users control of the desired mode selection. Refer to the TLV320AIC27 data sheet and section 2.1 of this user's manual for more information. Power options (jumpers J21, J22, J43-J44): These jumpers are used for the selection of the power options. Shared master clock (jumpers J16-J18): These jumpers are used to control the shared master-clock options. DSP/CODEC configuration (jumpers J23, J24, J34, J36, J37, J39-J41): These jumpers provide users access to signals and clocks to allow flexibility in configuring the DSP or any other controller with the TLV320AIC27 CODEC.
Table 1-1. Jumper Description
TLV320AIC27 DELIVERED DEFAULT JUMPER POSITIONS J18 J22 J23 J36 J39 J7 J17 J44 J19 J20 DSP 1.8-V master clock DSP regulator SYNC signal RESETB signal SDATA_IN0 3-V or 5-V option CODEC 3.3-V master clock 5 V from DSP power Mode pin Mode pin Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Pins 1-2 shorted Open Open
System Description
1-5
TLV320AIC27 Jumper Description
1.4.2
Jumper List
JUMPER J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J16 J17 J18 J19 J20 J21 J22 J24 J36 J34 J37 J23 J39 J40 J41 J43 J44 J31 J32 J33 J28 29 J15 J14 J13 J42 J26 NAME D1_GPIO1 D1_GPIO3 D1_BITCLOCK D1_FORMAT D1_DEEMPH D1_MUTE D2_GPIO1 D2_GPIO2 D2_BITCLOCK D2_MUTE D2_DEEMPH D2_FORMAT CODEC_CRYSTAL CODEC_MC DSP_MC MODE0 MODE1 5V_ISOL DSP_REG SDATAOUT RESETB CRYSTAL X_FSRO SYNC SDATA_IN0 X_CLKXO X_CLKRO 12V 5V DIVIDE_IN DIVIDE_HI DIVIDE_RESET DIVIDE_HIJ DIVIDE_RESET DIVIDE_G DIVIDE_OUT DIVIDE_G_OUT STEP_UP_IN STEP_UP_OUT DESCRIPTION DAC #1 GPIO1 pin DAC #1 GPIO3 pin DAC #1 BITCLOCK DAC #1 format control DAC #1 DEEMPH control DAC #1 mute control DAC #2 GPIO1 pin DAC #2 GPIO2 pin DAC #2 BITCLOCK DAC #2 mute control DAC #2 DEEMPH control DAC #2 format control Control to onboard CODEC-only crystal Control to onboard DSP-only crystal Control to onboard DSP-only crystal Mode control pin 30 Mode control pin 40 Prevent 5 V to regulator Sets up DSP for needed voltages Serial data out of DSP Reset Master clock for AMR connector DSP frame-sync receive control AC97 sync control DSP serial data into DSP DSP CLK transmit DSP clock receive 12-V control 5-V control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Create frame-sync-circuitry control Step-up clock level control Step-up clock level control
1-6
Getting Started
1.5 Getting Started
1.5.1 DSP DSK Setup
This procedure uses the TI C5402 DSK. If another 80-pin common-connector type DSP DSK is used instead of the C5402, refer to the specific manuals for the necessary signal connections to the board. This getting-started procedure uses a configuration of DSP and AIC27 CODEC running from the same clock (see Shared Clock Configurations in Appendix D). Complete the following two steps: 1) On the TI DSP5402 DSK, remove crystal Y2 and capacitors CAP57 and CAP70. A connection needs to be made from pin 96 of the DSP to J9-13 of the DSP DSK. The now unused crystal pad closest to pad CAP70 can be used to connect to DSP pin 96. This connection to J9-13 will allow the CODEC EVM master clock to be connected to the DSP (see Figure 1-3).
Figure 1-3. Pin 96 to DSK J9-13 Connection
DSP PIN 96
13 J9
2) Connect J9-17 to the 1.8-V solder connection. This connection allows 1.8 V to be used on the CODEC EVM board (see Figure 1-4). a) Power up the C5402 DSK board and place the DSK with the side with the rubber feet facing up. b) With a voltmeter, measure the 1.8 V from the solder connection as shown below. c) Connect a wire from J9-17 to the 1.8-V solder connection as shown below.
System Description
1-7
Getting Started
Figure 1-4. Connection of J9-17 to 1.8 V
Rubber Foot 1.8-V Solder Connection
J9-17
3) Connect the DSP DSK's parallel port to the PC using the DSK cable provided. 4) Set the dip switch (SW1) on the DSP DSK accordingly: a) If using parallel port DSP to PC connector, 1 = Down 2 = Down 3 = Down 4 = Up 5 = Down 6 = Up 7 = Down 8 = Down b) If using DSP JTAG to PC connector, 1 = UP 2 = Down 3 = Down 4 = Up 5 = Down 6 = Up 7 = Down 8 = Down
1-8
Getting Started
1.5.2
TLV320AIC27 EVM Setup
1) Attach the TLV320AIC27 EVM board to the DSP 5410 DSK using the two common 80-pin connectors. 2) Connect the following jumpers on the TLV320AIC27 EVM: a) J7 - Selects either 3 V or 5 V b) J17 - Codec master clock (3.3 V) c) J18 - DSP master clock (1.8 V) d) J22 - DSP regulator e) J23 - SYNC signal f) J36 - RESETB signal (short two pins) (short two pins) (short two pins) (short two pins) (short two pins) (short two pins) (short two pins) (short two pins) (open) (open)
g) J39 - SDATA_IN0 h) J44 - 5 V from DSP power i) j) J19 - Mode pin J20 - Mode pin
3) Turn power on DSP DSK (power to both DSP DSK and CODEC EVM from DSP power). 4) Load Code Composer Studio. 5) Under File, select Load Program. Load AIC27driver.out (updates located on TI web site). 6) Under Project, select Open and Load AIC27driver.mak (updates located on TI web site). 7) Hit F5 (Run) or select Run under Debug. 8) To stop the program from running, select Halt under Debug. 9) To make changes to signal path, programmable gain amplifier (PGA), or modes, edit file taic27_ob.c contained in directory Project/Source (displayed in code composer). Refer to data sheet for register descriptions and values. The serial interface register map is located in Appendix E. 10) The TLV320AIC27 EVM has the available hardware on board to run in configurations b and c, as shown in Figure 1-5.
System Description
1-9
DSP-CODEC Configurations
1.6 DSP-CODEC Configurations
Figure 1-5 illustrates three possible DSP and CODEC configurations. They are: 1) DSP and CODEC sharing the same master clock. This is the configuration used in this manual. The configurations used to drive both DSP and CODEC are shown in Appendix D. 2) DSP and CODEC sharing the same master clock, with the CODEC in secondary mode. To place the CODEC in secondary mode, populate R9 with a resistor with a value between 1 and 50 . Both FRAME SYNC and BITCLOCK are from the DSP. 3) The DSP and CODEC run at their own unique master clocks. The frame sync is created by the BITCLOCK by divide-down circuitry provided on the EVM board. Jumpers 13 to 15, and 29 to 31 are used to implement this configuration. Refer to the schematics on page 8 of Appendix H for additional information.
1-10
DSP-CODEC Configurations
Figure 1-5. DSP-CODEC Configurations
X_FSX (23) D S P a) Shared Clock X_DX0 X_DR0 (30) X_XF (49) X2/CLKIN SYNC BIT_CLK SDATA_OUT SDATA_IN RESET XTL_IN CID0 CID1 C O D E C Primary NC NC
24.576 MHz Crystal X_FSX (23) X_FSR (29) X_CLKX0(21) X_DX0 X_DR0 (30) X_XF (49) X2/CLKIN SYNC C O D E C Secondary NC GND
D S P b) Secondary Mode
BIT_CLK
SDATA_OUT SDATA_IN CID0 RESET CID1 XTL_IN
24.576 MHz Crystal
D S P c) Frame Sync Generator
X_FSX (23) X_FSR (29) X_CLKX0(21) X_DX0 X_DR0 (30) X_XF (49) X2/CLKIN /256 DSP Crystal
SYNC C O D E C Primary NC NC
BIT_CLK
SDATA_OUT SDATA_IN CID0 RESET CID1 XTL_IN
24.576 MHz Crystal
System Description
1-11
Chapter 2
Modes of Operation
This chapter describes the modes of operation of the TLV320AIC27 EVM.
Topic
2.1 2.2 2.3 2.4 2.5 2.6
Page
Introduction to the TLV320AIC27 Modes . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Basic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Six-Channel I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Quad Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Modem Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Power Supply Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Modes of Operation
2-1
Introduction to the TLV320AIC27 Modes
2.1 Introduction to the TLV320AIC27 Modes
The TLV320AIC27 has four modes of operation. The EVM will allow any of the four modes by configuring jumpers J19 and J20. The four modes are: 1) Basic two-channel mode 2) I2S six-channel mode 3) Quad mode 4) Modem mode
Table 2-1. TLV320AIC27 Modes
Mode1 J20 0 0 1 1 Mode0 J19 0 1 0 1 Operational Mode Basic Six-channel I2S Quad Modem Resulting Device Behavior Two-channel mode codec Six-channel I2S mode codec Quad DAC mode (with I2S six-channel support) Modem DAC mode
2.2 Basic Mode
The basic mode is illustrated in Figure 2-1.
Figure 2-1. Basic Mode
Slot 3 PCM LEFT Slot 4 PCM RIGHT
One stereo DAC available in basic mode
Digital/Analog Audio Input
AIC27 CODEC LINEOUTL LINEOUTR LNLVLOUT LNLVROUT 35 36 39 41
Data placed on LINEOUT will be the same on LNLVOUT
MODE0 = 0 MODE1 = 1
2-2
Six-Channel I 2S Mode
2.3 Six-Channel I2S Mode
Figure 2-2. Six-Channel I 2S Mode
Slot 3 PCM LEFT Slot 4 PCM RIGHT Slot 7 PCM SURROUND LEFT Slot 8 PCM SURROUND RIGHT Slot 6 PCM CENTER Slot 9 PCM LFE External 5V 13 14 1 2 48 44 43 5V 9 35 FRONT 36 14 39 MODE0 = 1 MODE1 = 0 1 FRONT 41 2 3 Insert jumpers J1, J2, J3, J7, J8, and J9. Use jumpers J4, J5, J6, J10, J11, and J12 for FORMAT, DEEMPH, and MUTE options by selecting either high or low. Register 3Eh, bit0 set to 0 Register 5Ah, bit 7 set to 1 (I2S enable) SDATA BCKIN VOUTL 9 Rear LRCLK SCLK WM8725 VOUTR 6 Rear 5V 13
I2S Data I2S Data
FORMAT SCLK WM8725 LRCLK SDATA BCKIN VDD 8 CAP 5 GND 7 10 F VOUTL 9 LFE Data VOUTR 6 Center Data
AIC27 CODEC GPIO3 GPIO2 GPIO1 BIT_CLK
3
External FORMAT
VDD 8 5V
CAP 5
GND 7
10 F
Modes of Operation
2-3
2-4
Quad Mode
2.4 Quad Mode
Figure 2-3. Quad Mode
Modes of Operation
Slot 3 PCM left Slot 4 PCM right Slot 7 PCM surround left Slot 8 PCM surround right Slot 6 PCM center Slot 9 PCM LFE
NC 4
NC 11
External DAC #1 AVD 13 14 1 2 J1 9 J2 48 J3 43 44 35 36 39 41 Rear L/R AVD AGN Front L/R 10 F
I2S Data
FORMAT SCLK LRCLK SDATA BCKIN WM8725 9 LFE Data 3.5 mm Jack VOUTR 6 Center Data
AIC27 CODEC BIT_CLK GPIO3 GPIO1 GPIO2 LINEOUT LINEOUTR LNLVLOUT LNLVLOUTR
VOUTL
3
DEEMPH 12 GND
MUTE 10 GND
VDD 8
CAP 5
GND 7 Insert jumpers J1, J2, J3
10 F
Use jumpers J4, J5, J6 for FORMAT, DEEMPH, and MUTE options by selecting either high or low. Register 3Eh, bit 0 set to 0; register 5Ah, bit 7 set to 1 (I2S enabled).
MODE0 = 0 MODE1 = 1
0.1 F
2.5 Modem Mode
Figure 2-4. Modem Mode
5V 640 k 1% 200 k AIC27 JM1 JM2 GPIO GPIO GPIO 43 44 48 JM6 LNLVL_R LNLVL_L PHONE 41 39 13 R3 150 k GND_M 0.1 F 0.1 F 0.1 F JM3 JM4 JM5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C6 0.1 F 32 31 30 29 28 R4 27 150 k 26 25 24 23 22 21 20 19 18 17 C28 0.47 F R5 10M C7 0.001 F 500 V R6 10 k GND_M B1 + - AC AC
VCC TXF1 TX- TX+ TX NC GND OH RING CID RX- RX+ SNP+ SNP- RXF RX CPC560
BR- TXF2 ZTX ZNT TXS BR- NTS GAT REF DCS DCF ZDC BR- RFB RXS VDD
GND_M
Q1 CPC5602C
R64 1.2 M R89 100 R86 806 k 1% R83 8.2 GND_M R84 300 R85 R105 10
R106 10
Hardware shown for modem mode is not provided on TLV320AIC27 EVM board. This schematic view is provided to illustrate how the TLV320AIC27 would be used in modem mode. Slot 3 PCM left Slot 4 PCM right Slot 7 PCM surround left Slot 8 PCM surround right Slot 6 PCM center Slot 9 PCM LFE Slot 5 Line 1 DAC Slot 10 Line 2 DAC R90 1 M C10 220 pF 2 kV R91 1.5 M
Modes of Operation
2-5
C27 0.01 F
R87 806 k 1% GND_M F1 C16 JM7 4.7 nF J1 1 2 3 4 5 6
Modem Mode
220 pF 2 kV 1.5 M
FUSE D1 P3200SB
L4 Bead GND_M L3 Bead
220 pF 220 pF
L1 Bead
L2 Bead
Power Supply Description
2.6 Power Supply Description
The TLV320AIC27 EVM receives its power from the DSP EVM board. The voltages supplied to the EVM from the DSP are 1.8 V, 3.3 V, 5 V, and 12 V. The voltage sources are as follows:
- The 1.8 V comes from the DSP (5-V power plug regulated to 1.8 V). - The 3.3 V comes from the DSP (5-V power plug regulated to 3.3 V). - The 5 V comes from the DSP. - The 12 V comes from the AUX power connection on the DSP.
The voltage used on the EVM is DVDD (digital) and AVDD (analog), and VDSP18 (DSP clock voltage). DVDD is either 3.3 V or 5 V, as determined by a jumper (J7) which comes from the DSP. AVDD is 5 V, and comes from either the DSP by using J44, or from the 12-V AUX power connector on the DSP, which is regulated to 5 V on the CODEC EVM board using J43.
2.6.1
DSP Power Options
If using external 12 V from the DSP DSK AUX connector:
- Connect J43 (short pins 1 and 2) and J21 (short pins 1 and 2).
If using 5 V from the DSP power supply:
- Connect J44 (short pins 1 and 2) and leave J21 off.
2.6.2
Power Connections When Not Using the DSP as a Controller
- Use the 12-V, 5-V, and 3.3-V connections available on the breadboard
area as required.
2-6
Appendix A
TLV320AIC27 Register Block Diagram
This appendix presents the TLV320AIC27 register block diagram.
TLV320AIC27 Register Block Diagram
A-1
A-2
C3D1 C3D2 BITCLK (6) 2 X 18 Front Audio Data REAR Rear Audio Data Modem Data Quad or Modem Mode DAC ADC 2 X 18 (10) (8) (5) (11) (1) (4) (9) (7) SYNCH SDIN SDOUT NRES (33) Digital Sigma FRONT Delta Variable Rate Audio Support DAC Interpolation Filters Serial Loopback Reg 20h (34) DVDD1&2 DVSS1&2 Multibit DAC and Filter DACR FRONT DAC PGA PGA Reg 18h FRONT Multibit DAC and Filter DACL 3D ENHANCE REAR DAC PGA PGA Reg 70h ADC CLK FRONT MIXER PGA ADC Decimation filters PGA Reg 0Ah Multibit DAC and Filter DACR REAR EAPD (47) IDO (45) IDI (46) MODE1 (40) MODE0 (30) GPIO3 (48) GPIO2 (44) GPIO1 (43) Multibit DAC and Filter DACL PGA Reg 02h PGA Reg 12h REAR MIXER PGA PGA Reg 0Ah Mono Mux 2.1 mode LINEOUTL (35) LINEOUTR (36) PGA Reg 0Ah LNLVLOUT (39) LNLVROUT (41) PGA Reg 0Ah MONOOUT (37) ADCNDAC L R ADC REF Analog Sigma Delta Modulator RECORD MUX Reg 1Ah PGA Reg 0Ah ADC CLOCK Analog Sigma Delta Modulator XTLIN (2) ADC CLK PR0 ADC EN PR1 DAC EN EN PR2 MIX EN Power Enable Reg 26h PR3 LNK EN PR4 ADC EN PR5 CLK EN EAPD AVSS1 (26) CAP2 (32) VREFOUT (28) VREF (27) AFILT1 (29) CAP1 (31) MIX REF DAC REF ADC REF XTLOUT (3) AVDD1 (25) AVDD2 (38) DAC CLOCK CLOCK GENERATOR Mic Mux +20 DB PGA Reg 0Eh
TLV320AIC27 Block Diagram
DAC REF
CDL (18)
TLV320AIC27 Register Block Diagram
PGA Reg 10h
VIDL (16)
VIDR (17)
PGA Reg 14h
AUXL (14)
AUXR (15)
PGA Reg 16h
PHONE (13)
PGA Reg 0Ch
PGA Reg 0Ah
MIC1 (21)
MIC2 (22)
Appendix B
DSP Interface
This appendix presents the DSP interface schematic diagram.
Topic
B.1
Page
TLV320AIC27 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
DSP Interface
B-1
B.1 DSP Interface Diagram
DSP INTERFACE 1.8 V 3.3 V 5V 12 V J6 1 3 5 7 NC CRYSTAL NC NC J38-11 9 11 13 15 17 19 X_CLKXO SYNC NC X_CLKRO X_FSRO NC X_CLKX1 J38-12 NC NC X_CLKR1 J38-13 NC NC X_TOUT J38-9 NC RESET NC NC NC NC NC NC NC NC NC NC NC NC J22 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 NC 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC J38-16 X_CLOCK NC NC J38-14 X_DX1 NC NC SDATA_IN NC NC J38-15 X_DR1 NC NC NC NC NC NC NC SDATAOUT NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 59 NC NC NC NC NC NC NC NC NC NC NC 63 65 67 69 71 73 75 77 79 61 51 53 55 57 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 J16 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
B-2
Appendix C
Audio Control Block Diagram
This appendix presents the audio-control block diagram.
Topic
C.1
Page
Audio Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Audio Control Block Diagram
C-1
Audio-Control Block Diagram
C.1 Audio-Control Block Diagram
AUDIO_IN LINE_IN_L LINE_IN_R AUX_IN_L AUX_IN_R VIDEO_IN_L VIDEO_IN_R CD_IN_L CD_IN_GND CD_IN_R MIC1_IN MIC2_IN PRIMARY_DN PHONE_IN SDATAIN BITCLK RESETB SYNC SDATAOUT TLV320AIC27 MSTRCLK PCBEEP AUDIO_OUT LINE_OUT_L LINE_OUT_R LINELVL_OUT_L LINELVL_OUT_R MONO_OUT
AMR_BUS
C-2
Appendix D
EVM Shared Clock Configuration
The following illustration shows the TLV320AIC27 shared clock configuration.
Topic
D.1
Page
Shared Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
EVM Shared Clock Configuration
D-1
Shared Clock Configuration
D.1 Shared Clock Configuration
1.8 V (J6-17) 14 1 2 7 SN74LVC04A DVDD OUT 4 3 SG8002DC 24.576 MHz Epson Oscillator 1 1 DVDD 2 DVDD 14 2 7 SN74LVC04A 'AIC27 J18 2 XTLIN J17 Crystal (To DSP)
D-2
Appendix E
Serial Interface Register Map
The following table shows the functions and addresses of the various control bits that are loaded through the serial interface during write operations.
Topic
E.1
Page
Serial Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
Serial Interface Register Map
E-1
E-2
Serial interface Register Map
Table E-1.Serial Interface Register Map Description
Reg 00h Name Reset Master volume Headphone volume Master volume mono PCBEEP volume Phone volume Mic volume Line-in volume CD volume Video volume Aux volume Front PCM out volume Receiver select Receiver gain General purpose 3D control Reserved Power-down ctrl/stat Extended audio ID Extended audio ctrl/stat Front DAC rate Rear DAC rate LFE DAC rate Audio ADC rate Six channel vol. C, LFE Six channel vol. L, R surround D15 X Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute X Mute POP X x EAPD ID1 X SR15 SR15 SR15 SR15 Mute Mute D14 SE4 X X X X X X X X X X X X X ST X x PR6 ID0 PRL SR14 SR14 SR14 SR14 x x D13 SE3 X X X X X X X X X X X X X 3D X x PR5 X PRK SR13 SR13 SR13 SR13 x x D12 SE2 ML4 ML4 X X X X GL4 GL4 GL4 GL4 GL4 X X lD X x PR4 X PRJ SR12 SR12 SR12 SR12 LFE4 LSR4 D11 SE1 ML3 ML3 X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X x PR3 X PRI SR11 SR11 SR11 SR11 LFE3 LSR3 D10 SE0 ML2 ML2 X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X x PR2 X X SR10 SR10 SR10 SR10 LFE2 LSR2 D9 ID9 ML1 ML1 X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X x PR1 Amap Madc SR9 SR9 SR9 SR9 LFE1 LSR1 D8 ID8 ML0 ML0 X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS X x PR0 Ldac Ldac SR8 SR8 SR8 SR8 LFE0 LSR0 D7 ID7 X X X X X X X X X X X X X LPBK X x X Sdac Sdac SR7 SR7 SR7 SR7 Mute Mute D6 ID6 X X X X X 20 dB X X X X X X X X X x X Cdac Cdac SR6 SR6 SR6 SR6 x x D5 ID5 X X X X X X X X X X X X X X X x X X X SR5 SR5 SR5 SR5 x x D4 ID4 MR4 MR4 MM4 PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X x X X X SR4 SR4 SR4 SR4 CNT4 RSR4 D3 ID3 MR3 MR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 X DP3 x REF VRM VRM SR3 SR3 SR3 SR3 CNT3 RSR3 D2 ID2 MR2 MR2 MM2 PV2 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X DP2 x ANL X X SR2 SR2 SR2 SR2 CNT2 RSR2 D1 ID1 MR1 MR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X DP1 x DAC DRA DRA SR1 SR1 SR1 SR1 CNT1 RSR1 D0 ID0 MR0 MR0 MM0 X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X DP0 x ADC VRA VRA SR0 SR0 SR0 SR0 CNT0 RSR0 Default 6150h 8000h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 8000h 0000h 0000h 000Fh 0281h 0080h BB80h BB80h BB80h BB80h 8080h 8080h
Serial Interface Register Map
02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 36h 38h
Table B-1.Serial Interface Register Map Description (Continued)
Reg 3Ch 3Eh 40h 42h 46h 48h 4Ch 4Eh 50h 52h 54h 56h 5Ah 70h 72h 74h Name Extended modem ID Extended modem stat Line1 sample rate ADC/ DAC Line2 sample rate ADC/ DAC Line1 DAC/ADC level Line2 DAC/ADC level GPIO pin configuration GPIO pin type GPIO pin sticky GPIO wake-up GPIO pin status Misc. modem ctrl/stat Vendor reserved test Rear PCM out volume Front mixer volume Rear mixer volume Vendor reserved Vendor ID1 Vendor ID2 0 1 0 0 0 CID2 ATST Mute Mute Mute X F7 T7 0 1 0 0 0 CID1 DTST x x x X F6 T6 GW13 GC13 GP13 GS13 GI13 CIDR AFTS x x x X F5 T5 GC12 GP12 GS12 GI12 MLNK DFTS GL4 GL4 GL4 X F4 T4 D15 ID1 PRH SR15 D14 ID0 PRG SR14 D13 x PRF SR13 D12 x PRE SR12 D11 x PD SR11 D10 x PRC SR10 D9 x PRB SR9 D8 x PRA SR8 D7 x HDAC SR7 D6 x HADC SR6 D5 x DAC2 SR5 D4 CID2 ADC2 SR4 D3 CID1 DAC1 SR3 D2 HSET D1 LIN2 D0 LIN1 GPIO SR0 Default x00xh 0100h BB80h
ADC1 MREF SR2 SR1
Sample rates written to 42h will alias onto 40h Not supported - set TX modem levels by writing to rear DAC PGA 04h Not supported - set TX modem levels by writing to rear DAC PGA 04h GW12 GW1 GC11 GP11 GS11 GI11 x RTST GL3 GL3 GL3 X F3 T3 0 1 0 0 0 HSB2 DDS GL2 GL2 GL2 X F2 T2 0 1 0 0 0 HSB1 AMD GL1 GL1 GL1 X F1 T1 0 1 0 0 0 HSB0 DLM GL0 GL0 GL0 X F0 T0 0 1 0 0 0 x I2S x x x X S7 Rev7 0 1 0 0 0 L2B2 R2S x x x X S6 Rev6 0 1 0 0 0 L2B1 AND x x x X S5 Rev5 0 1 0 0 0 L2B0 HIM GR4 GR4 GR4 X S4 Rev4 0 1 0 0 0 x HIC GR3 GR3 GR3 X S3 Rev3 0 1 0 0 0 L1B2 TRM GR2 GR2 GR2 X S2 Rev2 0 1 0 0 0 L1B1 BB GR1 GR1 GR1 X S1 Rev1 0 1 0 0 0 L1B0 AEV GR0 GR0 GR0 X S0 Rev0 000Eh FFFFh 0000h 0000h 000xh 0000h 0000h 0808h 8808h 8808h X 574Dh 4C0xh
Serial Interface Register Map
E-3
7Ah 7Ch 7Eh
Serial Interface Register Map
Appendix F
Software Drivers
This appendix presents the software drivers.
Topic
F.1
Page
Software Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2
Software Drivers
F-1
F.1 Software Drivers
The TLV320AIC27 software package may be downloaded from the TLV320AIC27 EVM product page web site.
F-2
Appendix G
PC Board and Bill of Materials
This appendix contains the pc-board layout and bill of materials for the TLV320AIC27 evaluation module.
Topic
G.1 G.2
Page
PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-8
PC Board and Bill of Materials
G-1
PC Board
G.1 PC Board
G-2
PC Board
PC Board and Bill of Materials
G-3
PC Board
G-4
PC Board
PC Board and Bill of Materials
G-5
PC Board
G-6
PC Board
PC Board and Bill of Materials
G-7
Bill of Materials
G.2 Bill of Materials
Item Reference Qty Value Foot Print Manufacturer Part Number
1 2
C1 C17, C15, C16, C53, C54, C57, C58 C19, C10, C11, C18, C39, C40, C51, C52, C56, C60, C55, C59 C2, C4, C14, C25, C27, C29, C31, C33, C43, C44, C61, C62, C64, C65 C20, C23 C22 C3, C5, C6, C7, C12, C13, C21, C24, C26, C28, C30, C32, C67, C68, C69, C70, C71, C72 C35, C36, C37, C38, C41, C42, C45, C50, C34 C8, C9 J6, J16 J1, J5, J9, J15, J45, J56 J10, J11, J12 J17, J18, J19, J20, J21, J22 J2 J23, J24, J25, J26, J27, J28, J29, J30, J31, J32, J33, J34, J36, J37, J39, J40, J41, J42, J43, J44
1 7
0.33 F 2.2 F
CAP0805 CAP0805
Panasonic or equivalent Panasonic or equivalent
Digi-Key # PCC1817CT-ND PCC1923CT-ND
3
12
220 pF
CAP0805
Panasonic or equivalent
PCC221CGCT-ND
4
14
10uFX 16 V
4MM x 7MM
XICON
MOURSER 140-MLRL16V10
5 6 7
2 1 18
22 pF 47 nF 0.1 F
CAP0805 CAP0805 CAP0805
Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent
PCC1973CT-ND PCC1808CT-ND PCC1812CT-ND
8
9
0.47 F
CAP0805
Panasonic or equivalent
PCC1818CT-ND
9 10 11 12 13 14 15
2 2 6 4 6 1 20
330 F x 16 V
8MM x 11MM CON\80P\TFM JACK_35
XICON SAMTEC MOUSER LEOCO
MOURSER 140XRL16V330 TFM-140-31-S-D 161-3504 HDR1X4V-2MM LTI-SASF54GT
RF connector
SMA
Lighthorse Technologies or equivalent PCB AMR_CONNECTOR
2 POS JMPR
SIP\2P
SAMTEC
TSW-102-07-L-S.1" spacing
G-8
Bill of Materials
Item 16 Reference JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8, JP9, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19, JP20, JP21, JP22 J3, J8, J13 J10, J11, J12 J14 J4 J7 J35, J38 JMP_C1 Qty 22 Value 2-POS JMPR Foot Print SIP\2P Manufacturer SAMTEC Part Number TSW-102-07-L-S .1" spacing
17 18 19 20 21 22 23
3 3 1 1 1 2 1
2-Pin HDR 4-Pin HDR 4-Pin RT HDR 6-PIN HDR
HDR1X2V-2MM HDR1X4V-2MM HDR1X4H-2MM HDR1X6V-2MM HDR1X3 SIP\16 SIP\3P
LEOCO LEOCO LEOCO LEOCO SAMTEC SAMTEC SAMTEC
2011P02V000 2011P04V000 2550P04HU00 2011P06V000
TSW-116-07-L-D .1" spacing SAMTEC TSW-103-07-L-S .1" spacing
24 25 26 27 28 29 30 31 32
JMPM0-1 L1 R10, R26 R1, R2 R13, R19, R20, R25, R9 R18, R6, R46, R48 R21, R17 R27 R3, R4, R7, R15, R16, R54, R55, R23, R24, R58, R59 R30, R31, R32, R33, R34, R35, R40, R41, R43, R28, R29, R49, R50, R51, R52, R53 R36, R37, R38, R39 R44 R47 R5, R11, R42, R45, R14, R12, R22, R56, R57
2 1 2 2 5 4 2 1 11 1K, 1% 22R1, 1% UNPOP 10K, 1% 51R1, 1% 2K21, 1% 47K5, 1%
JUMPER1 Chip 1206 RES0805 RES0805 RES0805 RES0805 RES0805 RES0805 RES0805 Steward Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Digi-Key 240-1019-1-ND Digi-Key P/N P1.00K CCT- ND P22.1CCT-ND N/A P10KCCT-ND P51.1CCT-ND P2.21K P47.5KCCT-ND
33
16
8K25 1%
RES0805
Panasonic or equivalent
P8.25KCCT-ND
34 35 36 37
4 1 1 9
1K5 1% 11K, 1% 13K, 1% 220R, 1%
RES0805 RES0805 RES0805 RES0805
Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent Panasonic or equivalent
P1.5KCCT-ND P11KCCT-ND P13KCCD-ND P220CCT-ND
PC Board and Bill of Materials
G-9
Bill of Materials
Item 38 39 Reference R8 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9 U1 U2 U3 U4 U5 U6 U7 U8 U9, U10 U11, U12 Qty 1 9 Value 20K, 1% Foot Print RES0805 Test point Manufacturer Panasonic or equivalent SAMTEC Part Number P20KCCT-ND TWS-101-07-L-S .025" pin LM78L05ACZ NC7SZ66 TPA112D TLV320AIC27 SN74HC08 SN74HC32 SN74HC4060 SN65LVDS9637 WM8725 SN74LVC04A
40 41 42 43 44 45 46 47 48 49 50 51 52
1 1 1 1 1 1 1 1 2 2 SN74LVC04AD TPA112D TLV320AIC27-PFB SN74HC08D SN74HC32D SN74HC4060D SN65LVDS9637D
National National TI TI TI TI TI TI WOLFSON MICRO. TI
X1 X2
1 1
24.576 MHz 24.576 MHz
CTS or Equv EPSON
HC-94 SG-8002DC- PCC-24.576 MHz
G-10
Appendix H
Schematics
This appendix contains the schematics for the TLV320AIC27 evaluation board.
Topic
H.1
Page
TLV320AIC27 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-3
Schematics
H-1

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