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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
D D D D D
Push-Pull CMOS Output Drives Capacitive Loads Without Pullup Resistor, IO = 8 mA Very Low Power . . . 200 W Typ at 5 V Fast Response Time . . . tPLH = 2.7 s Typ With 5-mV Overdrive Single Supply Operation . . . 3 V to 16 V TLC3704M . . . 4 V to 16 V On-Chip ESD Protection
D, J, OR N PACKAGE (TOP VIEW)
1OUT 2OUT VDD 2IN - 2IN + 1IN - 1IN +
1 2 3 4 5 6 7
14 13 12 11 10 9 8
3OUT 4OUT GND 4IN + 4IN - 3IN + 3IN -
description
The TLC3704 consists of four independent micropower voltage comparators designed to operate from a single supply and be compatible with modern HCMOS logic systems. They are functionally similar to the LM339 but use 1/20th the power for similar response times. The push-pull CMOS output stage drives capacitive loads directly without a power-consuming pullup resistor to achieve the stated response time. Eliminating the pullup resistor not only reduces power dissipation, but also saves board space and component cost. The output stage is also fully compatible with TTL requirements. Texas Instruments LinCMOSTM process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages with large differential input voltages. This characteristic makes it possible to build reliable CMOS comparators.
FK PACKAGE (TOP VIEW)
VDD NC 2IN - NC 2IN +
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2OUT 1OUT NC 3OUT 4OUT GND NC 4IN + NC 4IN - 1IN- 1IN+ NC
IN + OUT IN - NC - No internal connection
symbol (each comparator)
The TLC3704C is characterized for operation over the commercial temperature range of 0C to 70C. The TLC3704I is characterized for operation over the extended industrial temperature range of - 40C to 85C. The TLC3704M is characterized for operation over the full military temperature range of - 55C to 125C. The TLC3704Q is characterized for operation from - 40C to 125C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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3IN- 3IN+
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
AVAILABLE OPTIONS TA 0C to 70C - 40C to 85C - 55C to 125C - 40C to 125C VIOmax at 25C 5 mV 5 mV 5 mV 5 mV PACKAGE SMALL OUTLINE (D) TLC3704CD TLC3704ID -- -- CERAMIC (FK) -- -- TLC3704MFK -- CERAMIC DIP (J) -- -- TLC3704MJ TLC3704QJ PLASTIC DIP (N) TLC3704CN TLC3704IN -- --
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC3704CDR).
functional block diagram (each comparator)
VDD
IN+ Differential Input Circuits IN- OUT
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC3704C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70C TLC3704I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C TLC3704M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C TLC3704Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN -.
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DISSIPATION RATING TABLE PACKAGE D FK J N TA 25C POWER RATING 950 mW 1375 mW 1375 mW 1150 mW DERATING FACTOR ABOVE TA = 25C 7.6 mW/C 11.0 mW/C 11.0 mW/C 9.2 mW/C TA = 70C POWER RATING 608 mW 880 mW 880 mW 736 mW TA = 85C POWER RATING 494 mW 715 mW 715 mW 598 mW TA = 125C POWER RATING N/A 275 mW 275 mW N/A
recommended operating conditions
TLC3704C MIN Supply voltage, VDD Common-mode input voltage, VIC High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 0 3 - 0.2 NOM 5 MAX 16 VDD - 1.5 - 20 20 70 UNIT V V mA mA C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER VIO IIO IIB Input offset voltage Input offset current Input bias current TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, See Note 3 VIC = 2 5 V 2.5 VIC = 2 5 V 2.5 TA 25C 0C to 70C 25C 70C 25C 70C 25C VICR Common-mode Common mode input voltage range 0C to 70C 25C CMRR Common-mode rejection ratio VIC = VICRmin 70C 0C 25C kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 70C 0C VOH VOL IDD High-level High level output voltage Low level output voltage Low-level Supply current (all four comparators) VID = 1 V V, VID = -1 V, 1V Outputs low low, IOH = - 4 mA IOH = 4 mA No load 25C 70C 25C 70C 25C 0C to 70C 35 4.5 4.3 210 300 375 80 100 0 to VDD - 1 0 to VDD - 1.5 84 84 84 85 85 85 4.7 V mV A dB dB 5 0.6 1 0.3 TLC3704C MIN TYP 1.2 MAX 5 6.5 UNIT mV pA nA pA nA
V
All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
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recommended operating conditions
TLC3704I MIN Supply voltage, VDD Common-mode input voltage, VIC High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA - 40 3 - 0.2 NOM 5 MAX 16 VDD - 1.5 - 20 20 85 UNIT V V mA mA C
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted)
PARAMETER VIO IIO IIB Input offset voltage Input offset current Input bias current TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, See Note 3 VIC = 2 5 V 2.5 VIC = 2 5 V 2.5 TA 25C - 40C to 85C 25C 85C 25C 85C 25C VICR Common-mode Common mode input voltage range - 40C to 85C 25C CMRR Common-mode rejection ratio VIC = VICRmin 85C - 40C 25C kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 85C - 40C VOH VOL IDD High-level High level output voltage Low-level Low level output voltage Supply current (all four comparators) VID = 1 V V, VID = -1 V, 1V Outputs low, low IOH = - 4 mA IOH = 4 mA No load 25C 85C 25C 85C 25C - 40C to 85C 35 4.5 4.3 210 300 400 80 125 0 to VDD - 1 0 to VDD - 1.5 84 84 83 85 85 83 4.7 V mV A dB dB 5 2 1 1 TLC3704I MIN TYP 1.2 MAX 5 7 UNIT mV pA nA pA nA
V
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
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recommended operating conditions
TLC3704M MIN Supply voltage, VDD Common-mode input voltage, VIC High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA - 55 4 0 NOM 5 MAX 16 VDD - 1.5 - 20 20 125 UNIT V V mA mA C
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted)
PARAMETER VIO IIO IIB Input offset voltage Input offset current Input bias current TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, See Note 3 VIC = 2 5 V 2.5 VIC = 2 5 V 2.5 TA 25C - 55C to 125C 25C 125C 25C 125C 25C VICR Common-mode Common mode input voltage range - 55C to 125C 25C CMRR Common-mode rejection ratio VIC = VICRmin 125C - 55C 25C kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 125C - 55C VOH VOL IDD High-level High level output voltage Low-level Low level output voltage Supply current (all four comparators) VID = 1 V V, VID = -1 V, 1V Outputs low, low IOH = - 4 mA IOH = 4 mA No load 25C 125C 25C 125C 25C - 55C to 125C 35 4.5 4.2 210 300 500 80 175 0 to VDD - 1 0 to VDD - 1.5 84 83 82 85 85 82 4.7 V mV A dB dB 5 30 1 15 TLC3704M MIN TYP 1.2 MAX 5 10 UNIT mV pA nA pA nA
V
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
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recommended operating conditions
TLC3704Q MIN Supply voltage, VDD Common-mode input voltage, VIC High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA - 40 3 - 0.2 NOM 5 MAX 16 VDD - 1.5 - 20 20 125 UNIT V V mA mA C
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted)
PARAMETER VIO IIO IIB VICR Input offset voltage Input offset current Input bias current Common-mode input voltage g range TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, See Note 3 VIC = 2 5 V 2.5 VIC = 2 5 V 2.5 TA 25C - 40C to 125C 25C 125C 25C 125C 25C - 40C to 125C 25C CMRR Common-mode rejection ratio VIC = VICRmin 125C - 40C 25C kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 125C - 40C VOH VOL IDD High level output voltage High-level Low-level Low level output voltage Supply current (all four y ( comparators) VID = 1 V V, VID = -1 V, 1V Outputs low, low IOH = - 4 mA IOH = 4 mA No load 25C 125C 25C 125C 25C - 40C to 125C 35 4.5 4.2 210 300 500 80 175 0 to VDD - 1 0 to VDD - 1.5 84 83 83 85 85 83 4.7 V mV A dB dB 5 30 1 15 TLC3704Q MIN TYP 1.2 MAX 5 7 UNIT mV pA nA pA nA V
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
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switching characteristics, VDD = 5 V, TA = 25C
PARAMETER TEST CONDITIONS Overdrive = 2 mV Overdrive = 5 mV tPLH Propagation delay time, low-to-high-level output time low to high level f = 10 kH kHz, CL = 50 pF F Overdrive = 10 mV Overdrive = 20 mV Overdrive = 40 mV VI = 1.4-V step at IN + Overdrive = 2 mV Overdrive = 5 mV tPHL Propagation delay time, high-to-low-level output time high to low level f = 10 kH kHz, F CL = 50 pF Overdrive = 10 mV Overdrive = 20 mV Overdrive = 40 mV VI = 1.4-V step at IN + f = 10 kHz, Overdrive = 50 mV CL = 50 pF f = 10 kHz, CL = 50 pF Overdrive = 50 mV TLC3704C, TLC3704I TLC3704M, TLC3704Q MIN TYP 4.5 2.7 1.9 1.4 1.1 1.1 4 2.3 1.5 0.95 0.65 0.15 50 125 ns ns s s MAX UNIT
tf tr
Fall time Rise time
Simultaneous switching of inputs causes degradation in output response.
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PRINCIPLES OF OPERATION LinCMOS process
The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI ESD-protection circuit is presented on the next page. All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through a 1500- resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor (charged device model). These tests simulate both operator and machine handling of devices during normal test and assembly operations.
VDD R1 Input R2 Q1 Q2 To Protected Circuit
D1
D2
D3
GND
Figure 1. LinCMOS ESD-Protection Schematic
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PRINCIPLES OF OPERATION input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on the VDD pin by a value equal to the VBE of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 to 27 V, which is well below the gateoxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is - 0.3 V to -1 V (the forward voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is 5 mA. Figures 2 and 3 show typical characteristics for input voltage versus input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. Again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limit the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 4).
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PRINCIPLES OF OPERATION circuit-design considerations (continued)
INPUT CURRENT vs INPUT VOLTAGE
8 TA = 25 C 7 6 5 4 3 2 1 0 VDD 9 8 I I - Input Current - mA I I - Input Current - mA 7 6 5 4 3 2 1 VDD + 4 VDD + 8 VDD + 12 0 VDD - 0.3 10 TA = 25 C
INPUT CURRENT vs INPUT VOLTAGE
VDD - 0.5
VDD - 0.7
VDD - 0.9
VI - Input Voltage - V
VI - Input Voltage - V
Figure 2
VDD
Figure 3
RI VI Vref + 1/2 TLC3704
Positive Voltage Input Current Limit : RI
-
* + V * V5 mA 0.3 V
I DD
See Note A
Negative Voltage Input Current Limit : V I V DD (* 0.3 V) RI 5 mA
+* *
*
NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required.
Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
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PARAMETER MEASUREMENT INFORMATION
The TLC3704 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo loop which is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 5(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy.
5V 1V
+
+
Applied VIO Limit
- VO
Applied VIO Limit
- VO
-4V (a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V
Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any residual d.c. offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R8 and R9 provides an increase in the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be one percent or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device.
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PARAMETER MEASUREMENT INFORMATION
VDD IC1a 1/4 TLC274CN + Buffer C2 1 F - - DUT R4 47 k + R7 1.8 k 1% + Integrator R6 1 M R5 1.8 k 1% C3 0.68 F
IC1c 1/4 TLC274CN - VIO (X100)
R1 240 k
IC1b 1/4 TLC274CN - C1 0.1 F +
C4 0.1 F
Triangle Generator
R9 100 1%
R8 10 k 1%
R3 100
R2 10 k
Figure 6. Circuit for Input Offset Voltage Measurement Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV overdrive, causes the output to change state.
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PARAMETER MEASUREMENT INFORMATION
VDD
Pulse Generator 50 1V 10 10-Turn Potentiometer + DUT - 1 k 0.1 F
1 F
CL (see Note A)
-1V
TEST CIRCUIT
Overdrive
Overdrive
Input
100 mV
Input
100 mV
90% Low-to-High Level Output 50% 10% High-to-Low Level Output
90% 50% 10%
tr tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance.
tf tPHL
Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE VIO IIB CMRR kSVR VOH VOL tt Input offset voltage Input bias current Common-mode rejection ratio Supply-voltage rejection ratio High-level High level output current Low level output voltage Low-level Transition time Supply current response Low-to-high-level output response High-to-low level output response tPLH tPHL IDD Low-to-high level output propagation delay time High-to-low level output propagation delay time Supply current y Distribution vs Free-air temperature vs Free-air temperature vs Free-air temperature vs Free-air temperature vs High-level output current vs Low-level output current vs Free-air temperature vs Load capacitance vs Time Low-to-high level output propagation delay time High-to-low level output propagation delay time vs Supply voltage vs Supply voltage vs Frequency q y vs Supply voltage g vs Free-air temperature 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DISTRIBUTION OF INPUT OFFSET VOLTAGE
200 180 160 Number of Units 140 120 100 80 60 40 20 0 -5 10
INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE
VDD = 5 V VIC = 2.5 V IIB - Input Bias Current - nA 1
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14
C EEECCCCCE CCEECE EE EECCCEEEC EEE C CCECECE ECCE EC CCCC C EEE EE CCCC C E CCC C E CCC C E CE C CC C CE E E
-4 -3 -2 -1 0 1 2 3 4 VIO - Input Offset Voltage - mV
VDD = 5 V VIC = 2.5 V TA = 25 C 698 Units Tested From 4 Wafer Lots
0.1
0.01
0.001 5 25 50 75 100 125 TA - Free-Air Temperature - C
Figure 8
Figure 9
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
90 CMRR - Common-Mode Rejection Ratio - dB 88 86 84 82 80 78 76 74 72 70 - 75 - 50 - 25 0 25 50 75 100 125 VDD = 5 V k SVR - Supply Voltage Rejection Ratio - dB 90 88 86 84 82 80 78 76 74 72 70 - 75 VDD = 5 V to 10 V
SUPPLY VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE
- 50
- 25
0
25
50
75
100
125
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
5 4.95 VOH - High-Level Outout Voltage - V 4.9 4.85 4.8 4.75 4.7 4.65 4.6 4.55 4.5 - 75 - 50 VOH - High-Input Level Output Voltage -V VDD = 5 V IOH = - 4 mA VDD - 0.25 - 0.5 - 0.75 -1
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
VDD = 16 V
10 V
5V - 1.25 - 1.5 - 1.75 -2 TA = 25C 0 - 2.5 -5 - 7.5 3V 4V
- 25
0
25
50
75
100
125
- 10 - 12.5 - 15 - 17.5 - 20
TA - Free-Air Temperature - C
IOH - High-Level Output Current - mA
Figure 12
Figure 13
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
1.5 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - mV TA = 25C 1.25 3V 4V 400 350 300 250 200 150 100 50 0 - 75 VDD = 5 V IOL = 4 mA
LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
1 5V 0.75 10 V 0.5
0.25
VDD = 16 V
0 0 2 4 6 8 10 12 14 16 18 20 IOL - Low-Level Output Current - mA
- 50
- 25
0
25
50
75
100
125
TA - Free-Air Temperature - C
Figure 14
OUTPUT TRANSITION TIME vs LOAD CAPACITANCE
250 225 200 tt - Transition Time - ns 175 150 125 100 Output Voltage - V 75 50 25 0 0 200 400 600 800 1000 CL - Load Capacitance - pF 5 Fall Time Rise Time VDD = 5 V TA = 25C 10 IDD - Supply Current - mA
Figure 15
SUPPLY CURRENT RESPONSE TO AN OUTPUT VOLTAGE TRANSITION
VDD = 5 V CL = 50 pF f = 10 kHz
5
0
0
t - Time
Figure 16
Figure 17
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
TYPICAL CHARACTERISTICS
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES HIGH-TO-LOW-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES
5 VO - Output Voltage - V
5 VO - Output Voltage - V 40 mV 20 mV 10 mV 5 mV 2 mV 40 mV 20 mV 10 mV 5 mV 2 mV 0 VDD = 5 V TA = 25 C CL = 50 pF
0
100 Differential Input Voltage - mV Differential Input Voltage - mV
100
0
VDD = 5 V TA = 25 C CL = 50 pF 0 1 2 3 4 5
0
0
1
2
3
4
5
tPLH - Low-to-High-Level Output Response Time - s
tPHL - High-to-Low-Level Output Response Time - s
Figure 18
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE
6 CL = 50 pF TA = 25C 5 Overdrive = 2 mV t PLH - Low-to-High-Level Output Response - s t PHL - High-to-Low-Level Output Response - s 5 6 CL = 50 pF TA = 25C
Figure 19
HIGH-TO-LOW-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE
Overdrive = 2 mV 4
4
3
5 mV 10 mV
3 5 mV 2 10 mV 20 mV 1 40 mV
2 20 mV 1 40 mV 0
0
2
4
6
8
10
12
14
16
0
0
2
4
6
8
10
12
14
16
VDD - Supply Voltage - V
VDD - Supply Voltage - V
Figure 20
Figure 21
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT (PER COMPARATOR) vs FREQUENCY
10000 TA = 25C CL = 50 pF VDD - Supply Current - A VDD = 16 V 1000 10 V 80 70 60 50 40 30 20 10 3V 10 0.01 0.1 1 f - Frequency - kHz 10 100 0 0 2 4 6 8 10 12 14 16 TA = 85C TA = 25C Outputs Low No Loads TA = - 55C TA = - 40C
SUPPLY CURRENT vs SUPPLY VOLTAGE
VDD - Average Supply Current - A
5V 100 4V
TA = 125C
VDD - Supply Voltage - V
Figure 22
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
30 VDD = 5 V No Load
Figure 23
25 IDD - Supply Current -A
20 Outputs Low 15
10 Outputs High 5
0 - 75
- 50
- 25
0
25
50
75
100
125
TA - Free-Air Temperature - C
Figure 24
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
APPLICATION INFORMATION
The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range. For example, at 25C with VDD = 5 V, both inputs must remain between - 0.2 V and 4 V to ensure proper device operation. To ensure reliable operation, the supply should be decoupled with a capacitor (0.1 F) that is positioned as close to the device as possible. Output and supply current limitations should be watched carefully since the TLC3704 does not provide current protection. For example, each output can source or sink a maximum of 20 mA; however, the total current to ground can only be an absolute maximum of 60 mA. This prohibits sinking 20 mA from each of the four outputs simultaneously since the total current to ground would be 80 mA. The TLC3704 has internal ESD-protection circuits that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. Table of Applications
FIGURE Pulse-width-modulated motor speed controller Enhanced supply supervisor Two-phase nonoverlapping clock generator Micropower switching regulator 25 26 27 28
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
APPLICATION INFORMATION
12 V SN75603 Half-H Driver
5V
DIR
1/2 TLC3704 + 10 k 5V - 10 k C1 0.01 F (see Note B) - 1/2 TLC3704 See Note A 100 k +
EN
Motor
12 V DIR 5V 10 k Motor Speed Control Potentiometer SN75604 Half-H Driver
10 k
EN
5V Direction Control
S1 SPDT
NOTES: A. The recommended minimum capacitance is 10 F to eliminate common ground switching noise. B. Adjust C1 for change in oscillator frequency
Figure 25. Pulse-Width-Modulated Motor Speed Controller
20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
APPLICATION INFORMATION
5V
12 V 12-V Sense 3.3 k + 1 k - 1/2 TLC3704
VCC
SENSE
5V 10 k
RESIN
TL7705A
RESET
To P Reset
REF 2.5 V 1 F 1/2 TLC3704 + V(UNREG) (see Note A) R1 - R2 To P Interrupt Early Power Fail
CT
GND
CT (see Note B)
Monitors 5 VDC Rail Monitors 12 VDC Rail Early Power Fail Warning
NOTES: A.
V (UNREG)
+R2) + 2.5 (R1R2
B. The value of CT determines the time delay of reset.
Figure 26. Enhanced Supply Supervisor
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TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
APPLICATION INFORMATION
12 V R1 100 k (see Note B) - R2 5 k (see Note C) 12 V 1/2 TLC3704 OUT1 +
12 V
-
1/2 TLC3704
100 k
+ 22 k - C1 0.01 F (see Note A) R3 100 k (see Note B)
1/2 TLC3704 OUT2
+
100 k
100 k
12 V
OUT1
OUT2
NOTES: A. Adjust C1 for a change in oscillator frequency where: 1/f = 1.85(100 k)C1 B. Adjust R1 and R3 to change duty cycle C. Adjust R2 to change deadtime
Figure 27. Two-Phase Nonoverlapping Clock Generator
22
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC3704, TLC3704Q QUAD MICROPOWER LinCMOSTM VOLTAGE COMPARATORS
SLCS117A - NOVEMBER 1986 - REVISED OCTOBER 1996
APPLICATION INFORMATION
+ 6 V to 16 V + 0.01 mA to 0.25 mA L (R1 ) R2) V + 2.5 O
V I I R2 1/2 TLC3704 + 100 k VI - 100 k C1 180 F (see Note A) + D IN5818 100 k - + 1/2 TLC3704 VI SK9504 (see Note C) GS VI 47 F Tantalum
100 k R1 100 k VI + R2 100 k 470 F
R=6 L = 1 mH (see Note D) VO
TLC271 (see Note B)
RL
-
C2 100 pF 100 k 270 k VI LM385 2.5 V
NOTES: A. Adjust C1 for a change in oscillator frequency B. TLC271 - Tie pin 8 to pin 7 for low bias operation C. SK9504 - VDS = 40 V IDS = 1 Awill D. To achieve microampere current drive, the inductance of the circuit must be increased.
Figure 28. Micropower Switching Regulator
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