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TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
D D D D
Supports UXGA Resolution (Output Pixel Rates up to 165 MHz) Digital Visual Interface (DVI 1.0) Specification1 Seamlessly Interfaces With IntelTM DVO Port on Whitney and Future IntelTM Chipsets Supports 24-bit RGB and YCrCb Input Formats on a 12-Bit Pixel Port
D D D D
Programmable Functionality and I2C Serial Interface Reduced Power Consumption - 1.8 V Digital Core and 3.3 V Analog Circuit Lowest Noise and Best Power Dissipation Using PowerPADTM Packaging Advanced Technology Using TI's 0.18 m EPIC-5TM CMOS Process
description
The TFP420 is a PanelBusTM flat panel display product, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop and notebook PCs, the TFP420 finds applications in any design requiring a high-speed digital interface with connectivity to the IntelTM DVO port.
PAP PACKAGE (TOP VIEW)
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DVSS CLKIN1 CLKIN0 DVDD DATA6 DATA7 DATA8 DATA9 DATA10 DATA11
DVDD BLANK VREF HSYNC VSYNC DVSS INT1 DVDDQ INT0 A0 HTPLG DVCC RST SDA SCL DVSS
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DVSS AVCC VS HS/CS/GPIO1 NC NC AVSS NC NC NC NC AVCC PVSS PVDD XTALO XTALI
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-5, PowerPAD, and PanelBus are trademarks of Texas Instruments. Intel is a trademark of Intel Corporation and Macrovision is a trademark of Macrovision Corporation. Other trademarks are property of their respective owners. 1. The Digital Visual Interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high-speed digital connection to digital displays. The TFP420 is compliant to the DVI specification Rev. 1.0.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEST GPIO0 TFADJ TVSS TX0- TX0+ TVDD TX1- TX1+ TVSS TX2- TX2+ TVDD TXC+ TXC- TVSS
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
description (continued)
The scalable (1.1 V to 1.8 V) low-swing digital pixel interface provides a low-EMI and high-speed bus that connects seamlessly with Intel's digital video out (DVO) port, perfectly linking the graphics controller and the DVI transmitter. The DVI interface supports display resolutions up to UXGA at 165 MHz in 24-bit true color pixel format. The TFP420 combines PanelBus TM circuit innovation, TI's advanced 0.18 m EPIC-5TM CMOS process technology, and PowerPADTM ultralow ground inductance package technology to provide a reliable, low-power, and low-noise digital interface solution.
functional block diagram
DVO I/F Video Port DVI Encoder DVI I/F
LTVDATA[11:0] De-Skew CLKOUT[1:0] BLANK VSYN HSYN Format Data
Encoder
Serializer
TX2
Encoder
Serializer
TX1
Encoder
Serializer
TX0
Control
TXC
SCL I2C Interface SDA PLL
XTAL2 XTAL1
2
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digital video out (DVO) interface diagram
Intel-Based Motherboard Intel Chipset TFP420
Graphics Controller
DVI
DVO I/F
Terminal Functions
TERMINAL NAME POWER RAIL NO. I/O DESCRIPTION
Digital Video Input Port BLANK CLKIN[1:0] DVDD DVDD 2 57, 56 I I Blanking signal - BLANK is low during blanking interval and high during active video. TFP420 uses CLKIN [1:0] to clock in video data and timing control signals. When used as a differential pair, CLKIN0 connects to the positive end and CLKIN1 connects to the negative end. For single-ended clock input, the clock is connected to CLKIN0 and a reference voltage of VDDQ/2 must be connected to CLKIN1. The graphics controller should use internal DOT clock to generate CLKIN[1:0]. DATA[11:0] HSYNC INT0 DVDD DVDD DVDD 49-54, 59-64 4 9 I I I/O DATA[11:0] is the pixel port Horizontal sync input Interrupt for hot plug support (output) INT0 is an open drain signal and an assertion low interrupt request informing the graphics controller of flat panel/TV/secondary monitor hot plug or hot unplug event. For normal applications, a 10K pullup resistor must be connected between this terminal and DVCC. Interrupt for hot plug support INT1 is an open drain signal and an assertion low interrupt request informing the graphics controller of flat panel/secondary monitor hot plug or hot unplug event. Digital video input port voltage reference sets the switching threshold of all the signals listed in digital video input port section of this table. VREF must be set to DVDDQ/2, where DVDDQ is the swing of the signals. DVDDQ ranges from 1.1 V to 1.8 V. Vertical sync input Terminal for reference crystal for the internal PLL. Leave unconnected if an external oscillator is connected to XTAL0. Terminal for reference crystal for the internal PLL or external reference oscillator input.
INT1
DVDD
7
O
VREF
DVDDQ/2
3
A
VSYNC Reference Crystal XTALI XTALO
DVDD PVDD PVDD
5 33 34
I I I
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SLDS123A - MARCH 2000 - REVISED JUNE 2000
Terminal Functions (Continued)
TERMINAL POWER NAME RAIL DVI Output TX2+ TX2- TX1+ TVDD TVDD TVDD 28 27 25 A A A Red channel positive transmitter output - Positive side of red channel T.M.D.S. low voltage signal differential output pair. Red channel transmits red pixel data in active display and 00 control bits in blank. Red channel negative transmitter output - Negative side of red channel T.M.D.S. low voltage signal differential output pair. Green channel positive transmitter output - Positive side of green channel T.M.D.S. low voltage signal differential output pair. Green channel transmits green pixel data in active display and 00 control bits in blank. Green channel negative transmitter output - Negative side of green channel T.M.D.S. low voltage signal differential output pair. Blue channel positive transmitter output - Positive side of blue channel T.M.D.S. low voltage signal differential output pair. Blue channel transmits blue pixel data in active display and HSYNC, VSYNC control signals in blank. Blue channel negative transmitter output - Negative side of blue channel T.M.D.S. low voltage signal differential output pair. Clock positive transmitter output - Positive side of reference clock T.M.D.S. low voltage signal differential output pair. Clock negative transmitter output - Negative side of reference clock T.M.D.S. low voltage signal differential output pair. T.M.D.S. drivers full scale adjust control A 2-k resistor must be connected between this terminal and TVSS. I2C slave address select General-purpose I/O #0 First general-purpose I/O. This terminal has an internal weak pulldown of 1 M (TBD). With GPIO0 as an input, use an external 10 k resistor to pull up or down to set the state of this terminal. Digital horizontal sync output - This is the HSYNC signal that connects to the VGA connector. Digital composite sync output - Composite HSYNC and VSYNC. The polarity of this signal is programmable when used for HS/CS. General-purpose I/O #1 - Second general-purpose I/O. This terminal has an internal weak pulldown of 1 M (TBD). With GPIO1 as an input, use an external 10-k resistor to pull up or down to set the state of this terminal. HTPLG NC RST SCL SDA TEST DVCC AVCC DVCC DVCC DVCC DVCC 11 38-41, 43, 44 13 15 14 17 I A I I/O I/O I DVI/P&D/DFP hot plug detect input Reserved Reset signal active low. I2C serial clock input maximum. Clock rate of 400 kHz. Open drained I/O. I2C Serial data line open drained I/O. Test mode enable This terminal must be tied to LOW for normal mode of operation. Connecting this terminal to HIGH puts TFP420 in test mode. Digital vertical sync output When the analog RGB video output is enabled this signal is the VSYNC that connects to the VGA connector. NO. I/O DESCRIPTION
TX1- TX0+
TVDD TVDD
24 22
A A
TX0- TXC+ TXC- TFADJ
TVDD TVDD TVDD TVDD
21 30 31 19
A A A A
I2C Interface and Miscellaneous A0 GPIO0 DVCC DVCC 10 18 I I/O
HS/CS/ GPIO1
AVCC
45
I/O
VS
AVCC
46
O
4
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Terminal Functions (Continued)
NAME TERMINAL POWER RAIL NO. I/O DESCRIPTION
Power and Ground AVCC AVSS DVCC DVDD DVDDQ DVSS PVDD PVSS TVDD TVSS 3.3 V 0.0 V 3.3 V 1.8 V 1.1 V-1.8 V 0.0 V 1.8 V 0.0 V 1.8 V 0.0 V 37, 47 42 12 1, 55 8 6, 16, 48, 58 35 36 23, 29 20, 26, 32 P G P P P G P G P G Analog power Analog ground Digital power Digital power Digital power Digital ground Power for PLLs Ground for PLLs Analog power for the DVI output drivers Analog ground for the DVI output drivers
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
External T.M.D.S. termination resistance, RLtmds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to open circuit External TFADJ resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 k to open circuit Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Maximum total power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions (ALL DATA PRELIMINARY)
MIN Digital supply voltage, DVDD Digital supply voltage, DVDDQ Analog supply voltage, AVCC Analog supply voltage, TVDD Analog supply voltage, PVDD Digital low-level input voltage, DVDD VIL (scalable with V(REF) Digital low-level input voltage, DVDD VIH (scalable with V(REF) Digital low-level input voltage, DVCC VIL Digital low-level input voltage, DVCC VIH Digital supply current, DVDD Digital supply current, DVDDQ DVI 1280x1024 resolution 60 Hz refresh rate Analog supply current, TVDD Analog supply current, AVCC Analog supply voltage, PVDD Reference voltage, V(REF) External T.M.D.S. termination resistor External TFADJ resistor Operating free-air temperature, TA 0.52 45 1.4 0 0.9 50 2 80 0 120 6 100 0.95 55 2.6 70 V k C mA V(REF)+100 mv 0.8 1.7 1.0 3.13 1.7 1.7 NOM 1.8 1.8 3.3 1.8 1.8 MAX 1.9 1.9 3.47 1.9 1.9 V(REF)-100 mv UNIT V V V V V V V V V
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SLDS123A - MARCH 2000 - REVISED JUNE 2000
functional description
overview The TFP420 integrates a PLL, DVI encoder, and three differential pairs of T.M.D.S. drivers. A dedicated high-speed low terminal count video pixel port transfers high-bandwidth digital video data from a graphics controller or other digital video source to the TFP420. The TFP420 is versatile and highly programmable to provide maximum flexibility for the user. An I2C host interface is provided to program and configure the TFP420. I2C interface The I2C interface is used to access the internal TFP420 register. This two-terminal interface consists of one clock line, SCL, and one serial data line, SDA. The basic I2C access cycles are shown in Figures 1 and 2.
SDA
SCL
Start Condition (S)
Stop Condition (P)
Figure 1. I2C Start and Stop Conditions The basic access cycle consists of the following:
D D D D D
A start condition A slave address cycle A subaddress cycle Any number of data cycles A stop condition
The start and stop conditions are shown in Figure 2. The high to low transition of SDA while SCL is high defines the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle, data or address consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 2.
1 SCL 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7
SDA
Stop MSB Slave Address Subaddress Data
Figure 2. I2C Access Cycles
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I2C interface (continued) Following a start condition, each I2C device decodes the slave address. The TFP420 responds with an acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address. During subsequent subaddress and data cycles the TFP420 responds with acknowledge as shown in Figure 3. The subaddress is autoincremented after each data cycle. The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device may drive the SDA signal low. The not acknowledge, /A, condition is indicated by the master by keeping the SDA signal high just before it asserts the stop, P, condition. This sequence terminates a read cycle as shown in Figure 4. The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in Figures 3 and 4. For the TFP420, the possible slave addresses (including the r/w bit) are 0x40 and 0x42 for write cycles and 0x41 and 0x43 for read cycles. Refer to register description, for additional base address information.
S Slave Address W A Subaddress A Data A Data A P
From Transmitter
A S
Acknowledge Start Condition
From Receiver
P Stop Condition / Not Acknowledge (SDA A High)
Figure 3. I2C Write Cycle
S
Slave Address
W
A
Subaddress
A
P
S
Slave Address
R
A
Data
A
Data
/A
P
From Transmitter
A S
Acknowledge Start Condition
From Receiver
P Stop Condition / Not Acknowledge (SDA A High)
Figure 4. I2C Read Cycle video port The TFP420 video port is a low terminal count and high-speed digital interface. The video port consists of a 12-bit data bus (DATA[11:0]), horizontal timing signal (HSYNC), vertical timing signal (VSYNC), blanking control (BLANK), clock signals (CLKIN0 and CLKIN1), and interrupt request signals (INT0 and INT1). To reduce the terminal count and the board space, a compact 12-bit pixel bus is used. The bus operates in either single-pump or double-pump mode depending on the selection of the input pixel format (FMT[2:0]). In single pump mode only the first edge of the CLKIN0/CLKIN1 differential clock pair is used to sample the data, timing, and blanking control signals. In double-pump mode, both edges of the clock are used. With the double-pump mode, high pixel transfer rates up to 165 Mpixels/sec can be achieved.
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video port (continued) To ease the timing and EMI issues associated with a high pixel transfer rate, the signaling level of the signals in video port is scalable. The input signals in video port are scalable by adjusting the voltage on the VREF terminal to VDDQ/2. Similarly, the output signals are scalable by adjusting the voltage on the VDDQ terminal to VDDQ, where VDDQ is the desirable full-swing voltage for the video port I/O signals. The differential CLKIN pair provides more robust and reliable sampling for the pixel data and control signals, alleviating tight setup and hold time requirements for high pixel transfer rates. Although differential clocking is the recommended clocking scheme, it is possible to use single-end clocking with reduced timing margin, which may be significant with high clock rates. When single-end clocking is used, CLKIN0 must be connected to the clock and CLKIN1 must be connected to VDDQ/2. The INT1 terminal, when enabled, generates an interrupt to inform the host CPU of events related to hot plug and power management. INT1 is open-drained and must be pulled up to VDDQ with a 10-K resistor. The INT0 terminal provides a dedicated interrupt for future applications. Similar to INT1, INT0 is open-drained. Normally a 10-K pullup resistor is needed to pull the signal to VDDQ. The TFP420 enters a special mode when the INT0 is forced to low just before the deassertion of the RST. DVI encoder The DVI encoder receives RGB pixel data from the video port and encodes the pixel data based on the transition minimized differential signaling (T.M.D.S.) encoding algorithm. The DVI encoder consists of three independent identical channels, each of which is responsible for encoding one color component. The encoding algorithm minimizes the signal transition while maintaining a good dc balance to reduce EMI. The encoded data is then serially shifted to the DVI output drivers for transmission. The low-voltage swing differential output further reduces EMI. Each channel is encoded independently. Each channel receives 2 bits of control data and 8 bits of color component data. Depending on the state of BLANK, the DVI encoder encodes either control data or color components. In either case, the data is encoded to a 10-bit character and serially shifted out with the LSB transmitted first. Blue channel (Channel 0) receives HSYNC and VSYNC as the control data and the blue color component as the pixel data. If BLANK is low, indicating valid blue component data is not transmitting, the DVI encoder of the blue channel encodes the HSYNC and VSYNC signals. If BLANK is high, indicating valid blue component data is transmitting, the DVI encoder encodes the blue component data. The green channel (Channel1) and the red channel (Channel 2) operate in a way similar to the blue channel with the exception that the control bits are hardwired to 0. There are two possible encoded characters for each pixel data. The DVI encoder keeps track of the difference between the number of ones and zeros that have been sent and selects the character that minimizes the difference in order to maintain the best dc balance. A serializer serializes the 10-bit character in each channel. An on-chip PLL locks to the CLKIN0 and CLKIN1 and generates the 10X clock to drive the serializer. The 10X clock is also sent to the T.M.D.S. drivers for output. clock generation The TFP420 uses the CLKIN signal to generate the required clock for DVI output. The on-chip PLL takes CLKIN as the reference and generates the 10X clock. This clock is used internally by the DVI encoder to encode and clock out the DVI bit stream as well as to output TXC+ and TXC- differential clock along with the DVI data signals. The CLK_CTRL register provides additional control over the clock signals. DKEN and CLKINDSK[2:0] allow the user to compensate the skew between the CLKIN and the pixel data and control signals. Refer to the description of the CLK_CTRL for details.
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functional description (continued)
hot plug/unplug (auto connect/disconnect detection) The TFP420 supports hot plug/unplug (auto connect/disconnect detection) for the DVI link. The connection status of DVI link and HTPLG sense terminal is provided by the CON_STATUS register. The RXCON bit indicates if a DVI receiver is connected to the TXC+ and TXC-. HPCON bit reflects the current state of the HTPLG terminal connected to the monitor via DVI connector. HTPLG terminal is 3-V tolerant with an internal digital debouncing circuit to allow for direct connection to the DVI connector. Whenever one or more connection status bits change states, the corresponding bit in the IN_STATUS bit is set to 1 to record the changes. An interrupt can also be generated as an option. The interrupt for each type of connect/disconnect event can be individually enabled or disabled by writing a 1 or 0 to the corresponding bit in the INT_ENABLE register. Notice that INT_ENABLE register does not affect the state of the INT_STATUS bits. A host can either poll the INT_STATUS bits or rely on the interrupt to learn about the states or the change of states of the connections. The interrupt continues to be asserted until 1 is written to the corresponding interrupt bit in the INT_STATUS register to reset the bit back to 0. Writing 0 to an interrupt status bit has no effect.
register map
The TFP420 is a standard I2C slave device. All the registers can be written and read through the I2C interface. The I2C base address of the TFP420 is dependent on terminal 10 (A0) as shown in Table 1. Table 1. Base I2C Address
Terminal 10 0 1 REGISTER VEN_ID VEN ID DEV_ID DEV ID REV_ID RESERVED F_CONTROL CLK_CTRL VIDOUT_CTRL SYNC_CTRL0 CON_STATUS INT_STATUS INT_ENABLE GP_CTRL RESERVED RW RW RW RW R RW RW RW RW R R R R R SUBADDRESS 00 01 02 03 04 05-39 3A 3B 3C 3D 3E 3F 40 41 42-FF Gio1_en Gp1_in Gp0_in Gp1_oe Gp0_oe RESERVED Syn_g Fid_pol Vs_fid Daccon3 Hs_com Daccon2 Vsen Daccon1 Cbar Intcko RGBF Ckindsk[3:0] Vidout[3:0] Hsen Daccon0 Tvsen Hpcon Hpevnt Hpen Gp1_out Thsen Rxcon Rxevnt Rxen Gp0_out BIT7 WRITE ADDRESS (HEX) 40 42 BIT6 BIT5 BIT4 READ ADDRESS (HEX) 41 43 BIT3 BIT2 BIT1 BIT0
Ven_id[7:0] Ven_id[15:8] Dev_Id[7:0] Dev_id[15:8] Rev_Id[7:0] RESERVED Fmt[3:0] Ckencse
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register description
VEN_ID 7 Subaddress = 00 6 5 Read Only 4 VEN_ID[7:0] 3 Default = 0x4C 2 1 0
Subaddress = 01 7 6 5
Read Only 4 VEN_ID[15:8] 3
Default = 0x01 2 1 0
This read-only register contains the 16-bit Texas Instruments vendor ID for the TFP420. VEN_ID[15:0] is hardwired to 0x014C.
DEV_ID 7 Subaddress = 02 6 5 Read Only 4 DEV_ID[7:0] 3 Default = 0x22 2 1 0
Subaddress = 03 7 6 5
Read Only 4 DEV_ID[15:8] 3
Default = 0x64 2 1 0
This read-only register contains the 16-bit device ID for the TFP420.
REV_ID 7 Subaddress = 04 6 5 Read Only 4 REV_ID[7:0] 3 Default = 0x01 2 1 0
This read-only register contains the revision ID for the TFP420. The revision ID will identify different revisions of the device. REV_ID[7:0] is hardwired to 0x01.
STATUS Subaddress = 05 Read Only
F_CONTROL 7 RSVD
Subaddress = 3A 6 RSVD 5 RGBF 4 3
Default = 0x8D 2 FMT[3:0] 1 0
Format Control Register. This register specifies the input video source and format. RGBF RGB /YCrCb input coding range 0(*) The input RGB data are in binary format with coding range 0-255 The input YCrCb data are in binary format with coding range 0-255 1 The input RGB data are in binary format with coding range 16-235 The input YCrCb data are in binary format conforming to ITU-601 standard
FMT[3:0] These four bits specify the video input data stream format and timing as shown in the table below. H indicates the sampling point at the crossover of the rising edge of CLKIN0 and the falling edge of CLKIN1 L indicates the sampling point at the crossover of the falling edge of CLKIN0 and the rising edge of CLKIN1
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register description (continued)
digital input video data and sync format
FMT[3:2] = 00(*) Color space Pixel format Scan Sync 00(*) H R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] L G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] H G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] RGB (8,8,8) Progressive HSYNC, VSYNC and BLANK FMT[1:0] DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Color space Pixel format Scan Sync 00 H Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Y[7] Y[6] Y[5] Y[4] L Y[3] Y[2] Y[1] Y[0] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] H Y[3] Y[2] Y[1] Y[0] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] 01 L R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] G[7] G[6] G[5] G[4] FMT[3:2] = 01 YCrCb 4:4:4 Progressive HSYNC, VSYNC and BLANK FMT[1:0] DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] 01 L Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[1] Cr[0] Y[7] Y[6] Y[5] Y[4] H Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Y[7] Y[6] Y[5] Cr[2] Cr[1] Cr[0] Y[1] 10 L Y[4] Y[3] Y[2] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Y[0] Cb[2] Cb[1] Cb[0] H Y[4] Y[3] Y[2] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Y[0] Cb[2] Cb[1] Cb[0] 11 L Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Y[7] Y[6] Y[5] Cr[2] Cr[1] Cr[0] Y[1] H R[7] R[6] R[5] R[4] R[3] G[7] G[6] G[5] R[2] R[1] R[0] G[1] 10 L G[4] G[3] G[2] B[7] B[6] B[5] B[4] B[3] G[0] B[2] B[1] B[0] H G[4] G[3] G[2] B[7] B[6] B[5] B[4] B[3] G[0] B[2] B[1] B[0] 11 L R[7] R[6] R[5] R[4] R[3] G[7] G[6] G[5] R[2] R[1] R[0] G[1]
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SLDS123A - MARCH 2000 - REVISED JUNE 2000
digital input video data and sync format (continued)
FMT[3:2] = 10 Color space Pixel format Scan Sync DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Scan Sync 0H DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] 0L 1H 1L Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] FMT[1:0] = 01 Interlaced HSYNC, VSYNC and BLANK 2H 2L 3H 3L Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] 0H 0L 1H 1L YCrCb 4:2:2 FMT[1:0] = 00 Interlaced HSYNC, VSYNC and BLANK 2H 2L 3H 3L
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TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
digital input video data and sync format (continued)
FMT[3:2] = 10 Color space Pixel format Scan Sync DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Scan Sync DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] 0H 0L 1H 1L Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] FMT[1:0] = 11 Progressive HSYNC, VSYNC and BLANK 2H 2L 3H 3L Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] 0H 0L 1H 1L YCrCb 4:2:2 FMT[1:0] = 10 Progressive HSYNC, VSYNC and BLANK 2H 2L 3H 3L
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TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
digital input video data and sync format (continued)
FMT[3:2] = 11 Color space Pixel format Scan Sync DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Scan Sync DATA[11:0] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] FMT[1:0] = 10 Reserved FMT[1:0] = 11 Reserved Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] 0H 0L 1H 1L Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] FMT[1:0] = 01 Interlaced F, V and H bits in the SAV and EAV codes are embedded in the video stream 2H 2L 3H 3L Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] 0H 0L 1H 1L YCrCb 4:2:2 FMT[1:0] = 00 Interlaced F, V and H bits in the SAV and EAV codes are embedded in the video stream 2H 2L 3H 3L
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SLDS123A - MARCH 2000 - REVISED JUNE 2000
register description (continued)
7 6 5 4 3 CKINDSK[3:0] 2 1 0 RSVD
CKINDSK
[3:0]
CLKIN deskew control
0000 -8 T 0001 -7 T 0010 -6 T 0011 -5 T 0100 -4 T 0101 -3 T 0110 -2 T 0111 -T 1000(*) No Skew 1001 T 1010 2 T 1011 3 T 1100 4 T 1101 5 T 1110 6 T 1111 7 T Where T = approximately 100 ps.
VIDOUT_CTRL 7 Subaddress = 3C 6 5 4 3 Default = 0x00 2 VIDOUT[3:0] 1 0
VIDOUT[3:0]
Video output mode 0000(*) DVI 0001-1110 Reserved 1111 Power down I2C interface continues to be active in power down modes.
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TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
register description (continued)
SYNC_CTRL0 7 RSVD Subaddress = 3D 6 RSVD 5 RSVD 4 HS_COM 3 VSEN Default = 0x03 2 HSEN 1 TYSEN 0 THSEN
THSEN
DVI HSYNC enable 0 HSYNC is transmitted as 0 1(*) HSYNC is transmitted as received from the video port DVI VSYNC enable 0 VSYNC is transmitted as 0 1(*) VSYNC is transmitted as received from the video port HS enable 0(*) HS is in inactive state (LOW) 1 HS outputs digital horizontal/composite sync VS enable 0(*) VS is in inactive state (LOW) 1 VS outputs digital vertical sync
TVSEN
HSEN
VSEN
HS_COM HS function select 0(*) HS outputs horizontal sync 1 HS outputs composite sync
CON_STATUS 7 Subaddress = 3E 6 5 RSVD Read Only 4 RSVD 3 RSVD 2 RSVD 1 HPCON 0 RXCON
RXCON HPCON
INT_STATUS 7
0 1 0 1
DVI receiver is not connected DVI receiver is connected Hot plug is not connected Hot plug is connected
Subaddress = 3F 6 5 Read Only 4 3 2 1 HPEVNT 0 RXEVNT
RXEVNT HPEVNT
0 1 0 1
RXCON bit has not changed RXCON bit has changed HPCON bit has not changed HPCON bit has changed
To clear a bit, write 1 to the bit to clear. Writing 0 will not change the bit status.
INT_ENABLE 7 Subaddress = 40 6 5 Default = 0x00 4 3 2 1 hpen 0 rxen
RXEN HPEN
0(*) 1 0(*) 1
RXEVNT interrupt disabled RXEVNT interrupt enabled HPEVNT interrupt disabled HPEVNT interrupt enabled
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register description (continued)
GP_CTRL 7 GIO1_EN Subaddress = 41 6 Reserved 5 GP1_IN 4 GP0_IN Default = 0x80 3 GP1_OE 2 GP0_OE 1 GP1_OUT 0 GP0_OUT
GP0_OUT General-purpose output bit. The state of this bit shows on GPIO0 terminal if GP0_OE is set to 1. Otherwise, GPIO0 terminal goes to a high impedance state. 0(*) GPIO0 terminal outputs LOW 1 GPIO0 terminal outputs HIGH GP1_OUT General-purpose output bit. The state of this bit shows on GPIO1 terminal if GP1_OE is set to 1. Otherwise, GPIO1 terminal goes to a high impedance state. 0(*) GPIO1 terminal outputs LOW 1 GPIO1 terminal outputs HIGH GP0_OE General-purpose bit output enable. 0(*) GPIO0 output goes to a high impedance state. 1 GPIO0 output is enabled GP1_OE General-purpose bit output enable. 0(*) GPIO1 output goes to a high impedance state. 1 GPIO1 output is enabled GP0_IN General-purpose input bit. This bit shows the state of GPIO0 terminal. 0(*) GPIO0 terminal is LOW 1 GPIO0 terminal is HIGH General-purpose input bit. This bit shows the state of GPIO1 terminal. 0(*) GPIO1 terminal is LOW 1 GPIO1 terminal is HIGH
GP0_IN
GIO1_EN .GPIO1 terminal enable 0(*) HC/CS/GPIO1 outputs Horizontal or composite sync 1 HC/CS/GPIO1 is used as the second general-purpose I/O terminal.
GIO1_EN 0 0 0 0 0 1 1 1 1 GP1_OUT X X X X X 0 0 1 1 GP1_OE X X X X X 0 1 0 1 HS_COM 0 1 1 1 1 X X X X HSEN 0 0 0 1 1 X X X X VSEN X 0 1 0 1 X X X X Terminal 45 LOW LOW VS HS CS 3-state LOW 3-state HIGH
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TFP420 PanelBusTM DIGITAL TRANSMITTER
SLDS123A - MARCH 2000 - REVISED JUNE 2000
PowerPADTM 64TQFP package
The TFP420 is packaged in TI's thermally enhanced PowerPADTM 64TQFP packaging. The PowerPADTM package is a 10 mm x 10 mm x 1.4mm TQFP outline with 0.5mm lead-pitch. The PowerPADTM package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 64TQFP PowerPADTM package offers a backside solder plane that connects directly to the die mount pad for enhanced thermal conduction. The system designer has the option to solder this backside plane to a thermal/ ground plane on the PCB. Since the die pad is electrically connected to the TFP420 chip substrate and hence ground, the backside PowerPADTM connection to a PCB ground plane can improve ground bounce and power supply noise. The connection of the PowerPADTM to a PCB thermal/ground plane is optional. The following table outlines the thermal properties of the TI 64-TQFP PowerPADTM package. The 64-TQFP non-PowerPADTM package is included only for reference. TI 64-TQFP (10 x 10 x 1.4 mm)/0.5 mm lead-pitch
PARAMETER Theta-JA Theta-JC Maximum power dissipation Maximum TFP6422 pixel rate Specified with 2 oz. Cu PCB plating. Airflow is at 0 LFM (no airflow) Measured at ambient temperature, TA = 70C. WITHOUT PowerPADTM 45C/W 3.11C/W 1.6 W TBD PowerPADTM NOT CONNECTED TO PCB THERMAL PLANE 27.3C/W 0.12C/W 2.7 W TBD PowerPADTM CONNECTED TO PCB THERMAL PLANE 17.3C/W 0.12C/W 4.3 W TBD
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MECHANICAL DATA
PAP (S-PQFP-G64) PowerPADTM PLASTIC QUAD FLATPACK
0,50 48
0,27 0,17 33
0,08 M
49
32 Thermal Pad (See Note D)
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane 0- 7 16
1,20 MAX
0,08 4147702/A 01/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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