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| TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 * * * * Low rDS(on) . . . 0.3 Typ High-Voltage Output . . . 60 V Pulsed Current . . . 8 A Per Channel Fast Commutation Speed DW PACKAGE (TOP VIEW) description The TPIC5601 is a monolithic power DMOS array that consists of six electrically isolated N-channel enhancement-mode DMOS transistors, three of which are configured with a common source. The TPIC5601 is offered in a 20-pin wide-body surface-mount (DW) package. The TPIC5601 is characterized for operation over the case temperature range of - 40C to 125C. DRAIN4 GATE4 GND GND DRAIN5 GATE5 GND GND GATE6 DRAIN6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SOURCE1 NC GATE1 DRAIN1 DRAIN2 SOURCE2 GATE2 DRAIN3 GATE3 SOURCE3 NC - No internal connection schematic 17 Q1 GATE1 18 Z1 D1 SOURCE2 GATE2 DRAIN2 15 14 16 Q2 Z2 D2 D3 Z3 13 Q3 12 GATE3 DRAIN1 DRAIN3 SOURCE1 DRAIN4 20 1 Q4 Q5 Z4 Z5 Z6 11 10 Q6 9 SOURCE3 DRAIN6 GATE4 2 GATE6 5 DRAIN5 6 GATE5 3, 4, 7, 8 GND PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q4, Q5, and Q6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Continuous drain current, each output, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 A Continuous source-to-drain diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 A Pulsed drain current, ID, each output, TC = 25C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . . . 8 A Single-pulse avalanche energy, EA, TC = 25C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 mJ Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% DISSIPATION RATING TABLE PACKAGE DW TC 25C POWER RATING 1125 mW DERATING FACTOR ABOVE TC = 25C 9.0 mW/C TC = 125C POWER RATING 225 mW 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 electrical characteristics, TC = 25C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) V(BR) VDS(on) VF VF(SD) Drain-to-source breakdown voltage Gate-to-source threshold voltage Reverse drain-to-GND breakdown voltage (across D1, D2, and D3) Drain-to-source on-state voltage Forward on-state voltage, GND-to-drain TEST CONDITIONS ID = 250 A, ID = 1 mA, VGS = 0 VDS = VGS MIN 60 1.5 100 0.51 7.5 0.6 1.85 2.2 TYP MAX UNIT V V V V V Drain-to-GND current = 250 A ID = 1.7 A, See Notes 2 and 3 VGS = 10 V, ID = 1.7 A (D1, D2, D3), See Notes 2 and 3 IS = 1.7 A, VGS = 0 (Z1, Z2, Z3, Z4, Z5, Z6), See Notes 2 and 3 , VDS = 48 V, VGS = 0 VGS = 16 V, VSG = 16 V, VR = 48 V VGS = 10 V, ID = 1.7 A, , See Notes 2 and 3 and Figures 6 and 7 VDS = 15 V, See Notes 2 and 3 TC = 25C TC = 125C VDS = 0 VDS = 0 TC = 25C TC = 125C TC = 25C TC = 125C ID = 1 A, 1.2 Forward on-state voltage, source-to-drain 1 0.05 0.5 10 10 0.05 0.5 0.3 0.41 1.75 190 1.2 1 10 100 100 1 10 0.35 V IDSS IGSSF IGSSR Ilk lkg Zero-gate-voltage Zero gate voltage drain current Forward gate current, drain short circuited to source Reverse gate current, drain short circuited to source Leakage current, drain-to-GND current drain to GND A nA nA A rDS( ) DS(on) Static drain-to-source on-state resistance drain to source on state 0.5 S 240 125 50 pF F gfs Ciss Coss Crss Forward transconductance Short-circuit input capacitance, common source Short-circuit output capacitance, common source Short-circuit reverse-transfer capacitance, common source VDS = 25 V, f = 1 MHz VGS = 0, 100 40 NOTES: 2. Technique should limit TJ - TC to 10C maximum, pulse duration 5 ms. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain diode characteristics, TC = 25C PARAMETER trr(SD) QRR trr(SD) QRR Reverse-recovery time Total diode charge Reverse-recovery time Total diode charge TEST CONDITIONS IS = 1 A, VGS = 0, di/dt = 100 A/s A/s, See Figure 1 IS = 1 A, VGS = 0, di/dt = 100 A/s A/s, See Figure 1 VDS = 48 V, (Z1, Z2 Z3) (Z1 Z2, Z3), VDS = 48 V, (Z4, Z5 Z6) (Z4 Z5, Z6), MIN TYP 65 0.12 240 0.9 MAX UNIT ns C ns C GND-to-drain diode characteristics, TC = 25C (see schematic, D1, D2, and D3) PARAMETER trr QRR Reverse-recovery time Total diode charge TEST CONDITIONS IF = 1 A, di/dt = 100 A/s, VDS = 48 V, See Figure 1 MIN TYP 260 2.2 MAX UNIT ns C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 resistive-load switching characteristics, TC = 25C PARAMETER td(on) td(off) tr2 tf2 Qg QGS QGD L(drain) L(source) Rg Turn-on delay time Turn-off delay time Rise time Fall time Total gate charge Threshold gate-to-source charge Gate-to-drain charge Internal drain inductance Internal source inductance Internal gate resistance VDS = 48 V, V See Figure 3 ID = 1 A, A VGS = 10 V, V VDD = 25 V, , tf1 = 10 ns, RL = 25 , , See Figure 2 tr1 = 10 ns, , TEST CONDITIONS MIN TYP 32 40 15 25 5 0.5 1.9 5 5 0.25 nH MAX 65 80 30 50 6 0.6 2.3 nC ns UNIT thermal resistance PARAMETER RJA RJP Junction-to-ambient thermal resistance Junction-to-pin thermal resistance TEST CONDITIONS All outputs with equal power power, See Note 4 MIN TYP 90 27 MAX UNIT C/W NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink. PARAMETER MEASUREMENT INFORMATION 3 TJ = 25C 2 I S - Source-to-Drain Diode Current - A trr(SD) 1 Reverse di/dt = 100 A/s 0 25% of IRM -1 -2 IRM(REC) -3 0 50 100 150 Time - ns IRM(REC)= maximum recovery current 200 250 300 Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tr1 RL Pulse Generator VGS DUT Rgen 50 50 CL 30 pF (see Note A) VDS td(on) tf2 VDS VGS 0V td(off) tr2 VDD VDS(on) tf1 10 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms VDS Qg Same Type as DUT 0.3 F VDD DUT VGS Gate Voltage Time IG CurrentSampling Resistor TEST CIRCUIT ID CurrentSampling Resistor Qgs = Qg - Qgd VOLTAGE WAVEFORM 10 V Qgs(th) Qgd Current Regulator 12-V Battery 0.2 F 50 k 0 IG = 1 A Figure 3. Gate-Charge Test Circuit and Voltage Waveform POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V 656 H Pulse Generator (see Note A) 50 Rgen 50 VDS VDS VGS 0V ID IAS (see Note B) 0V V(BR)DSX = 60 V Min tw tav 15 V ID VGS DUT 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 8 A. I V t av AS (BR)DSX Energy test level is defined as E 36 mJ, where AS 2 tav = Avalanche time + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) - Gate-to-Source Threshold Voltage - V 2.5 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.5 ID = 1.7 A VGS = 10 V 2 ID = 1 mA 1.5 ID = 100 A 1 r DS(on) - Static Drain-to-Source 0.4 On-State Resistance - VGS = 15 V 0.3 0.2 0.5 0.1 0 - 40 - 20 0 20 40 60 80 100 120 140 160 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 5 Figure 6 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 0.9 0.8 0.7 On-State Resistance - 0.6 0.5 0.4 0.3 VGS = 10 V I D - Drain Current - A 5 TJ = 25C 4 VGS = 10 V VGS = 15 V DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE nVGS = 0.2 V r DS(on) - Static Drain-to-Source TJ = 25C Unless Otherwise Noted 3 VGS = 4 V 2 VGS = 15 V 0.2 1 VGS = 3 V 0.1 0.01 0 0 2 4 6 8 10 12 14 16 18 20 VDS - Drain-to-Source Voltage - V 0.10 1 ID - Drain Current - A 10 Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 8 TJ = - 40C 7 6 I D - Drain Current - A 5 4 3 2 1 TJ = 25C TJ = 75C TJ = 125C TJ = 150C DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 0.25 Total Number of Units = 2196 TJ = 25C 0.2 Percentage of Units - % 0.15 0.1 0.05 1.375 1.525 1.675 1.975 1.825 2.125 1.75 1.45 2.05 1.3 1.6 1.9 0 0 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to-Source Voltage - V gfs - Forward Transconductance - S Figure 9 Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 400 360 320 C - Capacitance - pF 280 240 200 160 120 80 40 0 0 4 8 12 16 20 24 28 32 36 40 VDS - Drain-to-Source Voltage - V Coss Crss Ciss I SD - Source-to-Drain Diode Current - A f = 1 MHz TJ = 25C 8 6 4 SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 2 1 0.6 0.4 TJ = 150C 0.2 TJ = 75C 0.1 0.1 1 VSD - Source-to-Drain Voltage - V 10 TJ = 125C TJ = - 40C TJ = 25C Figure 11 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 70 60 50 40 30 20 VDD = 48 V 10 VDD = 20 V 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Qg - Gate Charge - nC 0 0 0 100 2 VDD = 30 V ID = 1 A TJ = 25C See Figure 3 14 12 10 8 6 4 VGS - Gate-to-Source Voltage - V 300 IS = 1 A TJ = 25C 250 See Figure 1 Figure 12 REVERSE-RECOVERY TIME vs REVERSE di/dt VDS - Drain-to-Source Voltage - V VDD = 20 V trr - Reverse-Recovery Time - ns 200 Q4, Q5, and Q6 150 100 Q1, Q2, and Q3 50 200 300 400 500 Reverse di/dt - A/s 600 700 Figure 13 Figure 14 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 100 TC = 25C I RM(REC) - Maximum Drain Current - A I AS - Maximum Peak-Avalanche Current - A 100 See Figure 4 MAXIMUM PEAK-AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 1 s 10 ms 1 ms 500 s 10 1 TC = 25C TC = 125C AA AA AA DC Conditions 0.1 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 1 0.01 0.1 1 10 tav - Time Duration of Avalanche - ms 100 Less than 0.1 duty cycle Non-JEDEC symbol for avalanche time. Figure 15 Figure 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TPIC5601 3-PHASE BRIDGE POWER DMOS ARRAY SLIS022B - MARCH 1994 - REVISED OCTOBER 1995 THERMAL INFORMATION DW PACKAGE NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE vs PULSE DURATION 10 RJA - Normalized Junction-to-Ambient Thermal Resistance - C/W DC Conditions 1 d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 0.01 d = 0.01 Single Pulse 0.001 tw ID 0 0.0001 0.0001 tc 0.001 0.01 0.1 1 10 tw - Pulse Duration - s Device mounted on FR4 printed-circuit board with no heatsink NOTE A: ZA(t) = r(t) RJA tw = pulse duration tc = cycle time d = duty cycle = tw / tc Figure 17 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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