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| TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 * * * * Low rDS(on) . . . 0.3 Typ High-Voltage Outputs . . . 60 V Pulsed Current . . . 7 A Per Channel Fast Commutation Speed D PACKAGE (TOP VIEW) description The TPIC5302 is a monolithic power DMOS array that consists of three electrically isolated independent N-channel enhancement-mode DMOS transistors. The TPIC5302 is offered in a standard 16-pin small-outline surface-mount (D) package. The TPIC5302 is characterized for operation over the case temperature range of - 40C to 125C. GND SOURCE1 SOURCE1 SOURCE2 SOURCE2 SOURCE3 SOURCE3 GATE3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DRAIN1 DRAIN1 GATE1 DRAIN2 DRAIN2 GATE2 DRAIN3 DRAIN3 schematic DRAIN1 15, 16 GATE2 11 DRAIN2 12, 13 GATE3 8 DRAIN3 9, 10 Q1 GATE1 14 Z1 D1 Q2 Z2 D2 Q3 Z3 D3 2, 3 SOURCE1 1 GND 4, 5 SOURCE2 6, 7 SOURCE3 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Gate-to-source voltage, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Continuous drain current, each output, all outputs on, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Continuous source-to-drain diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Pulsed drain current, each output, TC = 25C (see Note 1 and Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A Single-pulse avalanche energy, EAS, TC = 25C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 mJ Continuous total power dissipation at (or below) TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 mW Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms and duty cycle = 2% PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 electrical characteristics, TC = 25C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) V(BR) VDS(on) VF(SD) VF IDSS IGSSF IGSSR Ilk lkg Drain-to-source breakdown voltage Gate-to-source threshold voltage Reverse drain-to-GND breakdown voltage (across D1, D2, and D3) Drain-to-source on-state voltage TEST CONDITIONS ID = 250 A, ID = 1 mA, VGS = 0 VDS = VGS MIN 60 1.5 100 0.42 0.49 1.85 2.2 TYP MAX UNIT V V V V Drain-to-GND current = 250 A ID = 1.4 A, See Notes 2 and 3 IS = 1.4 A, VGS = 0 (Z1, Z2, Z3), See Notes 2 and 3 ID = 1.4 A VDS = 48 V, , VGS = 0 VGS = 16 V, VSG = 16 V, VR = 48 V VGS = 10 V, ID = 1.4 A, , See Notes 2 and 3 and Figures 6 and 7 VDS = 10 V, See Notes 2 and 3 TC = 25C TC = 125C VDS = 0 VDS = 0 TC = 25C TC = 125C TC = 25C TC = 125C ID = 0.7 A, VGS = 10 V, Forward on-state voltage, source-to-drain Forward on-state voltage, GND-to-drain Zero-gate-voltage Zero gate voltage drain current Forward gate current, drain short circuited to source Reverse gate current, drain short circuited to source Leakage current, drain-to-GND current drain to GND 0.9 4.8 0.05 0.5 10 10 0.05 0.5 0.3 0.41 1.15 1.41 135 1.1 V V 1 10 100 100 1 10 0.35 A nA nA A rDS( ) DS(on) Static drain-to-source on-state resistance drain to source on state 0.5 S 170 100 40 pF F gfs Ciss Coss Crss Forward transconductance Short-circuit input capacitance, common source Short-circuit output capacitance, common source Short-circuit reverse-transfer capacitance, common source VDS = 25 V, f = 1 MHz VGS = 0, 80 30 NOTES: 2. Technique should limit TJ - TC to 10C maximum and pulse duration 5 ms. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain diode characteristics, TC = 25C PARAMETER trr(SD) QRR Reverse-recovery time Total diode charge TEST CONDITIONS IS = 0.5 A, VGS = 0, di/dt = 100 A /s, VDS = 48 V, See Figure 1 MIN TYP 35 0.04 MAX UNIT ns C GND-to-drain diode characteristics, TC = 25C (see schematic, D1, D2, and D3) PARAMETER trr QRR Reverse-recovery time Total diode charge TEST CONDITIONS IF = 0.5 A, di/dt = 100 A /s, VDS = 48 V, See Figure 1 MIN TYP 130 0.4 MAX UNIT ns C 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 resistive-load switching characteristics, TC = 25C PARAMETER td(on) td(off) tr2 tf2 Qg Qgs(th) Qgd LD LS Rg Turn-on delay time Turn-off delay time Rise time Fall time Total gate charge Threshold gate-to-source charge Gate-to-drain charge Internal drain inductance Internal source inductance Internal gate resistance VDS = 48 V, V See Figure 3 ID = 0 5 A, 0.5 A VGS = 10 V, V VDD = 25 V, , tf1 = 10 ns, RL = 50 , , See Figure 2 tr1 = 10 ns, , TEST CONDITIONS MIN TYP 23 25 5 17 8 0.5 1.5 5 5 0.25 nH MAX 46 50 10 34 9.8 0.63 1.85 nC ns UNIT thermal resistance PARAMETER RJA RJP Junction-to-ambient thermal resistance Junction-to-pin thermal resistance TEST CONDITIONS All outputs with equal power power, See Note 4 MIN TYP 115 32 MAX UNIT C/W NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink PARAMETER MEASUREMENT INFORMATION 1 TJ = 25C 0.5 I S - Source-to-Drain Diode Current - A Reverse di/dt = 100 A/s 0 - 0.5 25% of IRM -1 - 1.5 -2 IRM - 2.5 trr(SD) -3 0 25 50 75 100 125 150 Time - ns 175 200 225 250 IRM = maximum recovery current Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tr1 VGS VGS DUT Rgen 50 50 CL = 30 pF (see Note A) VDS VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. td(on) tf2 0V td(off) tr2 VDD VDS(on) tf1 10 V RL Pulse Generator VDS Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms VDS Qg Same Type as DUT 0.3 F VDD DUT VGS Gate Voltage Time IG CurrentSampling Resistor TEST CIRCUIT ID CurrentSampling Resistor Qgs = Qg - Qgd VOLTAGE WAVEFORM 10 V Qgs(th) Qgd Current Regulator 12-V Battery 0.2 F 50 k 0V IG = 1 A Figure 3. Gate-Charge Test Circuit and Voltage Waveform 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 25 V tw VGS 0V ID IAS (see Note B) 0V 50 VDS V(BR)DSX = 60 V Min tav 15 V 250 H Pulse Generator (see Note A) 50 Rgen VDS ID VGS DUT 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 7 A, where tav = avalanche time. I V t av AS (BR)DSX Energy test level is defined as E 10.5 mJ AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) - Gate-to-Source Threshold Voltage - V 2.5 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 1 ID = 1.4 A 2 ID = 1 mA 1.5 ID = 100 A 1 r DS(on) - Static Drain-to-Source 0.8 On-State Resistance - 0.6 VGS = 10 V 0.4 VGS = 15 V 0.2 0.5 0 - 40 - 20 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C 0 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C Figure 5 Figure 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 TJ = 25C r DS(on) - Static Drain-to-Source 4 On-State Resistance - I D - Drain Current - A 5 15 V DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE VGS = 5 V nVGS = 0.2 V TJ = 25C Unless Otherwise Noted 3 VGS = 10 V VGS = 4 V 2 VGS = 15 V 1 VGS = 3 V 0.1 0.01 0 0.1 1 ID - Drain Current - A 10 0 1 5 6 7 8 2 3 4 VDS - Drain-to-Source Voltage - V 9 10 Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 5 TJ = - 40C TJ = 25C TJ = 75C TJ = 150C TJ = 125C DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 0.5 0.45 0.4 Percentage of Units - % I D - Drain Current - A 1.365 1.395 1.425 1.455 1.35 1.38 1.41 1.44 1.47 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 Total Number of Units = 819 TJ = 25C 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 7 8 9 2 3 4 5 6 VGS - Gate-to-Source Voltage - V 10 gfs - Forward Transconductance - S Figure 9 Figure 10 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 250 225 200 C - Capacitance - pF 175 150 125 100 75 50 25 0 0 4 8 12 16 20 24 28 32 36 VDS - Drain-to-Source Voltage - V 40 Crss Coss Ciss I SD- Source-to-Drain Diode Current - A f = 1 MHz TJ = 25C 10 SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 1 TJ = 125C 0.1 TJ = 150C TJ = - 40C TJ = 25C TJ = 75C Figure 11 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 80 70 VDS - Drain-to-Source Voltage - V 60 50 40 30 20 10 VDD = 20 V 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Qg - Gate Charge - nC 0 VDD = 30 V IS = 0.7 A TJ = 25C See Figure 3 16 14 VGS - Gate-to-Source Voltage - V 12 10 8 6 4 2 0 t rr - Reverse-Recovery Time - ns VDD = 20 V 150 VDD = 48 V Figure 13 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 AA AA AA 0.01 0.1 1 VSD - Source-to-Drain Voltage - V 10 Figure 12 REVERSE-RECOVERY TIME vs REVERSE di/dt IS = 0.7 A TJ = 25C See Figure 1 D1, D2, and D3 125 100 75 50 Q1, Q2, and Q3 25 0 100 200 300 400 500 600 Reverse di/dt - A/s Figure 14 7 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 10 TC = 25C I D - Maximum Drain Current - A I AS - Maximum Peak-Avalanche Current - A 1 s 10 See Figure 4 MAXIMUM PEAK-AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 ms 1 ms 1 500 s TC = 25C TC = 125C AA AA 8 DC Conditions 0.1 0.1 10 1 VDS - Drain-to-Source Voltage - V 100 1 0.001 0.01 0.1 1 10 tav - Time Duration of Avalanche - ms Less than 0.1 duty cycle Figure 16 Figure 15 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5302 3-CHANNEL INDEPENDENT POWER DMOS ARRAY SLIS029B - APRIL 1994 - REVISED SEPTEMBER 1995 THERMAL INFORMATION D PACKAGE NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE vs PULSE DURATION 10 R JA - Normalized Junction-to-Ambient Thermal Resistance - C/W 1 DC Conditions d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 d = 0.01 0.01 Single Pulse 0.001 tc tw ID 0 0.0001 0.0001 0.001 0.01 0.1 1 10 tw - Pulse Duration - s Device mounted on FR4 printed-circuit board with no heat sink NOTE A: ZA(t) = r(t) RJA tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 17 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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