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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
D D D D D D D D D D D D D D D D D D
Supports Provisions of IEEE 1394-1995 for High-Performance Serial Bus Fully Interoperable With FireWireTM Implementation of IEEE 1394-1995 Provides Three Fully Compliant Cable Ports at 100 Mbits Per Second (Mbits/s) Cable Ports Monitor Line Conditions for Active Connection to Remote Node Inactive Ports Disabled to Save Power Logic Performs System Initialization and Arbitration Functions Encode and Decode Functions Included for Data Strobe Bit Level Encoding Incoming Data Resynchronized to Local Clock Interface to Link Layer Controller Supports Optional Electrical Isolation Data Interface to Link Layer Controller Provided Through Two Parallel Lines at 50 Mbits/s 25-MHz Crystal Oscillator and PLL Provide Transmit, Receive Data, and Link Layer Controller Clocks at 50 MHz Selectable Oscillator Input for External 100-MHz Reference Signal Node Power Class Information Signaling for System Power Management Cable Power Presence Monitoring Cable Bias and Driver Termination Voltage Supply Single 5-V Supply Operation Separate Multiple Package Terminals Provided for Analog and Digital Supplies and Grounds High-Performance 56-Pin SSOP (DL) Package
DL PACKAGE (TOP VIEW)
CPS AVCC AVCC XI XO AVCC AVCC PDOUT VCOIN TESTM2 RESET ISO AGND AGND AGND AGND AGND DGND LPS DGND LREQ TESTM1 DVCC SYSCLK CTL0 CTL1 D0 D1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
TPA1 TPA1 TPB1 TPB1 TPA2 TPA2 TPB2 TPB2 TPA3 TPA3 TPB3 TPB3 AGND AGND AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/ LKON
description
The TSB11C01 provides the analog transceiver functions needed to implement a 3-port node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB11C01 is designed to interface with a link layer controller, such as the TSB12C01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
description (continued)
The TSB11C01 requires either an external 24.576-MHz crystal or an external 98.304-MHz reference oscillator input. When using the crystal oscillator option, an internal phase-locked loop (PLL) generates the required 98.304-MHz reference signal. Selecting the external oscillator option turns off both the crystal oscillator and the PLL. The 98.304-MHz reference signal is internally divided to provide the 49.152-MHz 100 ppm clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link layer controller for synchronization of the two chips and is used for resynchronization of the received data. Data bits to be transmitted are received from the link layer controller on two parallel paths and are latched internally in the TSB11C01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 Mbits/s as the outbound data strobe information stream. During transmit, the encoded data information is transmitted differentially on the TPB cable pair(s) and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams, resynchronized to the local system clock and sent to the associated link layer controller. The received data is also transmitted (repeated) out of the other active cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is used as an indication of cable connection status. The TSB11C01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, senses the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceivers operating from either 5-V nominal supplies or 3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 1 F. The line drivers in the TSB11C01 operate in the high-impedance current mode and are designed to work with external 112- line matching resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of series-connected 56- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B-package terminals is coupled to ground through a parallel RC network with recommended values of 5 k and 250 pF. The values of the external resistors are designed to meet the IEEE 1394-1995 specifications when connected in parallel with the internal receiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between R1 and R0 and has a value of 6.36 k 0.5%. Two terminals set up various test conditions used in manufacturing. Terminals TESTM1 and TESTM2 should be connected to VCC for normal operation. Four terminals are used as inputs to set four configuration status bits in the self identification packet. These terminals are hardwired high or low as a function of the equipment design. PC[0:2] are three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON, indicates if a node is a contender for configuration manager. C/LKON can also output a 6.114-MHz 100 ppm signal, indicating reception of a link-on packet. See Table 4-27 of the IEEE 1394-1995 standard for additional details.
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
description (continued)
The TSB11C01 supports an optional isolation barrier between itself and its link layer controller. When ISO is tied high, the link interface outputs behave normally; when tied low, an internal differentiating logic is enabled and the outputs become short pulses that can be coupled through a capacitor or transformer. The TSB11C01 is characterized for operation from 0C to 70C.
functional block diagram
CPS LPS ISO 1 19 12 Received Data Decoder/ Retimer Bias Voltage and Current Generator 38 39 36 R1 R0 TPBIAS
SYSCLK LREQ
24 56 21 25 26 Link Interface I/O Cable Port 1 54 TPB1 TPB1 55 TPA1 TPA1
CTL0 CTL1
D0 D1
27 28
53
Arbitration and Control State Machine Logic Cable Port 2
52 51 50 49
TPA2 TPA2 TPB2 TPB2 TPA3 TPA3 TPB3 TPB3
C/LKON PC0 PC1 PC2 TESTM1 TESTM2
29 34 35 37 22 10 4 5 Crystal Oscillator PLL System and Transmit Clock Generator 8 9 32 31 Cable Port 3 46 45 48 47
XI XO PDOUT VCOIN CLK100 ENCLK100
RESET
11
Transmit Data Encoder
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
Terminal Functions
TERMINAL NAME AGND AVCC CLK100 C/LKON CPS CTL[0:1] D[0:1] DGND DVCC ENCLK100 ISO LPS LREQ PDOUT PC[0:2] R[0:1] RESET TESTM1, TESTM2 SYSCLK TPA1, TPA2, TPA3 TPA1, TPA2, TPA3 TPB1, TPB2, TPB3 TPB1, TPB2, TPB3 TPBIAS VCOIN NO. 13 -17, 40 - 44 2, 3, 6, 7 32 29 1 25, 26 27, 28 18, 20, 30 23, 33 31 12 19 21 8 34, 35, 37 38, 39 11 22, 10 24 56, 52, 48 55, 51, 47 54, 50, 46 53, 49, 45 36 9 I I O I/O I/O I/O I/O O I I I I I O I I I/O I I/O I/O I/O Analog circuit ground Analog circuit supply voltage Optional external clock input Configuration manager contender status input or link-on output Cable power status Link interface bidirectional control signals Link interface bidirectional data signals Digital circuit ground Digital circuit supply voltage Disable crystal oscillator and PLL, enable CLK100 input Physical (phy) link interface isolation status Link power status Link request from controller Output from PLL phase detector, input to external filter Power class bits 0 through 2 inputs External bias current-setting resistor Reset Test mode control, normally tied high 49.152-MHz clock to link controller Port n cable pair A, positive signal Port n cable pair A, negative signal Port n cable pair B, positive signal Port n cable pair B, negative signal Cable termination voltage source Input to VCO, output from external filter DESCRIPTION
XI, XO 4, 5 I/O External crystal for oscillator The output voltage at TPBIAS (terminal 36) is approximately 50 mV below the target design value. This can cause the measured TPBIAS output voltage to fall outside the specified limits when under the worst case conditions of minimum supply voltage and maximum load current. To adjust the output voltage at TPBIAS to the specified limit, connect an external resistor of approximately 785 between TPBIAS (terminal 36) and AVCC (terminals 2, 3, 6, or 7). The nominal TPBIAS output voltage will be adjusted to the target design value on a future revision of this device.
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SLLS167A - MARCH 1994 - REVISED MARCH 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING
DL 2500 mW 20 mW/C 1600 mW This is the inverse of the traditional junction-to-case thermal resistance (RJA) and uses a board mounted device rated at 50C/W.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID Common-mode input voltage, VIC High-level High level output current, IOH current Low-level Low level output current, IOL current Output current, IO CMOS inputs CMOS inputs Cable inputs Cable inputs SYSCLK CTL0, CTL1, D0, D1 SYSCLK CTL0, CTL1, D0, D1 TPBIAS -5 142 1.12 4.75 0.7 VCC 0.2 VCC 260 2.54 - 16 - 12 16 12 2.5 NOM 5 MAX 5.25 UNIT V V V mV V mA mA mA
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
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electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
driver
PARAMETER VOD IIC VOFF Differential output voltage Common-mode input current Off-state voltage TEST CONDITIONS RL = 55 Driver enabled Driver disabled MIN 180 - 0.55 MAX 260 0.55 20 UNIT mV mA mV
receiver
PARAMETER IIC zID zIC Common-mode input current Differential input impedance Common-mode Common mode input impedance Cable bias detect threshold, TPBx inputs TEST CONDITIONS Driver disabled MIN - 20 5 6 20 24 0.6 1.12 MAX 20 UNIT A k pF k pF V
device
PARAMETER Power status threshold VOH VOL High-level output voltage Low-level output voltage Positive arbitration comparator threshold Negative arbitration comparator threshold TPBIAS output voltage VIT + VIT - Positive input threshold voltage, LREQ, CTL, D inputs Negative input threshold voltage, LREQ, CTL, D inputs TEST CONDITIONS 0.4-M resistor IOH = MAX, IOL = MIN, VCC = MIN VCC = MAX MIN 4.7 3.7 0.5 89 - 168 1.71 VCC /2 + 0.2 VCC /2 - 1.1 168 - 89 2 VCC /2 + 1.1 VCC /2 + 0.2 140 MAX 7.5 UNIT V V V mV mV V V V mA
ICC Supply current VCC = 5.25 V For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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SLLS167A - MARCH 1994 - REVISED MARCH 1996
switching characteristics
PARAMETER Transmit jitter tr tf tsu th td Transmit rise time Transmit fall time Setup time, D, CTL, LREQ low or high before SYSCLK Hold time, D, CTL, LREQ low or high after SYSCLK Delay time, SYSCLK to D, CTL CL = 10 pF pF, RL = 55 5 0 5 13 TEST CONDITIONS MIN MAX 0.8 3 3 UNIT ns ns ns ns ns ns
thermal characteristics
PARAMETER RJA RJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance TEST CONDITIONS Board mounted, No air flow MIN TYP 50 12 MAX UNIT C/W C/W
PARAMETER MEASUREMENT INFORMATION
D, CTL, LREQ 50% th1 tsu1 SYSCLK 50%
Figure 1. D, CTL Output Delay Relative to SYSCLK Waveforms
D, CTL
50% td
SYSCLK
50%
Figure 2. D, CTL, LREQ Input Setup and Hold Time Waveforms
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
APPLICATION INFORMATION
TSB11C01 CPS 0.4 M 1 F TYP Cable Power Pair
TPBIAS
56 (each) TPA TPA Cable Pair A One Cable
Cable Port TPB TPB 56 (each) Cable Pair B
250 pF
5 k
To Other Ports
Figure 3. Twisted-Pair Cable Interface Connections
internal register configuration
The accessible internal registers of this device are listed in Table 1 and the description of the fields are listed in Table 2. Table 1. Accessible Internal Registers
ADDRESS 0000 0001 0010 0011 0100 0101 0110 0111 RHB SPD AStat1 AStat2 AStat3 IBR Reserved BStat1 BStat2 BStat3 Ch1 Ch2 Ch3 Reserved Reserved 0 1 2 3 4 GC NP Con1 Con2 Con3 Reserved Reserved Reserved 5 6 R 7 CPS Physical ID
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APPLICATION INFORMATION internal register configuration (continued)
Table 2. Internal Register Field Descriptions
FIELD SIZE (Bits) TYPE These bits give the line state of TPA of port n. 11 = Z 01 = 1 10 = 0 00 = invalid These bits give the line state of TPB of port n, the encoding is the same as AStat(n). When Ch(n) = 1, then port n is a child; otherwise, it is a parent. When Con(n) = 1, then port n is connected; otherwise it is disconnected. This bit is the cable power status for the CPS terminal. This bit initiates bus reset at next opportunity. These bits are the gap count may be changed by the serial bus manager to optimize performance. See the IEEE 1394-1995 standard for details. These bits are the number of ports on this TSB11C01 and are always set to 0011. These bits contain the address of the local node determined during self identification. This bit indicates that the local node is the root. This is the root hold-off bit that instructs the local node to try to become the root during the next bus reset. These bits indicate the top signalling speed of this TSB11C01 and is always cleared. DESCRIPTION
AStat(n)
2
Rd
BStat(n) Ch(n) Con(n) CPS IBR GC NP Physical ID R RHB SPD
2 1 2 1 1 6 4 6 1 1 2
Rd Rd Rd Rd Rd/Wr Rd/ Wr Rd Rd Rd Rd/ Wr Rd
external components and connections
Cable power status (CPS): This terminal is normally connected to the cable power through a 0.4-M resistor. This circuit feeds an internal comparator, which detects the presence of cable power. This information is available to the link layer controller. Oscillator crystal (XI and XO): These terminals are usually connected to an external 24.576-MHz parallel-resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the external crystal used and on circuit board layout. PLL/ VCO filter (PDOUT and VCOIN): These terminals are for an external lag-lead filter required for stable operation of the frequency multiplier running off the crystal oscillator. Test mode control inputs (TESTM1 and TESTM2): These terminals are used in manufacturing to enable production line testing of the TSB11C01. For normal use, these should be tied to VCC. Logic reset input (RESET): When forced low, this terminal causes a bus reset condition on the active cable ports and resets the internal logic to the reset/start state. An internal pullup resistor is provided that is connected to VCC, so only an external delay capacitor is required. This input is a standard logic buffer and may also be driven by a logic buffer. Link power status input (LPS): A 10-k resistor connected to VCC supplying the link layer controller to monitor the link power status. When the link is not powered on, SYSCLK is disabled and the TSB11C01 performs only the basic repeater functions required for network initialization and operation. Link request input (LREQ): An input from the link layer controller that is used by the link to signal the TSB11C01 of a request to perform some service System clock output (SYSCLK): This terminal provides a 49.152-MHz clock signal to which the data, control, and link request information is synchronized.
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APPLICATION INFORMATION external components and connections (continued)
Control I/Os (CTL[0:1]): These terminals are bidirectional signals communicated between the TSB11C01 and the link layer controller that control passage of information between the two devices Data I/Os (D0 and D1): These terminals are bidirectional information signals communicated between the TSB11C01 and the link layer controller Power class bits 0 through 2 inputs (PC[0:2]): These terminals are used as inputs to set the bit values of the three power class bits in the self-ID packet. They may be programmed by tying the terminals high to VCC or low to GND. Enable external clock input (ENCLK100): This terminal is a logic input that allows a choice between using the internal crystal oscillator and PLL frequency multiplier or an external 98.304-MHz signal source. When tied high, the internal crystal oscillator and the PLL are disabled and the external clock input can be used. External clock input (CLK100): When this terminal is asserted high (enabled), an external 98.304-MHz oscillator can drive the TSB11C01. Input voltages as low as 0.2 V peak-to-peak may be used, and the input should be ac coupled through a capacitor of 300 pF or greater. When the crystal oscillator and PLL are being used, it is recommended that this terminal be tied to GND. Twisted-pair cable bias-voltage output (TPBIAS): This terminal provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and for signalling to the remote nodes that there is a valid cable connection. Configuration manager contender input or link-on output (C/LKON): C/LKON is a bidirectional terminal that is used as an input to specify in the self-ID packet that the node is a configuration manager contender. As an output, it signals the reception of a link-on message by supplying a 6.114-MHz signal. The bit-value programming is done by tying the terminal through a 10-k resistor high (VCC) or low (GND). The use of the series resistor allows the link-on output to override the input value when necessary. Current setting resistor (R[0:1]): An internal reference voltage is applied across the resistor connected between these two terminals to set the internal operating currents and the cable driver output currents. A low temperature-coefficient (TC) resistor should be used to meet the IEEE 1394-1995 output voltage limits. Supply filters (AVCC and DVCC): A combination of high-frequency decoupling capacitors is suggested for these terminals, such as paralleled 0.1 F and 0.001 F. These supply lines are separated on the device to provide noise isolation. They should be tied together at a low-impedance point on the circuit board. Individual filter networks are desirable.
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APPLICATION INFORMATION external components and connections (continued)
400 k Cable Power VCC 0.1 F 1 2 3 4 5 12 pF VCC 12 pF 6 7 0.1 F 560 8 9 96 0.01 F 10 k 1000 pF VCC 10 11 0.1 F VCC 12 13 14 15 16 17 18 10 k Link VCC 19 20 Link Controller Interface VCC VCC 23 0.1 F 24 25 Link Controller Interface 26 27 28 21 22 CPS AVCC AVCC XI XO AVCC AVCC PDOUT VCOIN TESTM2 RESET ISO AGND AGND AGND AGND AGND DGND LPS DGND LREQ TESTM1 DVCC SYSCLK CTL0 CTL1 D0 D1 TSB11C01 TPA1 TPA1 TPB1 TPB1 TPA2 TPA2 TPB2 TPB2 TPA3 TPA3 TPB3 TPB3 AGND AGND AGND AGND AGND R0 R1 PC2 TPBIAS PC1 PC0 DVCC CLK100 ENCLK100 DGND C/LKON 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 LKON Contender Programming 10 k Power Class Programming VCC 0.1 F Power Class Programming TPBIAS 1 F 6.36 k 0.5% TP Cables
Figure 4. External Component Hookup Circuit
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
PRINCIPLES OF OPERATION external components and connections (continued)
The TSB11C01 is designed to operate with a link layer controller such as the Texas Instruments TSB12C01A. These devices use an interface described in annex I of the IEEE 1394-1995 standard. Details of how the TSB12C01A devices operate are described in the TSB12C01A data manual (literature number SLLS219). The following describes the operation of the physical (phy) link interface. The TSB11C01 supports 100 Mbits/s data transfers and has two bidirectional data lines D[0:1] crossing the interface. In addition, there are two bidirectional control lines CTL[0:1], the 50-MHz SYSCLK line from the TSB11C01 to the link, and the link request line (LREQ) from the link to the TSB11C01. The TSB11C01 has control of all the bidirectional terminals. The link is allowed to drive these terminals only after it has been given permission by the TSB11C01. The dedicated LREQ request terminal is used by the link for any activity it wishes to initiate. There are four operations that may occur in the phy link interface: request, status, transmit, and receive. With the exception of the request operation, all actions are initiated by the TSB11C01. When the TSB11C01 has control of the bus the CTL[0:1] lines are encoded as shown in Table 3. Table 3. TSB11C01 Control of Bus Functions
CTL [0:1] 00 01 10 11 NAME Idle Status Receive Transmit DESCRIPTION OF ACTIVITY No activity is occurring (this is the default mode). Status information is being sent from the TSB11C01 to the link An incoming packet is being sent from the TSB11C01 to the link The link has been given control of the bus to send an outgoing packet.
When the link has control of the bus (TSB11C01 permission) the CTL[0:1] lines are encoded as shown in Table 4. Table 4. Link Control of Bus Functions
CTL [0:1] 00 01 10 11 NAME Idle Hold Transmit Reserved DESCRIPTION OF ACTIVITY The link has released the bus (transmission has been completed). The link is holding the bus prior to sending a packet. An outgoing packet is being sent from the link to the TSB11C01. None
When the link wishes to request the bus or access a register that is located in the TSB11C01, a serial stream of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer is a bus request, a read command, or a write command (see Table 5). Regardless of the type of transfer, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end of the stream. Bit 0 is the most significant and is transmitted first. Table 5. Link Request Functions
NO. of BITS 7 9 17 REQUEST TYPE Bus Request Read Register Request Write Register Request
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PRINCIPLES OF OPERATION external components and connections (continued)
For a bus request, the length of the LREQ data stream is 7 bits, as shown in Table 6. Table 6. Bus Request Functions
BIT(S) 0 1-3 4-5 6 NAME Start Bit Request Type Request Speed Stop Bit DESCRIPTION This bit indicates the beginning of the transfer (always a 1). This bit indicates the type of bus request (see Table 7 for the encoding of this field). These bits should always be 00 for the TSB11C01 100-Mbits/s speed. This bit indicates the end of the transfer (always a 0).
For a read register request, the length of the LREQ data stream is 9 bits, as shown in Table 7. Table 7. Read Register Request Functions
BIT(S) 0 1-3 4-7 8 NAME Start Bit Request Type Address Stop Bit DESCRIPTION This bit indicates the beginning of the transfer (always a 1). These bits are always a 100 indicating that this is a read register request. These bits contain the address of the TSB11C01 register to be read. This bit indicates the end of the transfer (always a 0).
For a write register request, the length of the LREQ data stream is 17 bits, as shown in Table 8 and LREQ timing is shown in Figure 5. Table 8. Write Register Request Functions
BIT(S) 0 1-3 4-7 8 - 15 16 NAME Start Bit Request Type Address Data Stop Bit DESCRIPTION This bit indicates the beginning of the transfer (always a 1). These bits are always a 101 indicating that this is a write register request. These bits conatin the address of the TSB11C01 register to be written to. These bits contain the data that is to be written to the specified register address. This bit indicates the end of the transfer (always a 0).
LREQ0
LREQ1
LREQ2
LREQ3
LREQn
Figure 5. LREQ Timing (Each Cell Represents One Clock-Sample Time)
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PRINCIPLES OF OPERATION external components and connections (continued)
The 3-bit request-type field has the following possible values as shown in Table 9. Table 9. Request Functions
LREQ[1:3] 000 001 010 011 100 101 110, 111 NAME TakeBus IsoReq PriReq FairReq RdReg WrReg Reserved DESCRIPTION Immediate request. Upon detection of an idle, take control of the bus immediately (no arbitration). Isochronous request. Arbitrate after an isochronous gap. Priority request. Arbitrate after a fair gap, ignore fair protocol. Fair request. Arbitrate after a fair gap; use fair protocol. Return the specified register contents through a status transfer. Write to the specified register. Reserved
bus request
For fair or priority access, the link requests control of the bus at least one clock after the phy link interface becomes idle. When the link senses that the CTL terminals are in a receive state (CTL[0:1] = 10), it knows that the request has been lost. This is true any time during or after the link sends the bus request transfer. The TSB11C01 ignores any fair or priority requests when it asserts the receive state while the link is requesting the bus. The link then reissues the request one clock after the next interface idle. The cycle master uses a normal priority request to send a cycle start message. After receiving a cycle start, the link can issue an isochronous bus request. When arbitration is won, the link proceeds with the isochronous transfer of data. The isochronous request is cleared in the TSB11C01 once the link sends another type of request or when the isochronous transfer has been completed. The TakeBus request is issued when the link needs to send an acknowledgment after reception of a packet addressed to it. This request must be issued during packet reception. This is done to minimize the delays that the TSB11C01 has to wait between the end of a packet and the transmittal of an acknowledgment. As soon as the packet ends, the TSB11C01 immediately grants access of the bus to the link. The link sends an acknowledgment to the sender unless the header cycle redundancy check (CRC) of the packet is bad. In this case, the link releases the bus immediately; it is not be allowed to send another type of packet on this grant. To ensure this, the link is forced to wait 160 ns after the end of the packet is received. The TSB11C01 then gains control of the bus and the acknowledgment indicating the CRC error is sent. The bus is released and allowed to proceed with another request. It is conceivable that two separate nodes might believe that an incoming packet is intended for them. The nodes then issue a TakeBus request before checking the CRC of the packet. Since both nodes seize control of the bus at the same time, a temporary localized collision of the bus occurs somewhere between the competing nodes. This collision would be interpreted by the other nodes on the network as being a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken node drops its request and the false line state is removed. The only side effect is the loss of the intended acknowledgment packet (this is handled by the higher layer protocol).
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
PRINCIPLES OF OPERATION read/write requests
When the link requests to read the specified register contents, the TSB11C01 sends the contents of the register to the link through a status transfer. If an incoming packet is received while the TSB11C01 is transferring status information to the link, the TSB11C01 continues to attempt to transfer the contents of the register until it is successful. For write requests, the TSB11C01 loads the data field into the appropriately addressed register as soon as the transfer has been completed. The link is allowed to request read or write operations at any time. A status transfer is initiated by the TSB11C01 when it has some status information to transfer to the link. The transfer is initiated by asserting CTL[0:1] = 01 and D[0:1] = 00 (100 Mbits/s only). The D[0:1] = 00 represents the speed at which the status transfer is to occur; status information at 100 Mbits/s is always transmitted two bits at a time. The status transfer can be interrupted by an incoming packet from another node. When this occurs, the TSB11C01 attempts to resend the status information after the packet has been acted upon. The TSB11C01 continues to attempt to complete the transfer until the information has been successfully transmitted.
NOTE There must be at least one idle cycle between consecutive status transfers. The definition of the bits in the status transfer is shown in Table 10.
status request
Length of stream: 4 or 16 bits Table 10. Status Request Functions
BIT(s) 0 1 NAME Arbitration Reset Gap Subaction Gap DESCRIPTION This bit indicates that the TSB11C01 has detected that the bus has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used by the link in its busy/retry state machine. This bit indicates that the TSB11C01 has detected that the bus has been idle for a subaction gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used by the link to detect the completion of an isochronous cycle. This bit indicates that the TSB11C01 has entered the bus reset state The TSB11C01 has stayed in a particular state for too long. These bits hold the address of the TSB11C01 register whose contents are transferred to the link. The data that is to be sent to the link
2 3 4-7 8 - 15
Bus Reset State Time Out Address Data
Normally, the TSB11C01 sends just the first 4 bits of status data to the link. These bits are used by the link state machines; however, when the link has initiated a read register request the TSB11C01 sends the full status packet to the link (see Figure 6). The TSB11C01 also sends a full status packet to the link if it has some important information to pass on to the link. Currently, the only condition where this occurs is after the self identification process when the TSB11C01 needs to inform the link of its new node address (physical ID register).
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15
TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
PRINCIPLES OF OPERATION status request (continued)
TSB11C01 CTL[0:1]
00
01
01 S(0,1)
01
01
00
00
S(14, 15) 00 S(2,3) 00
TSB11C01 D[0:1]
00
00
Figure 6. Status Transfer Timing There may be times where the TSB11C01 wants to start a second status transfer. The TSB11C01 waits at least one clock cycle with the CTL lines idle before it begins a second transfer.
transmit
When the link wants to transmit information, it first requests access to the bus through the LREQ line. When the TSB11C01 receives this request, it arbitrates to gain control of the bus. When the TSB11C01 wins ownership of the bus, it grants the bus to the link by asserting the transmit state on the CTL terminals for at least one SYSCLK cycle. The link takes control of the bus by asserting either hold or transmit on the CTL lines. Hold is used by the link to keep control of the bus if it needs more time to prepare the data for transmission. The TSB11C01 keeps control of the bus for the link by asserting a data-on state on the bus. It is not necessary for the link to use hold when it is ready to transmit as soon as bus ownership is granted. When the link is prepared to send data, it asserts transmit on the CTL lines as well as sending the first bits of the packet on the D[0:1] lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The link then asserts idle on the CTL lines for one clock cycle, after which it releases control of the interface. There are times when the link needs to send another packet without releasing the bus. For example, the link may want to send consecutive isochronous packets or it may want to attach a response to an acknowledgment. To do this, the link asserts hold instead of idle when the first packet of data has been completely transmitted. Hold, in this case, informs the TSB11C01 that the link needs to send another packet without releasing control of the bus. The TSB11C01 waits a set amount of time before asserting transmit, and the link can then proceed with the transmission of the second packet. After all data has been transmitted and the link has asserted idle on the CTL lines, the TSB11C01 asserts its own idle state on the CTL lines. When sending multiple packets in this fashion, all data must be transmitted at the same speed. This is because the transmission speed is set during arbitration, and since the arbitration step is skipped, there is no way of informing the network of a change in speed.
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TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
PRINCIPLES OF OPERATION transmit timing
Transmit timing is shown in Figure 7.
TSB11C01 CTL[0:1] TSB11C01 D[0:1] Link CTL[0:1] Link D[0:1] 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
ZZ
ZZ
ZZ
01
01
10
10
10
10
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
D0
D1
D2
Dn
00
ZZ
ZZ
SINGLE PACKET TSB11C01 CTL[0:1] TSB11C01 D[0:1] Link CTL[0:1] Link D[0:1] ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
10
10
01
00
ZZ
ZZ
ZZ
ZZ
01
01
10
10
Dn-1
Dn
00
00
ZZ
ZZ
ZZ
ZZ
00
00
D0
D1
CONTINUED PACKET
ZZ = high-impedance state
D0 - Dn = packet data
Figure 7. Transmit Timing
receive operation
When data is received by the TSB11C01 from the serial bus, it transfers the data to the link for further processing. The TSB11C01 asserts receive (10) on the CTL lines and 11 on the D lines. The TSB11C01 indicates the start of the packet by placing the speed code on the data bus. The TSB11C01 then proceeds with the transmission of the packet to the link on the D lines while keeping the receive status on the CTL lines. Once the packet has been completely transferred, the TSB11C01 asserts idle on the CTL lines to complete the receive operation. The speed code is a phy link protocol and not included in the CRC.
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17
TSB11C01 IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996
PRINCIPLES OF OPERATION receive timing
The receive timing is shown in Figure 8.
TSB11C01 CTL[0:1] TSB11C01 D[0:1] 00 10 10 10 10 10 10 00 00
00
11
11
SPD D0
D1
Dn
00
00
SPD = speed code
D0 - Dn = packet data
Figure 8. Receive Timing The speed code for the receiver is shown in Table 11. Table 11. Receiver Speed Code
D[0:1] DATA RATE 100 Mbits/s
00
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