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| Universal Operational Amplifier Single, Dual, Quad (SOIC) Evaluation Module With Shutdown User's Guide October 1999 Mixed-Signal Products SLOU061 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated Preface Related Documentation From Texas Instruments J Amplifiers, Comparators, and Special Functions Data Book (literature number SLYD011 and SLYD012). This data book contains data sheets and other information on the TI operational amplifiers that can be used with this evaluation module. Operational Amplifier Supplement Data Book (literature number SLOD002). This data book contains data sheets and other information on the TI operational amplifiers that can be used with this evaluation module. Power Management Products Data Book (literature numbers SLVD003, SLVD004, and SLVD005). This data book contains data sheets and other information on the TI shunt regulators that can be used with this evaluation module. J J FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks TI is a trademark of Texas Instruments Incorporated. PowerPAD is a trademark of Texas Instruments Incorporated. Chapter Title--Attribute Reference iii iv Running Title--Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Evaluation Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Physical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Area 100 - Single Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Area 200 - Dual Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Area 300 - Quad Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 EVM Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 2-3 2-4 2-5 2-7 2-8 2-9 2 3 Example Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 Non-Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.5 Sallen-Key Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.6 Sallen-Key High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.7 Two Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.8 Quad Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Chapter Title--Attribute Reference v Running Title--Attribute Reference Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 Area 100 Schematic--Single Device, SOIC (8-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Area 200 Schematic--Dual Device, SOIC (14-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Area 300 Schematic--Quad Device, SOIC (16-pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Maximum Power Dissipation vs Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 EVM Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 EVM Board Layout--Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 EVM Board Layout--Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Inverting Amplifier With Dual Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Non-Inverting Amplifier With Single Supply Using Area 100 . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 . . 3-4 Sallen-Key Low-Pass Filter With Dual Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . . . . 3-5 Sallen-Key High-Pass Filter With Single Supply Using Area 200 . . . . . . . . . . . . . . . . . . . . . 3-7 Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 200 3-9 Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300 3-11 Table 2-1 Dissipation Rating Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 vi Chapter 1 Introduction This user's guide describes the universal operational amplifier single, dual, quad (SOIC) evaluation module (EVM) with shutdown (SLOP248). The EVM simplifies evaluation of Texas Instruments surface-mount op amps with or without shutdown feature. Topic 1.1 1.2 Page Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Introduction 1-1 Design Features 1.1 Design Features The EVM board design allows many circuits to be constructed easily and quickly. There are three circuit development areas on the board, and each uses IC amplifiers in the SOIC package. Area 100 is for a single operational amplifier (op amp), with or without shutdown. It also features offset nulling pin pads. Area 200 is for a dual op amp, with or without shutdown. Area 300 is for a quad op amp, with or without shutdown. A few possible circuits include: - Voltage follower Noninverting amplifier Inverting amplifier Simple or algebraic summing amplifier Difference amplifier Current to voltage converter Voltage to current converter Integrator/low-pass filter Differentiator/high-pass filter Instrumentation amplifier Sallen-Key filter The EVM PCB is of two-layer construction, with a ground plane on the solder side. Circuit performance should be comparable to final production designs. 1.2 Power Requirements The devices and designs that are used dictate the input power requirements. Three input terminals are provided for each area of the board: Vx+ GNDx Vx- Positive input power for area x00 i.e., V1+ area 100 Ground reference for area x00 i.e., GND2 area 200 Negative input power for area x00 i.e., V3- area 300 Each area has four bypass capacitors - two for the positive supply, and two for the negative supply. Each supply should have a 1-F to 10-F capacitor for low frequency bypassing and a 0.01-F to 0.1-F capacitor for high frequency bypassing. When using single-supply circuits, the negative supply is shorted to ground by bridging C104 or C105 in area 100, C209 or C210 in area 200, or C311 or C312 in area 300. Power input is between Vx+ and GNDx. The voltage reference circuitry is provided for single-supply applications that require a reference voltage to be generated. 1-2 Introduction Chapter 2 Evaluation Module Layout This chapter shows the universal operational amplifier single, dual, quad (SOIC) evaluation module (EVM) with shutdown board layout, shows schematics of each area, and describes the relationships between the three areas. Topic 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Page Physical Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Area 100--Single Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Area 200--Dual Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Area 300--Quad Device SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 General Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . 2-7 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Evaluation Module Layout 2-1 Physical Considerations 2.1 Physical Considerations The EVM board has three circuit development areas. Each area can be separated from the others by breaking along the score lines. The circuit layout in each area supports an op amp package, voltage reference, and ancillary devices. The op amp package is unique to each area as described in the following paragraphs. The voltage reference and supporting devices are the same for all areas. Surface-mount or through-hole components can be used for all capacitors and resistors on the board. The voltage reference can be either surface-mount or through-hole. If surface mount is desired, the TLV431ACDBV5 or TLV431AIDBV5 adjustable shunt regulators can be used. If through hole is desired, the TLV431ACLP, TLV431AILP, TL431CLP, TL431ACLP, TL431ILP or TL431AILP adjustable shunt regulators can be used. Refer to Texas Instruments' Power Supply Circuits Data Book (literature number SLVD002) for details on usage of these shunt regulators. Each passive component (resistor or capacitor) has a surface-mount 1206 footprint with through holes at 0.2 spacing on the outside of the 1206 pads. C105, C106, C107, C207, C208, C209, C312, C314, and C315 have a surface-mount 1210 footprint with through holes at 0.2 spacing on the outside of the 1210 pads. Therefore, either surface-mount or through-hole parts can be used. The potentiometer for the offset nulling feature in area 100 can also be either a surface-mount or a through-hole unit. Figures 2-1 through 2-3 show schematics for each of the board areas. The schematics show all components that the board layout can accommodate. These should only be used as reference, since not all components will be used at any one time. 2-2 Evaluation Module Layout Physical Considerations 2.2 Area 100--Single Device SOIC Area 100 uses 1xx reference designators, and is compatible with a single op amp, with or without shutdown, packaged as an 8-pin SOIC, with or without PowerPAD. This surface-mount package is designated by a D suffix in TI part numbers, as in TxxxxCD, TxxxxID, etc. Offset nulling can be extremely important in some applications. The EVM accommodates TI IC op amps that provide this feature. The input offset can be adjusted by connecting a 100 k potentiometer between terminals 1 and 5 of the device and connecting the wiper to VCC- via a resistor (R101) as shown below. This resistor is used to fine tune the offset adjustment. For example, when using the TLC070 or TLC071 device and a 100 k nulling potentiometer, the offset voltage adjustment is 10 mV when R101 is 5.6 k and 3 mV when R101 is 20 k. When using the non-shutdown version of the device, pin 8 of the IC is a no connect. Figure 2-1 shows the area 100 schematic. Figure 2-1. Area 100 Schematic--Single Device, SOIC (8 pin) V1+ V1+ C107 GND1 R109 C105 V1- Power Supply Bypass V1- C104 A102- A103+ A104+ R102 R103 R104 2 7 -8 4 C108 R110 A101- C109 R114 C110 R112 V1+ U101 SD 6 5 OUT 3+ 1 V1- R107 R106 A1 FLT C103 R108 V1+ U102 R111 VREF1 C101 R105 R101 C102 V1- C106 R113 Voltage Reference Evaluation Module Layout 2-3 Physical Considerations 2.3 Area 200--Dual Device SOIC Area 200 uses 2xx reference designators, and is compatible with dual op amps, with or without shutdown, packaged as an 8-pin (without shutdown) or 14-pin (with shutdown) SOIC. This package is designated by a D suffix in TI part numbers, as in TxxxxCD. When using the non-shutdown version of the device, ensure that the IC is aligned at the top of the IC pad array--the last six PCB pads (3 on each side -- pins 5, 6, 7, 8, 9, and 10) will not be used. Figure 2-2 shows the area 200 schematic. Figure 2-2. Area 200 Schematic--Dual Device, SOIC (14 pin) R216 V2+ R221 V2+ C206 GND2 C209 V2- Power Supply Bypass V2- C210 A204+ R217 C212 C207 A202- A203+ A201- R220 R219 R218 C215 C211 R212 V2+ 14 2 - 3+ 6 1 4 U201a A2/SD A2OUT 1/2 Dual Op Amp V2- R214 R215 A2 FLT C214 C213 R210 V2+ U202 R211 R204 B201- C208 R213 R203 B202- B203+ Voltage Reference B204+ R202 R201 VREF2 R207 C203 C202 R206 9 12 R205 11 - + 13 U201b B2/SD B2OUT 1/2 Dual Op Amp R208 R209 C204 B2 FLT C205 C201 2-4 Evaluation Module Layout Physical Considerations 2.4 Area 300--Quad Device SOIC Area 300 uses 3xx reference designators, and is compatible with quad op amps, with or without shutdown, packaged in a 14-pin (without shutdown) or 16-pin (with shutdown) SOIC. This surface-mount package is designated by a D suffix in TI part numbers, as in TxxxxID. When using the non-shutdown version of the device, ensure that the IC is aligned at the top of the IC pad array--the last two PCB pads (1 on each side -- pins 8 and 9) will not be used. Figure 2-3 shows the area 300 schematic. Evaluation Module Layout 2-5 Physical Considerations Figure 2-3. Area 300 Schematic--Quad Device SOIC (16 pin) V3+ V3+ C313 GND3 C311 V3- Power Supply Bypass V3- C312 A302- R306 A303+ A304+ R308 R314 C310 C304 R310 B301- R312 B302- B303+ B304+ R315 C307 R311 R316 B3 FLT C306 R323 C317 R313 R317 6 C308 R318 C303 - 5+ R307 R305 C314 A301- R303 2 R301 C301 R302 V3+ 4 -8 AB3/SD 1 A3 OUT R304 C302 3+ U301A 13 V3- R309 A3 FLT C305 7 U301B B3 OUT C309 C301- R323 C316 R325 R324 C302- R327 R331 C324 C303+ C304+ R332 D301- R333 D302- R335 D303+ D304+ R336 C322 R337 C323 R338 D3 FLT V1+ R334 15 C321 R339 R329 C318 R326 11 - 9 10 U301C CD3/SD C3 OUT 12 + R330 C3 FLT R328 C320 - 14 + 16 U301D D3 OUT C319 R321 VREF3 U302 R320 C325 R319 C315 Voltage Reference 2-6 Evaluation Module Layout General Power Dissipation Considerations 2.5 General Power Dissipation Considerations For a given JA, the maximum power dissipation is shown in Figure 2-4 and is calculated by the following formula: P Where: + D T -T MAX A q JA PD = Maximum power dissipation of Txxxx IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) Figure 2-4. Maximum Power Dissipation vs Free-Air Temperature MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 SOIC (16-pin) Package Low-K Test PCB JA = 114.7C/W TJ = 150C Maximum Power Dissipation - W 1.5 SOIC (8-pin) Package Low-K Test PCB 1 0.5 SOIC (14-pin) Package Low-K Test PCB 0 -55 -25 5 35 65 95 TA - Free-Air Temperature - C 125 NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Table 2-1. Dissipation Rating Table PACKAGE D (8) D (14) D (16) JC (C/W) 38.3 26.9 25.7 JA (C/W) 176 122.3 114.7 TA 25C POWER RATING 710 mW 1022 mW 1090 mW Evaluation Module Layout 2-7 EVM Component Placement 2.6 EVM Component Placement Figure 2-5 shows component placement for the EVM board. Figure 2-5. EVM Component Placement 2-8 Evaluation Module Layout EVM Board Layout 2.7 EVM Board Layout Figures 2-6 and 2-7 show the EVM top and bottom board layouts, respectively. Figure 2-6. EVM Board Layout--Top Evaluation Module Layout 2-9 EVM Board Layout Figure 2-7. EVM Board Layout--Bottom 2-10 Evaluation Module Layout Chapter 3 Example Circuits This chapter shows and discusses several example circuits that can be constructed using the universal operational amplifier EVM. The circuits are all classic designs that can be found in most operational amplifier design books. Topic 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Page Schematic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Noninverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Sallen-Key Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Sallen-Key High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Two Operational Amplifier Instrumentation Amplifier . . . . . . . . . . . . 3-8 Quad Operational Amplifier Instrumentation Amplifier . . . . . . . . . 3-10 Example Circuits 3-1 Schematic Conventions 3.1 Schematic Conventions Figures 3-1 through 3-6 show schematic examples of circuits that can be constructed using the universal operational amplifier EVM with shutdown. The components that are placed on the board are shown in bold. Unused components are blanked out. Jumpers and other changes are noted. These examples are only a few of the many circuits that can be built. 3.2 Inverting Amplifier Figure 3-1 shows area 100 equipped with a single operational amplifier configured as an inverting amplifier using dual power supplies. Basic setup is done by choice of input and feedback resistors. The transfer function for the circuit as shown is: V OUT + *VIN R112 R109 To cancel the effects of input bias current, set R105 = R112 || R109, or use a 0- jumper for R105 if the operational amplifier is a low input bias operational amplifier. Figure 3-1. Inverting Amplifier With Dual Supply Using Area 100 R114 V1+ R110 V1+ C107 0.1 F GND1 C105 0.1 F C104 10 F C108 10 F A101- V1+ R109 A102- A103+ R102 + A104- Vin Power Supply Bypass V1- - C101 R105 R106 A1 FLT V1+ R108 VREF1 C102 C103 R103 R104 2 - 7 4 V1- 8 6 U101 R105 = R112 II R109, or Short if Using Low Input Bias Op Amp C109 C110 R112 R112 VOUT = -VIN R109 SD A OUT 3+ V1- - 3+ 1 C106 R107 2 6 5 R111 R R113 C U102 A Optional 100 k R101 V1- 5.6 k Voltage Reference Not Used 3-2 Example Circuits Noninverting Amplifier 3.3 Noninverting Amplifier Figure 3-2 shows area 100 equipped with a single operational amplifier configured as a noninverting amplifier with single-supply power input. Basic setup is done by choice of input and feedback resistors. The transfer function for the circuit as shown is: V OUT + VIN 1 ) R112 ) VREF1 R109 The input signal must be referenced to VREF1. To cancel the effects of input bias current, set R102 = R112 || R109, or use a 0- jumper for R102 if the operational amplifier is a low input bias operational amplifier. The TL431 adjustable precision shunt regulator, configured as shown, provides a low impedance reference for the circuit at about 1/2 V1+ in a 3 V system. Another option is to adjust resistors R113 and R111 for the desired VREF1 voltage. The formula for calculating VREF1 is: VREF1 + 1.24 V R111 ) R113 R113 Figure 3-2. Noninverting Amplifier With Single Supply Using Area 100 V1+ V1+ C107 0.1 F Jumper GND1 C108 10 F C104 R110 A101+ Jumper 102 - to VREF1 C105 A102- A103+ Power Supply Bypass V1- A104- V1- V1+ R108 2.2 k VREF1 = 1.24 V Jumper C102 R111 C R R113 U102 = TLV431ACDBV5 A C106 10 F Input Signal With Reference to VREF1 R102 = R112 II R109, or Short if Using Low Input Bias Op Amp C103 + Vin - R106 1 FLT R103 R102 R104 R109 C109 R112 V1+ 7 2 - 3+ 4 8 6 U101 VOUT = VIN 1 + SD 1 OUT R114 C110 ( R112 R109 ) + VREF4 V1- C101 R105 2 - 3+ 1 R107 6 5 Voltage Reference Optional 100 k R101 V1- 5.6 k Example Circuits 3-3 Differential Amplifier 3.4 Differential Amplifier Figure 3-3 shows area 100 equipped with a single operational amplifier configured as a differential amplifier using a voltage reference and single power supply. Basic setup is done by choice of input and feedback resistors. The transfer function for the circuit as shown is: V Where R112 R109 OUT + VIN R112 R109 ) VREF1 + R102 R103 The TLV431 adjustable precision shunt regulator, configured as shown, provides a low impedance reference for the circuit at about 1/2 V1+ in a 3-V system. Another option is to adjust resistors R111 and R113 for the desired VREF1 voltage. The formula for calculating VREF1 is: VREF1 + 1.24 V R111 ) R113 R113 Figure 3-3. Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 R114 V1+ R110 V1+ C107 0.1 F Jumper C110 R112 C109 R112 Vout = Vin V1+ R109 7 8 2 1/SD - 6 1OUT 3+ U101 4 101- C108 10 F + 102- Vin 103+ - 104+ R109 R103 R102 R104 Jumper ( ) + VREF1 GND1 C105 C104 V1- Power Supply Bypass V1+ R108 2.2 k V1- R112 R102 = R109 R103 C101 R105 R106 A1 FLT C102 Jumper 104+ to VREF1 C103 V1- VREF1 = 1.24 V R111 R R113 C A U102 TLV431ACDBV5 C106 10 F Voltage Reference 3-4 Example Circuits Sallen-Key Low-Pass Filter 3.5 Sallen-Key Low-Pass Filter Figure 3-4 shows area 200 equipped with a dual operational amplifier configured as a second-order Sallen-Key low-pass filter using dual-power supplies. Basic setup is done by proper choice of resistors R and mR and capacitors C and nC. The transfer function is: V OUT V IN Where: fo And Q + 1 1 * 2 f fo ) j Q f fo + 2p 1 m n RC + mm n )1 R216 C211 R212 Figure 3-4. Sallen-Key Low-Pass Filter With Dual Supply Using Area 200 V2+ A201- V2+ C206 0.1 F GND2 C209 0.1 F C210 10 F C207 10 F R221 C215 Jumper V2+ Vout Vin = 1 1- (f/fo)2 + (j/Q)(f/fo) R220 A202- A203+ A204+ R217 + Vin - C212 R219 mR R218 R 2 14 - 4 V2- 6 1 U201A A2/SD A2OUT 1/2 Dual Op Amp fo = Q= R214 1 2 mn RC mn m+1 A2 FLT C214 3+ V2- Power Supply Bypass V2- R215 C213 nC V2+ R207 R210 VREF2 R204 B201- R211 R R213 B204+ Jumper Not Used R209 C U202 A C208 R203 B202- B203+ R201 R202 R205 C202 R206 Jumper 12 9 - 13 U201B B2/SD B2OUT C203 11 + 1/2 Dual Op Amp Voltage Reference Not Used C204 R208 B2 FLT C205 C201 Example Circuits 3-5 Sallen-Key High-Pass Filter 3.6 Sallen-Key High-Pass Filter Figure 3-5 shows area 200 equipped with a dual operational amplifier configured as a second-order Sallen-Key high-pass filter using single-supply power input. Basic setup is done by proper choice of resistors R and mR and capacitors C and nC. Note that capacitors should be used for components R201 and R205, and a resistor for C201. The transfer function for the circuit as shown is: V OUT Where: +V * IN 2 f fo f fo 1 fo And Q ) j Q * 2 ) VREF2 f fo + 2p 1 m n RC + nm n )1 The TL431 adjustable precision shunt regulator, configured as shown, provides a low impedance reference for the circuit at about 1/2 V2+ in a 5 V system. Another option is to adjust resistors R211 and R213 for the desired VREF2 voltage. The formula for calculating VREF2 is: VREF2 + 2.50 V R211 ) R213 R213 3-6 Example Circuits Sallen-Key High-Pass Filter Figure 3-5. Sallen-Key High-Pass Filter With Single Supply Using Area 200 R216 V2+ R221 V2+ C206 0.1 F Jumper GND2 C209 C207 10 F C210 A204+ Jumper A201- R220 A202- A203+ R217 R219 R218 C215 Jumper V2+ 6 14 2 - 1 3+ U201A 4 V2- C211 R212 A2/SD A2OUT 1/2 Dual Op Amp Not Used V2- Power Supply Bypass V2- C212 R215 R214 A2 FLT C213 C214 R207 VREF2 = 2.5 V V2+ R210 2.2 k C203 R206 R204 B201- R203 B202- B204+ R202 mR R201 C + Vin - C202 Jumper 12 11 R205 fo = nC C204 R209 R208 Q= 9 - + 13 U201B VOUT = VIN -(f/fo)2 1+(j/Q)(f/fo) - (f/fo)2 + VREF2 B2/SD B2OUT 1/2 Dual Op Amp 1 2 mn RC mn m+1 B2 FLT Jumper R211 R R213 C A U202 TL431ACLP C208 10 F B203+ Jumper B204 + to VREF2 Voltage Reference C201 R C205 Example Circuits 3-7 Two Operational Amplifier Instrumentation Amplifier 3.7 Two Operational Amplifier Instrumentation Amplifier Figure 3-6 shows area 200 equipped with a dual operational amplifier configured as a two-operational-amplifier instrumentation amplifier using a voltage reference and single power supply. Basic setup is done by choice of input and feedback resistors. The transfer function for the circuit as shown is: V Where R212 = R206 and R221 = R203 To cancel the effects of input bias current, set R217 = R212 || R220 and set R202 = R206 ||R203, or use a 0- jumper for R217 and R202 if the operational amplifier is a low input bias operational amplifier. The TLV431 adjustable precision shunt regulator, configured as shown, provides a low impedance reference for the circuit at about 1/2 V2+ in a 3 V system. Another option is to adjust resistors R211 and R213 for the desired VREF2 voltage. The formula for calculating VREF2 is: VREF2 OUT + VIN 1 ) 2R212 ) R212 ) VREF2 R220 R221 + 1.24 V R211 ) R213 R213 3-8 Example Circuits Two Operational Amplifier Instrumentation Amplifier Figure 3-6. Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 200 R216 C211 Jumper A201 - to B2OUT R212 R217 = R212 II R220 or Short if Using Low Input Bias Op Amp V2+ A203+ V2+ C206 0.1 F Jumper GND2 C207 10 F Jumper A202- to B201- C212 R215 R217 A204+ R221 A201- Jumper R220 A202- R219 R218 C215 2R212 R212 VOUT = Vin R220 + R221 V2+ 14 6 2 A2/SD - 1 A2OUT 3+ U201A 4 1/2 Dual Op Amp V2- R212 = R206 R221 = R203 R214 A2 FLT C213 Vin - R207 V2+ Jumper VREF2 to B202- R204 B201- Jumper R203 R211 C R R213 U202 A TLV431ACDBV5 B204+ B202- C208 10 F B203+ R201 R205 Jumper 12 11 9 - + 13 U201B B2/SD B2OUT 1/2 Dual Op Amp C202 C203 R206 C214 (1+ )+ VREF2 C209 C210 V2- + Power Supply Bypass V2- R210 2.2 k VREF2 = 1.24 V Jumper R202 Voltage Reference R202 = R206 II R203 or Short if Using Low Input Bias Op Amp R209 C204 R208 B2 FLT C201 C205 Example Circuits 3-9 Quad Operational Amplifier Instrumentation Amplifier 3.8 Quad Operational Amplifier Instrumentation Amplifier Figure 3-7 shows area 300 equipped with a quad operational amplifier configured as a quad-operational-amplifier instrumentation amplifier using a dual power supply. Basic setup is done by choice of input and feedback resistors. The transfer function for the circuit as shown is: V OUT Where R302 = R318, R309 = R316, and R325 = R329 AV + V INB *V R303 INA ) 2(R302) ) R325 R309 R303 + R303 2(R302) R303 ) ) R325 + 101 R309 as shown To cancel the effects of offset errors, adjust Vadj (D304+) by applying an extra signal. 3-10 Example Circuits Quad Operational Amplifier Instrumentation Amplifier Figure 3-7. Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300 R304 C302 R302 R301 A301- R303 100 A302- A303+ A304+ R308 + VINA - V3+ 2.5 = V3+ 10 F GND3 AB3/SD 1 A3 OUT 10 F 2.5 = V3- Power Supply Bypass R309 A3 FLT V3- C311 C313 0.1 F C314 0.1 F C312 C301 5 k V3+ 4 2 -8 3+ Jumpers R306 R305 U301A 13 V3- C304 R307 10 k C305 C303 R323 C317 R325 R323 C301- R324 C302- R314 C310 R318 R310 B301- R312 B302- B303+ R313 B304+ R315 + VINB - C316 10 k Jumpers R326 11 9 - 10 12 + U301C CD3/SD C3 OUT R327 10 k R329 C303+ C304+ C308 5 k 6 - R330 C3 FLT C318 R328 C320 Jumpers R317 5+ 7 U301B B3 OUT C319 B3 FLT R316 C307 R311 10 k C306 C309 R321 V3+ R331 C324 U302 R339 R332 D301- R333 D302- R335 D303+ D304+ R336 Jumper + Vadj - VREF3 R320 C321 Jumper R319 15 R334 - 14 + 16 U301D D3 OUT C315 Voltage Reference R338 D3 FLT C322 R337 C323 C325 Example Circuits 3-11 3-12 Example Circuits |
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