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W83791D Winbond H/W Monitoring IC
W83791D
W83791D DataSheet Revision History
Pages
1 2 3 4 5 P. 40 P. 42 P. 60/61 P. 58/59 P. 66 P. 66 P. 66 P. 87 6 7 All pages n.a 09/Aug 11/Apr 0.71 1.0 n.a. 1.0 n.a. n.a. P.7 P.34 P.43/44 01/Jan 01/Jan 19/Mar 21/May 0.5 0.51 0.6 0.7
Dates
Version
Version on Web
n.a. n.a. n.a. n.a. n.a.
Main Contents
All version before 0.5 are for internal use. First publication. (1) Revise SLOTOCC# pin description. (2) Add SMI# /IRQ for Voltage/Fan description. Register Index 1Ah~1Fh revised. This update is for C version IC. 1) Add EVNTRAP1-5 polarity (Index Ah ) 2) Add VID protection control bit (Index15h bit5) 3) Add FAN1-3/PWMOUT1-3 as GPIn data register. (Index 95h/97h) 4) SMARTFANTM step up/down time registers exchanged. 5) Add a bit (Index A6 bit7) to know either speech or GPIO function did you use. 6) Pin44 (SMI#/LEDOUT) is a multi-function, it is programmable. 7) EVENTRAP can as GPIO by programming Index A6h bit0-4 . 8) Updated V0.17 schematics adding LEDOUT circuit for SMI# (Pin 44) Repaginate datasheet Change all version include version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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W83791D
TABLE OF CONTENTS
1. 2. 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3. 4. 5. 6. 6.1 6.2 6.3 GENERAL DESCRIPTION ................................................................................................ 1 FEATURES ...................................................................................................................... 3 Monitoring Items ....................................................................................................................................................... 3 Address Resolution Protocol (ARP) and Alert-Standard Forum(ASF) ........................................................... 3 Speech Items ............................................................................................................................................................... 3 Actions Enabling ....................................................................................................................................................... 3 Enhance Monitoring VID function......................................................................................................................... 4 General ........................................................................................................................................................................ 4 Package........................................................................................................................................................................ 4 KEY SPECIFICATIONS ..................................................................................................... 4 PIN CONFIGURATION...................................................................................................... 5 PIN DESCRIPTION ........................................................................................................... 6 FUNCTION DESCRIPTION ............................................................................................. 10 General Description ................................................................................................................................................ 10 Access Interface....................................................................................................................................................... 10 6.2.1 The first serial bus access timing ..........................................................................10 Speech Function....................................................................................................................................................... 11 6.3.1 General Description..............................................................................................11 6.3.2 Event Trigger Queue ............................................................................................11 6.3.3 Connection of EEPROM .......................................................................................13 6.3.4 Speaker Output ....................................................................................................13 Address Resolution Protocol (ARP) Introduction ............................................................................................. 14 ASF(Alert Standard Format) Introduction.......................................................................................................... 16 6.5.1 Platform Event Trap (PET) ....................................................................................16 Analog Inputs ........................................................................................................................................................... 19 6.6.1 Monitor over 4.096V voltage: .................................................................................19 6.6.2 Monitor negative voltage: ......................................................................................20 FAN Speed Count and FAN Speed Control ....................................................................................................... 21 6.7.1 Fan speed count...................................................................................................21 6.7.2 Fan speed control.................................................................................................22 6.7.3 Smart Fan Control ................................................................................................23 Temperature Measurement Machine.................................................................................................................... 25 6.8.1 Monitor temperature from thermistor: .....................................................................25 TM 6.8.2 Monitor temperature from Pentium II thermal diode or bipolar transistor 2N3904 ...25 6.8.3 SMI# interrupt for W83791D Voltage......................................................................26 6.8.4 SMI# interrupt for W83791D Fan ...........................................................................26 6.8.5 SMI# interrupt for W83791D temperature sensor 1/2/3... ... ... ... ... ... ... ... ... ... .27 6.8.6 Over-Temperature (OVT#) for W83791D temperature sensor 1/2/3 .........................28 ii Publication Release Date: Aug, 2001 Revision 1.0
6.4 6.5 6.6
6.7
6.8
W83791D
9 9.1 9.2 9.3 10 11
ELECTRICAL CHARACTERISTICS ................................................................................ 30 Absolute Maximum Ratings.................................................................................................................................. 30 DC Characteristics................................................................................................................................................... 30 AC Characteristics................................................................................................................................................... 32 9.3.1 Serial Bus Timing Diagram....................................................................................32 HOW TO READ THE TOP MARKING .............................................................................. 33 PACKAGE SPECIFICATION ........................................................................................... 34
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1. GENERAL DESCRIPTION
W83791D is an evolving version of the W83782D --- Winbond's most popular hardware status monitoring IC. Besides the conventional functions of W83782D, W83791D uniquely provides several innovative features such as speech function, ASF sensor compliant, SMBus 2.0 ARP command compatible, VID table selection trapping, and 5VID output control. Conventionally, W83791D can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and efficiently. As for data access, W83791D provides slave SMBus 2.0 interface which can reply PEC (Packet Error Code) when as ASF sensor. An 8-bit analog-to-digital converter (ADC) was built inside W83791D. W83791D can simultaneously monitor 10 analog voltage inputs (including power VDD/5VSB monitoring), 5 fan tachometer inputs, 3 remote temperatures, and one case open detection signal. The sense of remote temperature can be performed by thermistors, 2N3904 NPN-type transistors, or directly from IntelTM CPU with thermal diode output. W83791D provides 3 PWM (pulse width modulation) outputs for two modes of smart fan control-} Thermal CruiseTM ~ mode and }Speed Cruise} mode. Under } Thermal CruiseTM ~ mode, temperatures of CPU and the system can be maintained within specific programmable ranges under the hardware control. }Speed Cruise}, namely, is to keep the fan operate in the specific programmable r.p.m . As for warning mechanism, W83791D provides speech voice warning, beep tone warning, and SMI#, OVT#, IRQ signals for system protection events.
TM Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. Pentium II/III) if applicable. These VID inputs provide the information of Vcore voltage that CPU expects. Furthermore, W83791D provides programmable VID output control to alter the voltage CPU consumes. W83791D also uniquely provides an optional feature: early stage (before BIOS was loaded) beep / speech warning to detect if the fatal elements present --- Vcore or +3.3V voltage fail and thus the system can not be boomed up. If the VSB power on setting refers to Intel VRM 9.x, the VID table within W83791D will be according to the new one. W83791D also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2 CTM interface.
W83791D speech function is enabled by building in a programmable speech synthesizer with a 9-bit current DAC output as well as a connectable external flash memory for storing voice data. W83791D supports 1 CPU present or absent event trap, 5 external event traps, 17 hardware monitor event traps (10 analog voltage, 3 fan tachometer, 3 remote temperature, 1 case open) and 128 internal programmable event traps, amounting to 151 different speech outputs. If more than two events happen simultaneously, the priority set is: SLOTOCC# > EVNTRP1 > EVNTRP2 > EVNTRP3 > EVNTRP4 > EVNTRP5 > 128 Programmable events (Bank0 index 09h) > 17 Hardware status events. Voice data stored in the external flash memory interface with Winbond W55FXX is flexible to change by Winbond application software and on-line programming flash data is provided also. Besides, An external resistor is added to provide ring oscillator. When you do not use the speech function, W83791D provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a pre-defined alternate function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. W83791D can uniquely serve as an ASF sensor to respond to ASF master's request for the implementation of network management in OS-absent state. Through W83791D's compliance with ASF sensor spec , network server is able to monitor the environmental status of the client in OS-absent state by PET frame values returned from W83791D, such as temp eratures, voltages, fan speed, and case open. Moreover, W83791D supports SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new unique address to W83791D after W83791D's UDID is sent. 1 Publication Release Date: Aug, 2001 Revision 1.0
W83791D
Through the application software or BIOS, the users can read all the monitored parameters of the system from time to time. A pop-up warning can also be activated when the monitored item is out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, IntelTM LDCM (LanDesk Client Management), or other management application software. Besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate one programmable and maskable interrupts. An optional beep tone could be used as a warning signal when the monitored parameters are out of the preset range.
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2.
* * * * * * * * * * * * * * * * * * * * *
FEATURES
10 voltage inputs --- Typical for VCORE, +3.3V, +12V, -12V, +5V, -5V, +5VSB, VBAT, and two reserved 5 fan speed monitoring inputs 3 temperature inputs from remote thermistors, 2N3904 NPN-type transistors or PentiumTM II thermal diode output Case open detection input WATCHDOG comparison of all monitored values Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.1 Monitoring Items
(Deschutes)
2.2 Address Resolution Protocol (ARP) and Alert-Standard Forum(ASF)
Support System Management Bus (SMBus) version 2.0 specification Comply with hardware sensor slave ARP (Address Resolution Protocol) Response sensor type A RP command Response ASF command --- Get Event Data , Get Event Status Comply with ASF sensors (Monitoring fan speed, voltage, temperature, and case open)
2.3 Speech Items
Programmable speech synthesizer with new high fidelity synthesis algorithm Build in 8-bit current D/A converter 1 CPU present or absent trigger input 5 External trigger inputs 128 Internal programmable trigger inputs 17 H/W Monitor event trigger inputs Programmable 0-255 seconds timeout trigger inputs for firmware or software Instruction cycle is <= 400 uS typically Section control provided in each voice section External resistor for ring oscillator
2.4 Actions Enabling
* * * * Beep tone warning separated speech output 5 PWM (pulse width modulation) outputs for fan speed control (1~3 support Smart Fan control) and 5 Fan speed inputs for monitoring --- Total up to 5 sets of fan speed monitoring and controlling Issue SMI#, OVT#, IRQ signals to activate system protection Warning signal pop-up in application software
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2.5 Enhance Monitoring VID function
* * * CPU Voltage ID reading VID output control Enhance beep warning by detecting Intel VRM 9.0 VID
2.6 General
* * * * I2 CTM serial bus interface 5 VID input pins for CPU VCORE identification (for PentiumTM II/III) Initial power fault beep (for +3.3V, VCORE)
2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2 CTM interface Winbond hardware monitoring application software (Hardware DoctorTM ) support, for both Windows 95/98/2000 and Windows NT 4.0/5.0 * Internal clock Oscillator with 3M Hz * * 5V VSB operation
2.7 Package
48-pin LQFP
3.
* * * * * *
KEY SPECIFICATIONS
Voltage monitoring accuracy Intel VRM 9.x Voltage monitoring accuracy Monitoring Temperature Range and Accuracy - 40C to +120C Supply Voltage Operating Supply Current ADC Resolution 1% (Max) 0.5% (Max) 3C(Max) 5V 5 mA typ. 8 Bits
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4.
PIN CONFIGURATION
V V+ C I 3.3 O NV RRI E0N V I N R 1 + 12 V I N 12 V I N + 5 V S B 5 V I N
V B A T
G N D A
B E E P
V I D 3
36
35
34
33
32 31 30
29
28
27
26
25 24 23 22 21 20
VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# IRQ/GPIO10 SMI#/LED EVNTRP1/GPIO5 EVNTRP2/GPIO6/FANIN4 EVNTRP3/GPIO7/FANIN5 EVNTRP4/GPIO8/PWMOUT4
37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11
W83791D
19 18 17 16 15 14 13 12
VIDIN2 PWMTOUT3/VID_V90 SD A SC L FANIN1 FANIN2 FANIN3 VID4 CASEOPEN SLOTOCC# GNDD VDD
E ERACD V OEDL A NPXDKT T T ROA R / U/ P GTG 5 P/ P / I GI G OPO P 0I2 I O O 1 9 / P W M O U T 5
C T R L / G P I O 3
M O D E / G P I O 4
S P E A K E R / L E D / S P E E C H _ S E L
P W M O U T 1 / A 0
PV WI MD O1 U T 2 / A 1
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5.
PIN DESCRIPTION
- TTL level bi-directional pin with 12 mA source-sink capability - TTL level and schmitt trigger with 12 mA source-sink capability - TTL level and schmitt trigger with 8 mA source-sink capability - TTL level and schmitt trigger with 6 mA source-sink capability - TTL level and schmitt trigger open drain output with 12 mA sink capability - Output pin with 12 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Output pin(Analog) - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog)
I/O12t I/O12ts I/O8ts I/O6ts I/OD12ts OUT12 OD12 AOUT INt INts AIN
Pin Name EVNTRP5 / GPIO9/ PWMOUT5
Pin No. 1
Type I/ O 1 2 t
Description Event trapping to selection speech output sound. Default is high edge trigger. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or PWMOUT Fan control can be selected by registers, but the PWMOUT can not support Smart Fan.
EOP GPIO11 REXT ADDR /
2
I I/OD12ts
End of Process signal input from cascaded Flash. General purpose I/O function pin. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Resistor(Rosc) connect to VSB used to adjust ring oscillator frequency. Speech address pulse output, connect to W55FXX. When this pin translates from logic high to logic low, it will latch the data pin 6 and shift it into a speech flash address counter. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Speech clock output, for speech data read-out and write-in, connect to W55FXX. When this pin translates from logic high to logic low, the data pin 6 will be latched by this clock. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Serial data input/output, connect to W55FXX. The pin is latched by CLKOUT and ADDR acted as speech data and address respectively. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Output clock numbers of this pin decide which mode is selected. Connect to W55FXX. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Output mode signal to W55FXX serial Flash. 6 Publication Release Date: Aug, 2001 Revision 1.0
3 4
I OUT12
GPIO0 CLKOUT / 5
I/OD12ts OUT12
GPIO1 DATA / GPIO2 CTRL / GPIO3 MODE / 8 7 6
I/OD12ts I/O12t I/OD12ts OUT12 I/OD12ts OUT12
W83791D
GPIO4 SPEAKER LED 9
I/OD12ts OUT12 OUT12
General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. Current type output driving an external speaker. The function is only working in VDD 5V OK. LED output control. This is a multi-function pin with SPEA KER. When the LED_SEL register (Bank0 Index 17h) is set to 1, LED output function will be active. Otherwise, set to 0 (default), this pin serves as SPEAKER output. During VSB 5V power on, this pin is used to trap whether using speech function or GPIO function. Trapping low means using speech function (i.e. pin45-48, pin1, pin4-8 are as speech function). Trapping high means using GPIO function (i.e. pin45-48, pin1, pin4-8 are as GPIO function). The I/O control and status is defined in BANK0 Index 13h~16h. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2 C device address bit0 trapping during 5VSB power on. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2 C device address bit1 trapping during 5VSB power on. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. +5V VDD power. Bypass with the parallel combination of 10F (electrolytic or tantalum) and 0.1F (ceramic) bypass capacitors. Internally connected to all digital circuitry. CPU presence signal. 0, means CPU is present. 1, means CPU is absent. CASE OPEN detection. An active high input from an external device when case is Intruded. This signal can be latched in external circuit which power is supplied by VBAT, even if W83791D is power off. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. 0V to +5V amplitude fan tachometer input Serial Bus Clock. Serial Bus bi-directional Data. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. VID table selection trapping during RSMRST (0: Intel VRM 8.2/8.3; 1: Intel VRM 9.0). When the trapping pin get a logic 1, the beep warning function is according to Intel VRM 9.0 VID. Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU.
SPEECH_SEL
INts
PWMOUT1/ A0 PWMOUT2 / A1 VID1 VDD (5V) GNDD SLOTOCC# CASEOPEN
10
OUT12 INts
11
OUT12 INts
12 13 14 15 16
I/ O 1 2 t s POWER DGROUND INts I/O6ts
VID4 FAN3INFAN1IN SCL SDA PWMOUT3 / VID_V90
17 18-20 21 22 23
I/ O 1 2 t s INts INts I/OD8ts OUT12 INts
VID2
24
I/ O 1 2 t s
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VID3 BEEP GNDA -5VIN +5VSB VBAT -12VIN +12VIN VINR1 +3.3VIN VINR0 VCORE VREF VTIN3 / PIITD3 VTIN2 / PIITD2 VTIN1 / PIITD1 VID0 OVT# IRQ / GPIO10 SMI# / LED
25 26 27 28 29 30 31 32 33 34 35 36 37 38
I/ O 1 2 t s OD12 AGROUND AIN POWER POWER AIN AIN AIN AIN AIN AIN AOUT AIN
Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. Alarm beep output. Normal, this pin is low. When abnormal event happens, this pin will output alarm frequency. Internally connected to all analog circuitry. The ground reference for all analog inputs. 0V to 4.096V FSR Analog Inputs. This pin is power for W83791D. Bypass with the parallel combination of 10F (electrolytic or tantalum) and 0.1F (ceramic) bypass capacitors. This pin is power for W83791D. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. 0V to 4.096V FSR Analog Inputs. Reference voltage. Thermistor 3 terminal input.(Default). PentiumTM II diode 3 input. This multi-functional pin is programmable.
39
AIN
Thermistor 2 terminal input. (Default). PentiumTM II diode 2 input. This multi-functional pin is programmable.
40
AIN
Thermistor 1 terminal input. (Default). PentiumTM II diode 1 input. This multi-functional pin is programmable.
41 42 43
I/ O 1 2 t s OD12 OUT12 I/OD12ts
Voltage Supply readouts from CPU. After programming, this pin can be VID output to voltage regulator to generate Vcore for CPU. Over temperature Shutdown Output for temperature sensor 1-3. Interrupt request. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. System Management Interrupt (open drain). LED output control. This is a multi-function pin with SMI. When the register (Bank0 Index 17h bit7 and Index A6h bit 6) is set to 1, LED output function will be active. Otherwise, set to 0 (default), this pin serves as SMI#. Event trapping to selection speech output sound. Default is high edge trigger. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this speech function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or FAN inputs can be selected by registers. 8 Publication Release Date: Aug, 2001 Revision 1.0
44
OD12 OUT12
EVNTRP2-3/ GPIO6-7/ FANIN4-5
46-47
I/O12ts I/O12ts
W83791D
EVNTRP4/ GPIO8/ PWMOUT4
48
I/O12ts I/O12ts
Event trapping to selection speech output sound. General purpose I/O function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. The I/O control and status is defined in BANK0 Index 13h~14h. Otherwise, GPIO pin or PWMOUT Fan control can be selected by registers, but the PWMOUT can not support Smart Fan.
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6.
FUNCTION DESCRIPTION
6.1 General Description
The W83791D provides 10 analog positive inputs, 5 fan speed inputs , at most 5 sets for fan PWM (Pulse Width Modulation) control, 3 thermal inputs from remote thermistors , 2N3904 transistors or PentiumTM II/III (Deschutes) thermal diode outputs, case open detection and beep function output when the monitored values exceed preset ranges , including the voltage, temperature, and fan count. Moreover, W83791D uniquely provides several innovative and practical functions to make the whole system more efficient and compliant with future trend of network management, such as speech function, ASF sensor compliant, SMBus 2.0 ARP command compatible, VID table selection trapping, 5VID output control, and so forth. Once the monitoring function ofW83791D is enabled, the watch dog machine will monitor every function and store the values to registers for comparison with preset ranges. If the monitoring value exceeds the limit value, the interrupt status will be set to 1 and W83791D will issue interrupt signals such as SMI# and IRQ if not masked..
6.2 Access Interface
The W83791D provides I2 C Serial Bus for microprocessor to read/write internal registers. In the W83791D, there are three serial bus addresses. Through the first address defined at CR[48h], all the registers can be read and written except CPUT1/CPUT2 temperature sensor registers. The read/write of the CPUT1/CPUT2 temperature sensor registers can be implemented through the second address (defined at CR[4Ah] bit2-0) and the third address (defined at CR[4Ah] bit6-4). The first serial bus address of W83791D has 2 hardware setting bits set by pin10-11. The address is 001011[pin11][pin10]. Hence, the content of CR[48h] would be 00101110 if pin11=1 and pin10=0 . 6.2.1 The first serial bus access timing (a) Serial bus write to internal address register followed by the data byte
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 791D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
8
Ack by 791D 784R
Stop by Master
Frame 3 Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
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(b) Serial bus read from a register
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 791D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
0
7
8
0
7
8
0
Repeat start by Master
1
0
1
1
0
1
R/W
Ack by 791D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 3 Serial Bus Address Byte 0
Frame 4 Data Byte
Figure 2. Serial Bus Read from Internal Address Register
6.3 Speech Function
General Description The W83791D is a derivative of Winbond's PowerSpeechTM synthesizers. There are up to 5 hardware trigger inputs, 17 Hardware Monitor event and 128 programmable software event trigger inputs. If more than two events happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 > EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG(Index 09h) 128 events > VIN0 > VIN1> others (VIN2 - VIN9,TEMP, FAN, case open). Software trigger is able to accommodate 128 event triggers, with timeout register (index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system's power is on, BIOS can fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to prevent events from taking place simultaneously. 6.3.2 Event Trigger Queue W83791D provides 8 byte FIFO queue to store event trigger, i.e, the first 8 event can be served by speech and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791D detects no CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of the 8-Byte event trigger queue.
Enable Timeout CLK 1 HZ
(Index 0Ah, b6)
6.3.1
8-bit Counter Timeout Comparator Trigger Timeout Register
(Index 08h)
TRIG_REG Event Trigger Data
(Index 09h, b6~0)
8-Byte Event Trigger Queue
Figure 3. Event trigger Queue
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For example: As BIOS usually has POST (Power On Self Test) program, then it will test every item step by step if no failure takes place, however, if it detects a failure on a specific item, it will hang on there. Therefore, BIOS could write timeout value to register 08h and start timer setup speech trigger event (register 09h), then is BIOS test program started. Whenever the system is hang on specific item such as DRAM testing, W83791D would say "DRAM test fails" after the timeout previously set at CR[08h]. On the contrary, if DRAM test is ok, then BIOS could update the timeout value and proceed to the next test program. Below is the speech CPU_MODE table of W83791D: CPU_MODE item POI SLOTOCC EVNTRAP1(TG1) EVNTRAP2 EVNTRAP3 EVNTRAP4 EVNTRAP5 TRIGREG IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 TEMP1 TEMP2 TEMP3 FAN1 FAN2 FAN3 CHS_EV Table 1. CPU_MODE Table Definition Reserverd CPU present or absent Hardware trgger1 Hardware trgger2 Hardware trgger3 Hardware trgger4 Hardware trgger5 I2C setting software trigger Vcore(VIN0 ) exceed limit VINR0(VIN1) exceed limit (+3.3VIN)VIN2 exceed limit (5VDD)VIN3 exceed limit (+12VIN)VIN4 exceed limit (-12VIN)VIN5 exceed limit (-5VIN)VIN6 exceed limit VSB(VIN7) exceed limit VBAT(VIN8 ) exceed limit (VINR1)VIN9 exceed limit VTIN1 exceed limit VTIN2 exceed limit VTIN3 exceed limit FAN1 count over limit FAN2 count over limit FAN3 count over limit Case open trigger Vector (H) 0,32 1 2 3 4 5 6 80-FF 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
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6.3.3 Connection of EEPROM As is described previously that the W83791D has connectable W55FXX to store voice data. To expand the storage capacity, users can select many W55FXX to connect with each other. The maximum capacity could be up to 16Mbit. Following is the connection chart of W55FX with W83791D.
EEPROM
DATA ADDR CLK CTRL MODE EOP
EEPROM
DATA ADDR CLK CTRL MODE EOP
SLOTOCC# EVTTRAP 1: 5
DATA ADDR CLK CTRL MODE EOP
Speech Synthesizer (W83791D)
9-bit DAC
SPK/LED
Internal programmable Hardware monitor status trigger trigger
Figure 4. Speech Function Diagram
6.3.4
Speaker Output Speech output pin is a 8 bit Current D/A converter, with which loading is needed. The resistor could range from 510~1K ohm and bipolar could be a low power NPN bipolar with of 120 - 160 . Usually, an 8050D transistor is appropriate. The spec of speaker is 8 . Besides, SPK can also connect to AC97 codec chip Line_Out. C is decouple capacitor and is usually 200p- 0.01uF
8 ohm speaker SPK R C 8050D, NPN transistor
Figure. 5
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6.4
Address Resolution Protocol (ARP) Introduction
As the W8791D is a slave device existing on the System Management Bus, it m have a unique address to ust prevent itself from conflicting with the other devices existing on the same bus. In order to solve the problem of address conflicts, SMBus version 2.0 introduces the concept of dynamically assigned address called Address Resolution Protocol (ARP). By such mechanism, each device existing on the SMBus will be given an unique slave address if it is a ARP-capable device. Thus, to meet the new spec, W83791D uniquely provides ARP compliant function to acquire an unique slave address. The typical process of ARP contains several steps, including Prepare to ARP, Reset Device, Get UDID, Assign Address, and so on. Whenever the slave device accepts the command of ARP master, it must reply an Acknowledgement to the ARP master, thus the ARP master is able to carry on the next step. In order to provide a mechanism to isolate device for the purpose of address assignment, each device must implement a unique device identifier (UDID). The UDID is a 128-bit number comprised of several field, including Device Capabilities, Version Revision, Vendor ID, Device ID, Interface, Subsystem Vendor ID, Subsystem Device ID, and Vendor Specific ID. After the UDID of the device is sent to the ARP master, the ARP master will then assign a random address not in the Used Address Pool to the device Generally speaking, there are eleven possible commands to read /write the data of SMBus device, and a slave device may use any or all of the eleven protocols to communicate. These protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read word, Process Call, Block Write, and Block Write-Block Read Process Call. W83791D itself supports the Block Write-Block Read Process with PEC to communicate with ARP Master. Following is a description of the SMBus packet protocol diagrams element key.. Not all protocol elements will be present in every command, that is, not all packets are required to include the Packet Error Code. 1-bit S 7 Slave Address S Sr Rd Wr A 1 1 Wr A 8 Command 1 A 8 PEC 1 A 1-bit P
Start Condition Repeated Start Condition Read (bit value of 1) Write (bit value of 0) Acknowledge (this bit position may be `0' for an ACK or `1' for a NACK)
P PEC
Stop Condition Packet Error Code Master-to-Slave Slave-to-Master
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Relative command list: Slave address C2h C2h C2h C2h C2h C2h C2h Command 01h 02h 03h 04h Slave_Addr | 1 Slave_Addr | 0 05h-1Fh Description Prepare to ARP Reset device (general) Get UDID (general) Assign address Direct Get UDID Direct Reset Reserved.
Following is an example of the Block Write-Block Read Process Call. The Block Write-Block Read Process Call is a two-part message. It begins with a salve address and a write condition. After the command code the host issues a write count M that describes how many more bytes will be written in the first part of the message. The second part of the message is a block of read data beginning with a repeated start condition followed by thee salve address and a Read Bit. The next read byte count N indicates how many more data will be read in the second part of the message. Note that the combined data payload must not exceed 32bytes. Besides, W83791D also provides packet error code (PEC) to insure the accuracy during data transmission. 1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 8 Byte Count=M 1 A 8 Data Byte 1 1 A ...
8 Data Byte 2 1 Sr 7 Slave Address 8 Data Byte 2 1 Rd 1 A
1 A 1 A ... ...
... ...
8 Data Byte M 1 A 1 A
1 A
... 1 A 1 ...
8 Byte Count=N 8 Data Byte N
8 Data Byte 1 8 PEC 1 A 1 P
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6.5
ASF(Alert Standard Format) Introduction
In order to implement network management in OS-absent, W83791D provides ASF Response Registers to meet ASF sensor spec. As a result, the network server is able to monitor several environmental status of the client in OS-absent by PET frame values returned from W83791D, including temperature, voltage, fan speed, and case open. In below is the ASF diagram:
Alert Message LAN on Card
Management Server
Polling P C I B us LAN on Board SMBus Chi pset
(PET Subset) Mot herboard
791D Slave
Figure 6. ASF Block Diagram
6.5.1
Platform Event Trap (PET)
PET is the ASF transmit protocol used to provide common fields for trap regardless of trap source. The variable bindings fields in a PET frame contain the system and sensor information for an event, such as event sensor type, event type, event offset, event source type, sensor device, sensor number, entity ID, entity instance, event status index, event status, and event severity. Each field has its definition and is described in the following table.
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PET Variable Binding Field Event Sensor Type
Event Type Event Offset Event source Type
Sensor Device Sensor Number Entity ID Entity Instance Event Status Index
Description The Event Sensor Type field indicates what types of events the sensor is monitoring. E.g. temperature, voltage, fan, etc. The Event Type indicates what type of transition/state change triggered the trap. The Event Offset indicates which particular event occurred for a given Even Type. The Event Source Type describes the originator of the event. It is ASF1.0(68h) for all PET frames defined by this specification. The Sensor Device is the SMBus address of the sensor that caused the event for the PET frame. The Sensor Number is used to identify a given instance of a sensor relative to the Sensor Device. The Entity ID indicates the platform entity the event is associated with. E.g. processor, system board, etc. The Entity Instance indicates which instance of the Entity the event is for. E.g. processor 1 or processor 2. The Event Status Index identifies a unique event monitored by the ASF-sensor. It is zero-based, sequential, continuous, and ranging form 0-37h. The Event Status indicates the event state of the ASFsensor device associated with the message's Event Status Index. The Event Severity gives the management station an indication of the severity of the event in the PET frame. Typical values are Monitor (0x01), Non Critical (0x08), or Critical Condition (0x10).
Event Status
Event Severity
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Following is the illustration of ASF SMBus command for Get Event Data. 1 S 7 Slave Address ASF-sensor Address 1 A 0 1 Wr 0 1 A 0 8 Command Sensor Device 0000 0001 1 A 0 8 Wr Byte Count 0000 0100 1 A 0
...
8 Wr Data 1 Sub Command Get Event Data 0001 0001 1 Sr
8 1 Wr Data 2 A Version 0 Number 0001 0000 1 R 1
8 1 Wr Data 3 A Event Status Index 0 00ii iiii
8 Wr Data 4 Reserved 0000 0000
1 A 0
...
7 Slave Address ASF-sensor Address
1 A 0
8 Rd Byte Count 0000 1010 to 0000 1111 1 A 0 1 A 0 8 Rd Data 3 Event Type 8 Rd Data 7 Sensor Device
1 A 0
...
1 A 0
8 Rd Data 1 Status 1 A 0
1 A 0
8 Rd Data 2 Event Sensor Type 8 Rd Data 6 Event Severity
1 A 0 1 A 0
...
8 Rd Data 4 Event Offset
8 1 Rd Data 5 A Event Source 0 Type 1 A 0
...
8 Rd Data 8 Sensor Number
8 Rd Data 9 Entity
1 A 0
8 Rd Data 10 Entity Instance
1 A 0
...
... From zero to five bytes of Event Data
8 PEC [data dependent]
1 A 1
1 P
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6.6
Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Actually, the application of the PC monitoring would mo st often be connected to power supply. The CPU V-core voltage,+3.3V and battery voltage can directly connect to these analog inputs. The -5V, - 12V and +12V inputs should be reduced a factor with external resistors to meet the input range. As Figure 7 shows.
+1.8Vcore +1.5VINR0 Positive Inputs +3.3VIN VINR1 VBAT R1 V1 R2 12VIN 5VSB Positive Inpu t
Pin 36 Pin 35 Pin 34 Pin 33 Pin 30 Pin 32 Pin 29 8-bit ADC with 16mV LSB
R5 V3 Negative Input V4 R7
N12VIN N5VIN
Pin 31 Pin 28
R8 R 10K, 1%
R6
VREF VTIN3 Pin 38 Pin 39 Pin 40
Pin 37
Typical Thermister Connection R THM 10K, 25 C
VTIN2 VTIN1
**The Connections of VTIN1 and VTIN2 are same as VTIN3
Figure 7.
6.6.1 Monitor over 4.096V voltage: The input voltage +12VIN can be expressed as the following equation.
12VIN = V1 x
R2 R1 + R2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN should be subject to under 4.096V for the maximum input range of the 8-bit ADC. The pin 13 and pin 29 are discretely connected to the power supply +5V and 5VSB . There are two functions in these pins with 5V. The first function is to supply internal analog power in the W83791D and the second one is that these voltages are all connected to internal serial resistors to monitor the +5V and 5VSB voltage.
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6.6.2 Monitor negative voltage: The negative voltage should be connected to two series resistors and a positive voltage VREF (equal to 3.6V). In the Figure 11, the voltage V3 and V4 are two negative voltages and are -12V and -5V respectively. The voltage V3 is connected to two serial resistors as well as another positive terminal VREF. Therefore, the voltage node N12VIN would be a positive voltage if the scale of the two serial resistors are carefully selected. It is recommended from Winbond that the scale of the two serial resistors are R5=232K ohms and R6=56K ohm. The input voltage of node -12VIN can be calculated by the following equation.
N12VIN = (VREF + V5 ) x (
where VREF is equal to 3.6V.
232 K ) + V5 232 K + 56K
If the V5 is equal to -12V then the voltage is equal to 0.567V and the converted hexdecimal data is set to 35h by the 8-bit ADC with 16mV-LSB.This monitored value should be converted to the real negative voltage and the express equation is shown as follows.
V5 =
Where
is 232K/(232K+56K). If the N2VIN is 0.567 then the V5 is approximately equal to -12V.
N12VIN - VREF x 1-
The other negative voltage input V6 (approximate -5V) can also be evaluated by the similar method and the serial resistors can be R7=120K ohms and R8=56K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows.
V6 =
N 5VIN - VREF x 1 -
Where the is set to 120K/(120K+56K). If the monitored ADC value in the N5VIN channel is 0.8635, VREF=3.6V and the parameter is 0.6818, then the negative voltage of V6 can be evaluated -5V.
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6.7
FAN Speed Count and FAN Speed Control
6.7.1 Fan speed count W83791D support 5 sets of fan counting. Fan inputs are provided for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and the maximum input voltage should not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to meet the input specification. The normal circuit and trimming circuits are shown as Figure 8. Determine the fan counter according to:
1.35 x 10 6 Count = RPM x Divisor
In other words, if the fan speed counter has been read from register CR[28] or CR[29] or CR[2A] or CR[BA] or CR[BB] , then the fan speed can be evaluated by the following equation.
RPM =
1.35 x 10 6 Count x Divisor
The default divisor is 2 and defined at CR47.bit7~4, CR4B.bit7~6, and Bank0 CR5D.bit5~7 which are three bits for divisor. This provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count.
Divisor 1 2 (default) 4 8 16 32 64 128
Nominal RPM 8800 4400 2200 1100 550 275 137 68
Time per Counts Revolution 6.82 ms 153 13.64 ms 153 27.27 ms 153 54.54 ms 153 109.08 ms 153 218.16 ms 153 436.32 ms 153 872.64 ms 153 Table 2.
70% RPM 6160 3080 1540 770 385 192 96 48
Time for 70% 9.74 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms
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+12V
+5V
+12V
Pull-up resister 4.7K Ohms
Pull-up resister 4.7K Ohms
+12V FAN Out GND Fan Input Pin 18/19/20
+12V 14K~39K FAN Out GND Fan Input Pin 18/19/20
FAN Connector
W83791D
FAN Connector
10K
W83791D
Figure 8-1. Fan with Tach Pull-Up to +5V
Figure 8-2. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 18/19/20 3.9V Zener +12V
Pull-up resister < 1K or totem-pole output
> 1K FAN Out GND 3.9V Zener Fan Input Pin 18/19/20
FAN Connector
W83791D
FAN Connector Figure 8-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp
W83791D
Figure 8-3. Fan with Tach Pull-Up to +12V and Zener Clamp
6.7.2 Fan speed control The W83791D provides five sets of PWM for fan speed control. The duty cycle of PWM can be programmed by a 8-bit registers defined in the Bank0 CR[81], CR[83], CR[94], CR[9E] and CR[9F] . The default duty cycle is set to 100%, that is, the default 8-bit register is set to 0xFFh. The expression of duty cycle can be represented as follows.
Duty - cycle (%) =
Programmed 8 - bit Register Value x 100% 255
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+12V
R1 R2 D G PWM Clock Input NMOS S + C FAN PNP Transistor
Figure 9.
6.7.3 Smart Fan Control W83791D supports three Smart Fan function and mapping to temp1 (FAN1, PWMOUT1), temp2 (FAN2, PWMOUT2) , temp3( FAN3, PWMOUT3) .Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. 6.7.3.1 Thermal Cruise mode At this mode, W83791D provides the Smart Fan system to automatically control fan speed to keep the temperatures of CPU and the system within specific range. At first a wanted temperature and interval must be set (ex. 55 C 3 C) by BIOS and the fan speed will be lowered as long as the current temperature remains below the setting value. Once the temperature exceeds the high limit ( 58C), the fan will be turned on with a specific speed set by BIOS (ex: 80% duty cycle) and automatically controlled its PWM duty cycle with the temperature varying. Three conditions may occur : (1) If the temperature still exceeds the high limit (ex: 58C), PWM duty cycle will increase slowly. If the fan has been operating in its full speed but the temperature still exceeds the high limit (ex: 58C), a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58C), but still above the low limit (ex: 52C), the fan speed will be fixed at the current speed because the temperature is in the target range (ex: 52 C ~ 58C). (3) If the temperature goes below the low limit (ex: 52C), PWM duty cycle will decrease slowly to 0 or a preset stop value until the temp erature exceeds the low limit. Figure 10-1, 10-2 gives an illustration of Thermal Cruise Mode.
A 58C 55C 52C 100 50 0
B
C
D
PWM Duty Cycle
Fan Start = 20%
Figure 10-1.
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A 58C 55C 52C
B
C
D
PWM 100 Duty 50 Cycle 0
Fan Start = 20% Fan Start = 20% Fan Stop = 10%
Figure 10-2.
Fan Speed Cruise mode At this mode, W83791D provides the Smart Fan system to automatically control the fan speed within a specific range. In the beginning, a wanted fan speed count and interval must be set (ex. 160 10 ) by BIOS. As long as the fan speed count remains in the specific range, PWM duty cycle will keep the current value. If current fan speed count is higher than the high limit (ex. 160+10), PWM duty cycle will be increased to make the count under the high limit. On the other hand, if current fan speed count is less than the low limit(ex. 160-10), PWM duty cycle will be decreased to make the count higher than the low limit. See Figure 10-3 example.
6.7.3.2
Count 170 160 150
A
C
PWM Duty Cycle
100 50 0
Figure 10-3. Of course, Smart Fan control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software.
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6.8
Temperature Measurement Machine
The temperature data format is 8-bit two-complement for sensor 1 and 9-bit two-complement for sensor 2/3. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the bank0 CR[C0/ C8h] and the LSB from the bank0 CR[C1/C9h] bit 7. The format of the temperature data is show in Table 3. Temperature +125 C +25 C +1 C +0.5 C +0 C -0.5 C -1 C -25 C -55 C 8-Bit Digital Output 8-Bit Binary 8-Bit Hex 0111,1101 7Dh 0001,1001 19h 0000,0001 01h 0000,0000 00h 1111,1111 FFh 1110,0111 E7h 1100,1001 C9h Table 3. 9-Bit Digital Output 9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010
9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h
6.8.1 Monitor temperature from thermistor: The W83791D can connect three thermistors to measure three different environmental temperatures. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 11, the themistor is connected by a serial resistor with 10K Ohms(1% error), then connect to VREF (Pin 37).
6.8.2 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 The W83791D can alternate the thermistor to Pentium II/III TM thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 11. The pin of Pentium II/IIITM D- is connected to power supply ground (GND) and the pin D+ is connected to pin PIITDx in the W83791D. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode.
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VREF R=30K, 1% Bipolar Transistor Temperature Sensor PIITDx C=3300pF B C 2N3904 E R=30K, 1%
W83791D
OR
Pentium II/III CPU
Therminal Diode
D+ PIITDx C=3300pF D-
Figure 11.
6.8.3
SMI# interrupt for W83791D Voltage
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 12-1.)
6.8.4
SMI# interrupt for W83791D Fan SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit (set at value ram index 3Bh and 3Ch) , will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 12-2.)
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High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-1. Voltage SMI# Mode
Figure 12-2. Fan SMI# Mode
6.8.5
SMI# interrupt for W83791D temperature sensor 1/2/3
(1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO but has not been reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. (Figure 12-3.) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the T HYST , the interrupt will not occur. (Figure 12-4.) (3) One-Time interrupt mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO , then going below THYST, an interrupt will not occur again until the temperature exceeding TO . (Figure 12-5.)
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T OI
T OI
T HYST
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-3. Comparator Interrupt Mode
Figure 12-4. Two-Times Interrupt Mode
T OI
T HYST
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 12-5. One-Time Interrupt Mode
Note. The IRQ interrupt action like SMI# , but the IRQ is level signal.
6.8.6
Over-Temperature (OVT#) for W83791D temperature sensor 1/2/3
(1) Comparator Mode: Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. (Figure 13) (2) Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST, the OVT# will not be activated again.( Figure 13)
(3) ACPI Mode 28 Publication Release Date: Aug, 2001 Revision 1.0
W83791D
At this mode, temperature exceeding one level of temperature separation, starting from 0 degree, causes the OVT# output activated. OVT# will be activated again once temperature exceeds the next level. OVT# output will act the same manner when temperature goes down. (Figure 13-1). The granularity of temperature separation between each OVT# output signal can be programmed at Bank0 CR[4Ch] bit 4-5.
To
THYST
OVT#
(Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature 1/2/3 is read
Figure 13 Over-Temperature Response Diagram
('C) 100 90 80 70 60 50 40 30 20 10 0 OVT#
Current Temperature
Figure 13 -1. ACPI Mode
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9
ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
RATING -0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150 UNIT V V C C
PARAMETER Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9.2
DC Characteristics
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V)
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/O12t - TTL level bi -directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A
IOL = 12 mA IOH = - 12 mA
VIN = VDD VIN = 0V
I/O12ts - TTL level bi -directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V
IOL = 12 mA IOH = - 12 mA
VIN = VDD VIN = 0V
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9.2 DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V
IOL = 12 mA IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V
IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V
IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = VDD VIN = 0 V VOL 0.4 V
IOL = 48 mA
- TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
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9.3
AC Characteristics
9.3.1 Serial Bus Timing Diagram
t SCL
t R
tR
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time SYMBOL t-SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF MIN. 10 4.7 4.7 120 5 1.0 300 MAX. UNIT uS uS uS nS nS uS nS
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10 HOW TO READ THE TOP MARKING The top marking of W83791D
W83791D 025AA
Left: Winbond logo 1st line: Type number W83791D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B
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11 PACKAGE SPECIFICATION
(48-pin LQFP)
H D
36
D
25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
Notes:
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
A2
A
Seating Plane
See Detail F
A1 y L L1 Detail F
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without n otice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owner
34
Publication Release Date: Aug, 2001 Revision 1.0
VOLTAGE SENSING
R1 CPUVCOA GTLVOLT 3VCC 10K +12VIN R4 +12V 28K 1% R6 +5V R 34K 1%/791D 0 /782D R8 5VSB R 5.1K 1%/782D 0 /791D R10 R R9 R7 R R5 10K 1% VINR1 GNDA R 50K 1%/791D +5VSB +5VSB GNDA R 7.5K 1%/782D R11 232K 1% +5V -12VIN R R 10K R2 10K R3 R R VINR0 3VIN R VCORE
/782D : Only for W83782D /791D : Only for W83791D
3VCC R30 R 4.7K 330 SMDAT SMCLK R33 R 330 R31 R 4.7K
SDA SCL GNDA
R R32
L1 INDUCTOR FB/791D C1 CAP 10u/791D GNDA C2 CAP 0.1u/791D
-12V
56K 1% VREF
L2 INDUCTOR FB/782D
GNDA
VBAT +5VSB
VINR1 +12VIN
R12
R
R13 120K 1%
R
-5V R14 ADRMSELIN R 0/782D R16 IRQ/GPIO10 R 0/791D VREF T3 T2 T1 37 38 39 40 41 42 43 44 45 46 47 48
3VIN
C3 CAP 10u/782D GNDA
C4 CAP 0.1u/782D
VCORE VINR0
-12VIN
BEEP VID3
-5VIN
56K 1%
3VSB 36 35 VINR0 34 +3.3VIN 33 VINR1 32 +12VIN 31 -12VIN 30 VBAT 29 +5VSB 28 -5VIN 27 GNDA 26 BEEP 25 VID3
-5VIN
U1
VCORE
R15 R 10K/791D R17 SLOTOCC# 24 23 22 21 20 19 18 17 16 15 14 13 VID2 OUT3/VID90 SDA SCL FAN1IN FAN2IN FAN3IN CASEOPEN GNDD VDD C5 CAP 10u VCC
R? SMI# R? LED
0 FAN4IN SMI#/LED 0/791D EVNT2/A1
R18
EVNTRAP5/GPIO9/PWMOUT5
0/791D R22 0/791D R23 FAN5IN 0/791D R24 EVNT3/A0 0/791D
(FAN)
VID0 OVT# SMI#/LED
MODE/GPIO4 SPEAKER/LED/SPEECH_SEL
(EVNT2)
EVNT1/A2
CLKOUT/GPIO1 DATA/GPIO2
PWMOUT1/A0
(FAN)
PWMOUT2/A1
ADDR/GPIO0
CTRL/GPIO3
EOP/GPIO11 REXT
VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# IRQ/GPIO10 SMI#/LEDOUT EVNTRAP1/GPIO5 EVNTRAP2/GPIO6/FANIN4 EVNTRAP3/GPIO7/FANIN5 EVNTRAP4/GPIO8/PWMOUT4
VID2 PWMOUT3/VID_V90 SDA SCL FANIN1 FANIN2 FANIN3 VID4 CASEOPEN SLOTOCC# GNDD VDD
R 0/791D R19 MR# R 0/782D
(From PII/PIII CPU)
0: means CPU is present 1: means CPU is absent
VID4
C6 CAP 0.1u
(EVNT3)
R25
9 10
11
GNDA
GNDA INDUCTOR FB
GNDD
EVNT4 PWMOUT4 0/791D (EVNT4) R26 R 0/791D(FAN) R28 R27 CS# 0/782D R 0/791D (EVNT5) R29 0/791D (FAN)
PWMOUT1/D1
PWMOUT2/D0 VID1
REXT/CLKIN
12
L3 1 2 3 4 5 6 7 8
VID1 W83791D
ADDR/D7 CKOUT/D6
EOP/IOW#
MODE/D3 SPK/D2
SMI#/LEDOUT function circuit
5VSB 3VCC R? 270 R20 R 4.7K TO CHIPSET R21 R 4.7K OVT# R129 0
Select one of the two setting. Set A2-A0 as 3 lowest order bits of ISA address bus
(FOR 782D)
Beep Circuits
VCC EVNT5/IOR# R R R EVNT1/A2 EVNT2/A1 EVNT3/A0 R38 R 100 LS1 LED BUZZER PWMOUT5 R34 5VSB 220K/ 791D R R? 1K D? LED 0 0 0
CTRL/D4
DATA/D5
ADRMSELIN SA2 SA1 SA0 R35 R36 R37
{
THRM#
EXTSMI#
SMI#
R39 R 10K
U7A R130 Q? MOSFET N 2N7000 0/791d,B 7404 /791d, B 2 1
R131 SMI# 0/791d,B
!!Only for 791D ver B.
Set A2-A0 as bit2, bit1, bit0 of 7 bit I2C address setting BEEP VCC IA2 IA1 IA0 ADRMSELIN
R40 R 510 Q1 NPN 3904
R41 R42 R43
0 0 0
R R R
EVNT1/A2 EVNT2/A1 EVNT3/A0
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size Document Number Custom Date: Tuesday, May 22, 2001 Sheet 1 of 5 Rev 0.2
35
Publication Release Date: Aug, 2001 Revision 1.0
Temperature Sensing
T
PWM Circuit for FAN1-3 speed control
VSB R44 4.7K R46 1K Q3 PWMOUT1/D1 R51 R 0 MOSFET N 2N7002 R R Q2 PNP 3906 D1 DIODE 1N4148 +12V 10K 1% R45 R 47K/791D
R47 VREF 10K 1% R49
R
RT1
(for system)
10K 1%
THERMISTOR
R48 R 4.7K R50 27K R FAN1IN R52 R 10K
T
R
RT2
C7 + 47u
(for cpu1)
10K 1% R53 R
THERMISTOR RT3
T
JP1 3 2 1 HEADER 3
10K 1%
(for cpu2)
10K 1%
THERMISTOR
T1 T2 T3
R45,R61 in order to trap address be A0=1,A1=0
R54 GNDA 4.7K R55 1K Q5 PWMOUT2/D0 R60 R D+ 30K 1% DCAPACITOR C9 3300p R58 R 0 R61 R 47K/791D MOSFET N 2N7002 R R Q4 PNP 3906
+12V
D2 DIODE 1N4148
Measuring CPU temperature by either thermistor or diode.
VREF T2 GNDA
R56 R 4.7K R57 27K R R59 R 10K FAN2IN
JP2 + C8 47u 3 2 1 HEADER 3
(from PII/PIII CPU)
+12V R63 R RT4
T
10K 1%
R62 4.7K R64 1K
R Q6 PNP 3906 D3 DIODE 1N4148
VREF
10K 1%
THERMISTOR
(for cpu2)
R
R65 R 4.7K R66 27K R R68 R 10K FAN3IN
T2
GNDA R67 OUT3/VID90 R 0
Q7 MOSFET N 2N7002
JP3 + C10 47u 3 2 1 HEADER 3
PWM Circuit for FAN4-5 speed control when select these pin to PWMOUT/FAN function
+12V R69 4.7K R70 1K R75 PWMOUT4 0 Q9 R MOSFET N 2N7002 JP4 + C11 47u 3 2 1 HEADER 3 R Q8 PNP 3906 D4 DIODE 1N4148
Select VID Table
R71 R 4.7K R73 27K R R76 R 10K FAN4IN R72 VSB R 47K /791D OUT3/VID90 R74 47K /791D R OUT3/VID90
R
Select one of the two VID Table setting. 0:Old VID Table(VRM 8.3) 1:New VID Table(VRM 9.0)
+12V R77 4.7K R78 1K R81 PWMOUT5 0 Q11 R MOSFET N 2N7002 JP5 + C12 47u 3 2 1 HEADER 3 R R Q10 PNP 3906 D5 DIODE 1N4148
R79 R 4.7K R80 27K R R82 R 10K FAN5IN WINBOND ELECTRONICS CORP.
Title W83782D-W83791D Application Circuit Size Document Number Custom Date: Tuesday, May 22, 2001 Sheet 2 of 5 Rev 0.2
36
Publication Release Date: Aug, 2001 Revision 1.0
CPU Voltage ID input/output
3VCC R83 R 10K R84 R 10K R85 R 10K R86 R 10K R87 R 10K
Circuits for 782D
EVNT5/IOR# IOR# IOW# CLKIN R88 R R89 R R90 R R91 R R92 R R94 R R96 R R98 R R100 R R102 R R103 R 0 0 0 0 0 0 0 0 0 0 0 EOP/IOW# REXT/CKLIN ADDR/D7 CKOUT/D6 DATA/D5 CTRL/D4 MODE/D3 SPK/D2 PWMOUT1/D1 PWMOUT2/D0
PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0
R93 R95 R97 R99 R101
1K 1K 1K 1K 1K
VID4 VID3 VID2 VID1 VID0 VID0 VID1 VID2 VID3 VID4
SD[0..7]
(From CPU)
}
To Power Regulator
Case Open Circuits
R104 R 0/782D R106 R 2M/782D R109 R 0/782D S1 CASEOPEN SW R110 R 0/791D R111 R 2.2M/791D 74HC14 /791D 4 VBAT R105 R 0/791D C13 CAP 1000p /791D CASEOPEN U2B 3
These two inverters consume VBAT
74HC14 /791D U2A 1 2 R107 R 10K/791D R108 R CASEOPEN 0/791D
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size B Date: Document Number Tuesday, May 22, 2001 Sheet 3 of 5 Rev 0.2
37
Publication Release Date: Aug, 2001 Revision 1.0
Select SPEECH / LED Function by one of three cricuits. / 791D
3. 1.
VCC
C14 SPK/D2 R112 510 1uF/16V
2.
R113 270
VCC C15 LINE_OUT_L LS2
J1
D6 LED 8 ohm SPEAKER 1uF/16V R114 C16 100pF LINE_OUT
From AC' 97 Codec (W83971D)
SPK/D2 SPK/D2 Q13 MOSFET N 2N7000 R115 510 C17 0.1uF Q12 NPN 8050D LINE_OUT_R 1uF/16V
470K
C18
R116 470K C19 100pF
(LED FUNCTION)
(SPEECH FUNCTION)
(SPEECH FUNCTION)
Connect to serial FLASH EEPROM (W55FXX) /791D
VCC R117 EOP/IOW# 0/791D
VCC
R118 EOP/IOW# CTRL/D4 R120 R124 ADDR/D7 0/791D 0/791D 0/791D 1 2 3 4
U3 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7
R119 0/791D 0/791D
MODE/D3 U4 R121 MODE VDD CLK DATA W55F10 8 7 0/791D 6 5 R126 R128 0/791D CKOUT/D6 DATA/D5 3 4 0/791D MODE/D3 1 2 U5 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 1 2 3 4 U6 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 1 0/791D 2 3
6 5
R122 R125 0/791D
CKOUT/D6 CTRL/D4 DATA/D5 ADDR/D7
R123
EOP CTRL VSS ADDR
0/791D R127
4
Connect 1 FLASH
Connect 2 or more FLASH
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size Document Number Custom Date: Tuesday, May 22, 2001 Sheet 4 of 5 Rev 0.2
38
Publication Release Date: Aug, 2001 Revision 1.0
REV 0.1 0.15 0.16
Decription First Publication
Add FAN/PWMOUT4-5 circuit Change R34 connect to 5VSB 1. Change R32/R33 value to 330 ohm 2. Modify R34 value as 220K ohm 3. Change SMI# (pin 44) circuit. This update is for B version. Update Pin44 (SMI#/LEDOUT) circuit. This update is for C version.
0.17
0.2
WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application circuit Size A Date: Document Number Tuesday, May 22, 2001 Sheet 5 of 5 Rev 0.2
39
Publication Release Date: Aug, 2001 Revision 1.0

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