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| DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAH32868A QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before the device enters the low-power (LPM) and the QERR output is driven low, then it stays lateched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity check computation. The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when high). The C input should not be switched during normal operation. It should be hardwired to a valid low or high level to configure the register in the desired mode. The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 orDCS1 input is low, the Qn outputs will function normally. Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0 orDCS1 is low, the QERR output will function normally. The RESET input has priority over the DCS0 and DCS1 control and when driven low will force the Qn outputs low, and the QERR output high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0 and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only, then the CSGEN input should be pulled up to Vdd through a pullup resistor. The two VREF pins (A1 and V1) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The ICSSSTUAH32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (Vref) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the ICSSSTUAH32868A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The ICSSSTUAH32868A includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs is generated two clock cycles after the data, to which the QERR signal applies, is registered. The ICSSSTUAH32868A accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drain 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Features * 28-bit 1:2 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs Applications * DDR2 Memory Modules * Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A * Supports LVCMOS switching levels on CSGEN and RESET inputs * Ideal for DDR2 400, 533, and 667 * Low voltage operation: VDD = 1.7V to 1.9V * Available in 176-ball LFBGA package Block Diagram M2 RESET CLK CLK VREF L1 M1 A5, AB5 DCKE0, DCKE1 D1, C1 2 2 F2, E2 D 2 QCKE0A, QCKE1A CK R Q H8, F8 QCKE0B, QCKE1B QODT0A, QODT1A DODT0, DODT1 N1, P1 2 2 N2, P2 D CK R Q 2 M7, M8 QODT0B, QODT1B DCS0 K1 D CK R Q K2 QCS0A L7 QCS0B CSGEN L2 DCS1 J1 D CK R Q J2 QCS1A L8 QCS1B One of 22 Channels D1 A2 D CE CK Q A7 Q1A R A8 Q1B TO 21 OTHER CHANNELS (D2-D5, D7, D9-D12, D17-D28) 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity Logic Diagram M2 RESET CLK CLK L1 M1 D1-D5, D7, D9-D12, D17-D28 VREF A5, AB5 22 D1-D5, D7, D9-D12, D17-D28 22 D CK R CE Q 22 D1-D5, D7, D9-D12, D17-D28 22 22 Q1A-Q5A, Q7A, Q9A-Q12A, Q17A-Q28A Q1B-Q5B, Q7B, Q9B-Q12B, Q17B-Q28B D1-D5, D7, D9-D12, D17-D28 22 PAR_IN L3 D CK R CE Q Parity Generator and Error Check M3 QERR DCS0 K1 D CK R Q K2 QCS0A L7 QCS0B CSGEN L2 DCS1 J1 D CK R Q J2 QCS1A L8 QCS1B 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 3 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Block Diagram M2 RESET CLK CLK VREF L1 M1 A5, AB5 DCKE0, DCKE1 W1, Y1 2 2 U2, V2 D 2 QCKE0A, QCKE1A CK R Q R8, U8 QCKE0B, QCKE1B QODT0A, QODT1A DODT0, DODT1 K1, J1 2 2 K2, J2 D CK R Q 2 L7, L8 QODT0B, QODT1B DCS0 N1 D CK R Q N2 QCS0A M7 QCS0B CSGEN L2 DCS1 P1 D CK R Q P2 QCS1A M8 QCS1B One of 22 Channels A2 D1 D CE CK R Q A7 Q1A A8 Q1B TO 21 OTHER CHANNELS (D2-D12, D17-D20, D22, D24-D28) 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 4 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity Logic Diagram M2 RESET CLK CLK L1 M1 D1-D12, D17-D20, D22, D24-D28 VREF A5, AB5 22 D1-D12, D17-D20, D22, D24-D28 22 D CK R CE Q D1-D12, D17-D20, D22, D24-D28 22 22 Q1A-Q12A, Q17A-Q20A, Q22A, Q24A-Q28A Q1B-Q12B, Q17B-Q20B, Q22B, Q24B-Q28B 22 22 D1-D12, D17-D20, D22, D24-D28 PAR_IN L3 D CK R CE Q Parity Generator and Error Check M3 QERR DCS0 N1 D CK R Q N2 QCS0A M7 QCS0B CSGEN L2 DCS1 P1 D CK R Q P2 QCS1A M8 QCS1B 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 5 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configuration 1 A B C D E F G H J K L M N P R T U V W Y AA AB 2 3 4 5 6 7 8 176 BALL BGA TOP VIEW 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 6 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configuration A B C D E F G H J K L M N P R T U V W Y AA AB D2 D4 D6 (DCKE1) D8 (DCKE0) D9 D10 D1 D3 D5 D7 Q6A (QCKE1A) Q8A (QCKE0A) Q10A Q12A C VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF VDD GND VDD GND VDD GND VDD GND VDD GND VDD Q1A Q2A Q3A Q4A Q5A Q7A Q1B Q2B Q3B Q4B Q5B Q6B (QCKE0B) Q7B Q8B (QCKE0B) Q9B A B C D E F G H J K L M N P R T U V W Y AA AB D2 D4 D6 D8 D1 D3 D5 D7 Q6A Q8A C VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF VDD GND VDD GND VDD GND VDD GND VDD GND VDD Q1A Q2A Q3A Q4A Q5A Q7A Q1B Q2B Q3B Q4B Q5B Q6B D9 D10 D11 D12 GND VDD GND VDD GND VDD GND VDD Q9A Q11A D11 D12 D13 (DODT1) D14 (DODT0) CLK CLK D15 (DCS0) D16 (DCS1) D17 D18 Q10A Q12A Q13A (QODT1A) Q14A (QODT0A) CSGEN RESET Q15A (QCS0A) Q16A (QCS1A) Q17A Q19A Q21A (QCKE0A) Q23A (QCKE1A) D22 D24 GND VDD GND VDD GND VDD GND VDD Q9A Q11A Q7B Q8B DCS1 QCS1 GND GND GND GND Q10B GND GND GND GND Q10B Q9B DCS0 CLK CLK D15 (DODT0) D16 (DODT1) D17 D18 QCS0 CSGEN RESET Q15A (QODT0A) Q16A (QODT1A) Q17A Q19A VDD PAR_IN QERR VDD GND VDD VDD GND VDD VDD GND VDD Q12B Q14B (QCS0B) Q15B (QODT0B) Q17B Q11B Q13B (QCS1B) Q16B (QODT1B) Q18B VDD PAR_IN QERR GND VDD GND VDD VDD GND VDD VDD GND VDD Q12B Q14B (QODT0B) Q15B (QCS0B) Q17B Q11B Q13B (QODT1B) Q16B (QCS1B) Q18B GND GND GND GND GND GND GND VDD GND VDD VDD GND VDD VDD GND VDD VDD GND VDD Q19B Q18A Q20A Q20B Q21B Q22B VDD GND VDD VDD GND VDD VDD GND VDD VDD GND VDD Q19B Q18A Q20A Q20B Q21B (QCKE0B) Q22B Q23B (QCKE1B) Q24B D19 D20 Q21A Q23A GND VDD GND VDD GND VDD GND VDD Q22A Q24A Q23B Q24B D19 D20 D21 (DCKE0) D23 (DCKE1) D25 D27 GND VDD GND VDD GND VDD GND VDD Q22A Q24A D21 D23 D22 D24 GND VDD GND VDD GND VDD GND VDD Q25A Q26A Q25B Q26B GND VDD GND VDD GND VDD GND VDD Q25A Q26A Q25B Q26B D25 D27 D26 D28 GND NC GND VDD GND VREF GND VDD Q27A Q28A Q27B Q28B D26 D28 GND NC GND VDD GND VREF GND VDD Q27A Q28A Q27B Q28B 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1:2 REGISTER A (C = 0) NOTE: NC denotes a no-connect (ball present but not connected to the die). 1:2 REGISTER B (C = 1) 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 7 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 RESET H H H H H H H H H H H H H H H L 1 Outputs CLK L or H L or H L or H L or H L or H DCS0 L L L L L L L L L H H H H H H X or Floating DCS1 L L L H H H L L L H H H H H H X or Floating CSGEN X X X X X X X X X L L L H H H X or Floating CLK L or H L or H L or H L or H L or H Dx, DODT, DCKE L H X L H X L H X L H X L H X Qn L H Q 02 L H Q 02 L H Q 02 L H Q 02 Q 02 Q 02 Q 02 L QCS0 QCS1 QODT, QCKE Q 02 Q 02 Q02 Q 02 Q 02 Q02 Q 02 Q 02 Q02 Q 02 Q 02 Q02 Q 02 L Q 02 L Q02 L X or X or X or Floating Floating Floating 2 H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW Output Level before the indicated steady-state conditions were established. 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 8 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 RESET H H H H H H H H H H L 1 Outputs of Inputs = H (D1 - D28) Even Odd Even Odd Even Odd Even Odd X X X or Floating DCS0 L L L L X X X X H X X or Floating DCS1 X X X X L L L L H X X or Floating CLK X or Floating CLK X or Floating PAR_IN2 L L H H L L H H X X X or Floating QERR3 H L L H H L L H QERR04 QERR0 H H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2 PAR_IN arrives one clock cycle after the data to which it applies. 3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 4 If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM plus two clock cycles or until RESET is driven LOW. 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Supply Voltage, VDD Input Voltage Range, VI Output Voltage Range, 1 Rating -0.5V to 2.5V -0.5V to VDD + 2.5V -0.5V to VDDQ + 0.5V 50mA 50mA 50mA 100mA 40.4C/W 29.1C/W -65 to +150C 0m/s Airflow 1m/s Airflow VO1,2 Input Clamp Current, IIK Output Clamp Current, IOK Continuous Output Clamp Current, IO Continuous Current through each VDD or GND Package Thermal Impedance (ja)3 Storage Temperature 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V 0.1V Parameter dV/dt_r dV/dt_f dV/dt_ 1 1 Min. 1 1 Max. 4 4 1 Units V/ns V/ns V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 10 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Terminal Functions Terminal Name GND VDD VREF CLK CLK C RESET CSGEN Electrical Characteristics Ground Input 1.8V nominal 0.9V nominal Differential Input Differential Input LVCMOS Input LVCMOS Input LVCMOS Input Ground Power Supply Voltage Input Reference Clock Description Positive Master Clock Input Negative Master Clock Input Configuration Control Inputs - Register A or Register B Asynchronous Reset Input. Resets registers and disables Vref data and clock differential-input receivers. Chip select gate enable - When high, D1-D28 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. When low, the D1-D28 inputs will be latched and redriven on every rising edge of the clock. Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. Chip select inputs - These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The Register can be programmed to redrive all D inputs (CSGEN high) only when at least one chip select input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28 inputs will be disabled. The outputs of this register bit will not be suspended by the DCS0 and DCS1 controls The outputs of this register bit will not be suspended by the DCS0 and DCS1 controls Parity Input arrives one cycle after corresponding data input Data Outputs that are suspended by the DCS0 and DCS1 controls Data Output that will not be suspended by the DCS0 and DCS1 controls Data Output that will not be suspended by the DCS0 and DCS1 controls Data Output that will not be suspended by the DCS0 and DCS1 controls Output Error bit, generated one cycle after the corresponding data output No Connection D1 - D28 DCS0, DCS1 SSTL_18 Input SSTL_18 Input DCKE0, DCKE1 DODT0, DODT1 PAR_IN Q1 - Q28 QCS0, QCS1 QCKE0, QCKE1 QODT0, QODT1 QERR NC SSTL_18 Input SSTL_18 Input SSTL_18 Input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS Open Drain Output 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 11 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Operating Characteristics, TA = 25C The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is Low. Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Parameter I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Range Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data CSR and PAR_IN inputs RESET, C0, C1 CLK, CLK Min. 1.7 0.49 * VDD VREF - 0.04 0 VREF + 0.25 Typ. 1.8 0.5 * VDD VREF Max. 1.9 0.51 * VDD VREF + 0.04 VDD VREF - 0.25 Units V V V V VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ 0.675 600 -12 12 0 +70 1.125 V V V mV mA C 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 12 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDDQ/VDD = 2.5V 0.2V. Symbol VOH VOL IIL Parameter Output HIGH Voltage Output LOW Voltage All Inputs Static Standby Test Conditions IOH = -12mA, VDDQ = 1.7V IOL = 12mA, VDDQ = 1.7V VI = VDD or GND; VDD = 1.9V IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 250mV VICR = 0.9V, VIPP = 600mV VI = VDD or GND Min. 1.2 Typ. Max. 0.5 Units V V A A -5 200 +5 10 mA 170 A/Clock MHz A/Clock MHz/ Data 3.5 4 5 pF IDD Static Operating Dynamic Operating (clock only) IDDD Dynamic Operating (per each data input) 1:2 mode Data Inputs CI CLK and CLK RESET 500 82 2 3 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 13 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V 0.1V Symbol fCLOCK tW tACT 1,2 1,3 Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS0 before CLK, CLK, DCS1 and CSGEN HIGH; DCS1 before CLK, CLK, DCS0 and CSGEN HIGH; Min. 1 Max. 410 10 15 Units MHz ns ns ns ns ns tINACT 0.7 0.5 tSU Setup Time DCS0 before CLK, CLK, DCS1 LOW and CSGEN HIGH or LOW; DCS1 before CLK, CLK, DCS0 LOW and CSGEN HIGH or LOW DODTn, DCKEn, PAR_IN, and data before CLK, CLK 0.5 0.5 0.5 ns ns ns tH Hold Time DCSn, DODT,n DCKEn, and data after CLK, CLK PAR_IN after CLK, CLK 1 This parameter is not production tested. 2 VREF must be held at a valid input voltage level and data inputs must be held at valid voltage levels for a minimum time of tACT (max) after RESET is taken HIGH. 3 VREF data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time of tINACT (max) after RESET is taken LOW. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V 0.1V Symbol fMAX tPDM tPDMSS tLH tHL tPLH tPHL Parameter Max Input Clock Frequency Propagation Delay, single bit switching, CLK / CLK to Qn Propagation Delay, simultaneous switching, CLK / CLK to Qn LOW to HIGH Propagation Delay, CLK / CLK to QERR HIGH to LOW Propagation Delay, CLK / CLK to QERR HIGH to LOW Propagation Delay, RESET to Qn LOW to HIGH Propagation Delay, RESET to QERR Min. 410 1.3 1.2 0.8 Max. 1.9 2 3 2.4 3.2 3.5 Units MHz ns ns ns ns ns ns 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 14 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET CSGEN DCS0 DCS1 n CLK n +1 n+2 n+3 n+4 CLK tACT Dn, DODTn, DCKEn tPDM, tPDMSS CLK to Q Qn, QODTn, QCKEn tSU PARIN tPHL CLK to QERR QERR Data to QERR Latency tPHL, tPLH CLK to QERR tH tSU tH H, L, or X H or L NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held LOW for a minimum time of tACTMAX, to avoid false error. 2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 15 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven LOW, it stays latched LOW for a minimum of two clock cycles or until RESET is driven LOW. 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 16 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT CSGEN DCS0 DCS1 CLK CLK Dn, DODTn, DCKEn tRPHL RESET to Q Qn, QODTn, QCKEn PARIN QERR tRPLH RESET to QERR H, L, or X H or L NOTE: 1.After RESET is switched from LOW to HIGH, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 17 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD/2 RL = 1K DUT TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point Out CL = 30 pF TL = 350ps, 50 ZO = 50 Test Point Test Point DUT CLK Test Point Out CLK RL = 50 ZO = 50 Test Point RL = 1K CLK Inputs ZO = 50 Production-Test Load Circuit Simulation Load Circuit CLK CLK VICR tPLH Output VTT VICR tPHL VOH VTT VOL VID LVCMOS RESET Input tINACT IDD VDD VDD/2 VDD/2 0V tACT 90% 10% LVCMOS RESET Input Voltage Waveforms - Propagation Delay Times VIH VDD/2 VIL tRPHL VOH Voltage and Current Waveforms Inputs Active and Inactive Times Output VTT VOL tW Input VICR VICR VID Voltage Waveforms - Propagation Delay Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID Voltage Waveforms - Setup and Hold Times 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 18 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD DUT Out RL = 50 Test Point DUT Out RL = 1K Test Point CL = 10 pF CL = 10 pF Load Circuit: High-to-Low Slew-Rate Adjustment Load Circuit: Error Output Measurements Output 80% VOH LVCMOS RESET Input tPLH VCC VCC/2 0V 20% dv_f dt_f VOL VOH Output Waveform 2 0.15V 0V Voltage Waveforms: High-to-Low Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) DUT Out CL = 10 pF Test Point RL = 50 Timing Inputs VICR tHL VICR VI(PP) Output Waveform 1 VCC VCC/2 VOL Load Circuit: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) dt_r dv_r 80% VOH Timing Inputs VICR tHL VICR VI(PP) VOH 20% Output VOL Output Waveform 2 0.15V 0V Voltage Waveforms: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 19 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 C SEATING PLANE A1 T b REF 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) d TYP D1 Numeric Designations for Horizontal Grid D -e- TYP TOP VIEW E h TYP 0.12 C E1 c REF -e- TYP ALL DIMENSIONS IN MILLIMETERS BALL GRID d T Min/Max e Horiz Vert Total Min/Max D E 8 22 176 0.35/0.45 15.00 Bsc 6.00 Bsc 0.94/1.20 0.65 Bsc h Min/Max 0.25/0.35 REF. DIMS D1 E1 b c 13.65 Bsc 4.55 Bsc 0.675 0.725 *** NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, MO-205*, MO-255**, MO-246*** 10-0055 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 20 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Ordering Information ICSSSTUAH XX Family XX XXX Device Type Package X Shipping Carrier T Tape and Reel HLF Low Profile, Fine Pitch, Ball Grid Array - Lead-Free 868A 28-Bit Configurable Registered Buffer for DDR2 32 Double Density 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 21 ICSSSTUAH32868A 7115/9 ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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