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PEDL9201-03 Semiconductor
PEDL9201-03 This version: Sep. 2000 MSM9201-01 Previous version: Nov. 1997
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Semiconductor MSM9201-01
Fluorescent Display Tube Controller Driver
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GENERAL DESCRIPTION
The MSM9201-01 is a dot matrix fluorescent display tube controller driver IC which displays characters, numerics and symbols. Dot matrix fluorescent display tube drive signals are generated by serial data sent from a microcontroller. A display system is easily realized by internal ROM and RAM for character display.
FEATURES
* Logic power supply (VDD) : 3.3 V10%/5.0 V10% * Fluorescent display tube drive power supply (VDISP) : 3.3 V10%/5.0 V10% * Fluorescent display tube drive power supply (VFL) : -20 to -60 V * VFD driver output current (VFD driver output can directly be connected to the fluorescent display tube. No pull-down resistor is required.) - Segment driver (SEG1 to SEG35) : -5.0 mA (VFL=-60V) - Segment driver (AD1 to AD8) : -10.0 mA (VFL=-60V) - Grid driver (COM1 to COM16) : -20.0 mA (VFL=-60V) * General output port output current - Output driver (P1-4) : 1.0 mA (VDD=3.3V10%) 2.0 mA (VDD=5.0V10%) * Content of display - CGROM 57 dots, 240 types (character data) - CGRAM 57 dots, 16 types (character data) - ADRAM 24 (display digit) 4 bits (symbol data) - DCRAM 24 (display digit) 8 bits (register for character data display) - General output port 4 bits (static mode) * Display control function - Display digit : 9 to 24 digits - Display duty (contrast adjustment) : 8 stages - All lights ON/OFF * 3 interfaces with microcontroller : DA, CS, CP (4 interfaces if RESET is added) * 1-byte instruction execution (excluding data write to RAM) * Built-in oscillation circuit (external C and R) * Package options: 80-pin plastic QFP (QFP80-P-1414-0.65-K) (Product name: MSM9201-01GS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM9201-01GS-BK)
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PEDL9201-03 Semiconductor MSM9201-01
BLOCK DIAGRAM
VDISP VDD GND VFL
DCRAM 24w8b
CGROM 240w35b Segment Driver CGRAM 16w35b
SEG1
RESET DA CP CS 8-bit Shift Register
SEG35 AD1 AD Driver AD4
DCRAM Address Counter
ADRAM 24w8b
Address Selector Command Decoder Control Circuit Write Address Counter Read Address Counter
P1 Port Driver P4 Digit Control Duty Control COM1 Grid Driver COM24
Timing Generator 1 OSC0 Oscillator OSC1
Timing Generator 2
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PEDL9201-03 Semiconductor MSM9201-01
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits Input pin
VDD INPUT
VDD
GND
GND
Output pin
VDD VDD OUTPUT
GND
GND
Schematic Diagram of Driver Output Circuit
VDISP
VDISP OUTPUT
VFL
VFL
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PEDL9201-03 Semiconductor MSM9201-01
PIN CONFIGURATION (TOP VIEW)
AD3 AD4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
AD2 AD1 VDISP2 NC VFL2 P4 P3 P2 P1 VDD DA CP CS RESET OSC1 OSC0 GND VFL1 COM24 COM23
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3
SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 VDISP1 COM1 COM2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC: No connection
80-Pin Plastic QFP (QFP80-P-1414-0.65-K)
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PEDL9201-03 Semiconductor MSM9201-01
69 RESET
80 VDISP2 79 NC
68 OSC1
67 OSC0
66 GND
78 VFL2
65 VFL1
73 VDD
71 CP
70 CS
72 D4
77 P4
76 P3
75 P2
74 P1
AD1 AD2 AD3 AD4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 COM24 63 COM23 62 COM22 61 COM21 60 COM20 59 COM19 58 COM18 57 COM17 56 COM16 55 COM15 54 COM14 53 COM13 52 COM12 51 COM11 50 COM10 49 COM9 48 COM8 47 COM7 46 COM6 45 COM5 44 COM4 43 COM3 42 COM2 41 COM1
SEG21 25 SEG22 26 SEG23 27 SEG24 28 SEG25 29 SEG26 30 SEG27 31 SEG28 32 SEG29 33 SEG30 34 SEG31 35 SEG32 36 SEG33 37 SEG34 38 SEG35 39 VDISP1 40
NC: No connection
80-Pin Plastic QFP (QFP80-P-1420-0.80-BK)
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PEDL9201-03 Semiconductor MSM9201-01
PIN DESCRIPTIONS
Pin Symbol Type Connects to: QFP-1* QFP-2* 3-27 5-39 SEG1-35 O Description
Fluorescent Fluorescent display tube anode electrode drive output. tube anode Directly connected to fluorescent display tube. No pull-down electrode 39-62 41-64 COM1-24 O tube grid electrode 1, 2, 79, 80 1-4 AD1-4 O resistor is required. IOH>-5.0 mA Directly connected to fluorescent display tube. No pull-down resistor is required. IOH>-20.0 mA Fluorescent Fluorescent display tube grid electrode drive output.
Fluorescent Fluorescent display tube anode electrode drive output. tube anode Directly connected to fluorescent display tube. No pull-down electrode LED drive 72-75 71 38, 78 64 63, 76 70 69 68 74-77 73 40, 80 66 65, 78 72 71 70 P1-4 VDD VDISP1-2 GND VFL1-2 DA CP CS O -- -- -- -- I I I Microcontroller Microcontroller Microcontroller Serial data input (positive logic). Input from LSB. Shift clock input. Serial data is shifted on the rising edge of CP. Chip select input. Setting this pin to "H" disables serial data transfer. control terminals Power supply resistor is required. IOH>-10.0 mA General port output. Output of these pins in static operation, so these pins can drive the LED. IOH>-2.0 mA VDD-GND are power supplies for internal logic. VDISP-VFL are power supplies for driving fluorescent tubes. Use the same power supply for VDD and VDISP.
*
QFP-1 : QFP80-P-1414-0.65-K QFP-2 : QFP80-P-1420-0.80-BK
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PEDL9201-03 Semiconductor MSM9201-01
Pin QFP-1* QFP-2*
Symbol Type Connects to: Reset input.
Description
Setting this pin to "Low" initializes all the functions. The initial status is as follows. * Address of each RAM * Data of each RAM Micro67 69 RESET I or C2, R2 * Number of display digits * All lights ON or OFF * All outputs controller * Contrast adjusment address "00"H Content is undefined 24 digits 8/16 OFF mode "Low" level
RESET C2 R2
(Circuit when R and C are connected externally) See Application Circuit.
External RC pin for RC oscillation. 65 67 OSC0 I C1, R1 66 68 OSC1 O Connect R and C externally. The RC time constant depends on the VDD voltage used. Set the target oscillation frequency to 2 MHz. OSC0 R1 OSC1 C1 (RC oscillation circuit) See Application Circuit.
*
QFP-1 : QFP80-P-1414-0.65-K QFP-2 : QFP80-P-1420-0.80-BK
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PEDL9201-03 Semiconductor MSM9201-01
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage 1 Supply Voltage 2 Input Voltage Power Dissipation Storage Temperature Symbol VDD VDISP VFL VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Ta25C Condition (*1) (*1) -- -- QFP80-P-1414-0.65-K QFP80-P-1420-0.80-BK -- COM1-COM24 AD1-AD4 SEG1-SEG35 P1-P4 Rating -0.3 to +6.5 -0.3 to +6.5 -80 to VDISP+0.3 -80 to VDD+0.3 565 643 -55 to +150 -30 to 0.0 -20 to 0.0 -10 to 0.0 -4.0 to +4.0 mA Unit V V V V mW C
*1 Use the same power supply for VDD and VDISP.
RECOMMENDED OPERATING CONDITIONS (1)
When the power supply voltage is 5V (typ)
Parameter Supply Voltage 1 Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDD VDISP VFL VIH VIL fC fOSC fFR Top Condition -- -- All input pins excluding OSC0 pin -- R=3.3kW, C=47pF
DIGIT=1-24, R=3.3kW, C=47pF
Min. 4.5 -60 -- -- 1.5 122 -40
Typ. 5.0 -- -- -- -- 2.0 163 --
Max. 5.5 -20 -- 0.3VDD 1.0 2.5 204 85
Unit V V V V MHz MHz Hz C
All input pins excluding OSC0 pin 0.7VDD
--
RECOMMENDED OPERATING CONDITIONS (2)
When the power supply voltage is 3.3V (typ)
Parameter Supply Voltage 1 Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDD VDISP VFL VIH VIL fC fOSC fFR Top Condition -- -- All input pins excluding OSC0 pin -- R=3.3kW, C=39pF
DIGIT=1-24, R=3.3kW, C=39pF
Min. 3.0 -60 -- -- 1.5 122 -40
Typ. 3.3 -- -- -- -- 2.0 163 --
Max. 3.6 -20 -- 0.2VDD 1.0 2.5 204 85
Unit V V V V MHz MHz Hz C
All input pins excluding OSC0 pin 0.8VDD
--
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PEDL9201-03 Semiconductor MSM9201-01
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD=VDISP=5.0V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 Low Level Output Voltage VOL2 IDD1 Supply Current IDD2 VDD, VDISP VOL1 Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET COM1-24 AD1-4 SEG1-35 P1-4 COM1-24 AD1-4 SEG1-35 P1-4 IOL1=2mA Duty=15/16 fOSC= 2MHz, no load Digit=1-24 All outputs go ON Duty=8/16 Digit=1-9 All outputs go OFF -- 3 mA -- 4 mA -- 1.0 V -- -- VFL+1.0 V Condition -- -- VIH=VDD VIL=0.0V IOH1=-20.0mA IOH2=-10.0mA IOH3=-5.0mA IOH4=-2.0mA Min. 0.7VDD -- -1.0 -1.0 VDISP-1.5 VDISP-1.5 VDISP-1.5 VDD-1.0 Max. -- 0.3VDD 1.0 1.0 -- -- -- -- Unit V V A A V V V V
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PEDL9201-03 Semiconductor DC Characteristics (2)
(VDD=VDISP=3.3V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 Low Level Output Voltage VOL2 IDD1 Supply Current IDD2 VDD, VDISP VOL1 Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET COM1-24 AD1-4 SEG1-35 P1-4 COM1-24 AD1-4 SEG1-35 P1-4 IOL1=2mA Duty=15/16 fOSC= 2MHz, no load Digit=1-24 All outputs go ON Duty=8/16 Digit=1-9 All outputs go OFF -- 2 mA -- 3 mA -- 1.0 V -- -- VFL+1.0 V Condition -- -- VIH=VDD VIL=0.0V IOH1=-20.0mA IOH2=-10.0mA IOH3=-5.0mA IOH4=-1.0mA Min. 0.8VDD -- -1.0 -1.0 VDISP-1.5 VDISP-1.5 VDISP-1.5 VDD-1.0 Max. -- 0.2VDD 1.0 1.0 -- -- -- -- Unit V V A A V V V V
MSM9201-01
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PEDL9201-03 Semiconductor AC Characteristics (1)
(VDD, VDISP=5.0V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter CP Frequncy CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width DA Wait Time Slew Rate (All Drivers) VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSOFF tR tF tPRZ tPOF Cl=100pF Condition -- -- -- -- -- R1=3.3kW, C1=47pF -- R1=3.3kW, C1=47pF When RESET signal is input externally -- tR=20% to 80% tF=80% to 20% Min. -- 300 300 300 300 16 300 8 300 300 -- -- -- 5.0 Max. 1.0 -- -- -- -- -- -- -- -- -- 4.0 4.0 100 -- Unit MHz ns ns ns ns ms ns ms ns ms ms ms ms ms
MSM9201-01
When mounted on the unit When mounted on the unit, VDD=0.0V
AC Characteristics (2)
(VDD, VDISP=3.3V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter CP Frequncy CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width DA Wait Time Slew Rate (All Drivers) VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSOFF tR tF tPRZ tPOF Cl=100pF Condition -- -- -- -- -- R1=3.3kW, C1=39pF -- R1=3.3kW, C1=39pF When RESET signal is input externally -- tR=20% to 80% tF=80% to 20% Min. -- 300 300 300 300 16 300 8 300 300 -- -- -- 5.0 Max. 1.0 -- -- -- -- -- -- -- -- -- 4.0 4.0 100 -- Unit MHz ns ns ns ns ms ns ms ns ms ms ms ms ms
When mounted on the unit When mounted on the unit, VDD=0.0V
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PEDL9201-03 Semiconductor MSM9201-01
TIMING DIAGRAM
Symbol VIH VIL VDD=3.3V10% 0.8 VDD 0.2 VDD VDD=5.0V10% 0.7 VDD 0.3 VDD
* Data Timing
tCSS CS fC CP tDS DA VALID VALID tDOFF tDH VALID VALID VIH VIL tCW tCW tCSH VIH VIL
tCSW
0.7 VDD 0.3 VDD
* Reset Timing
0.8 VDD 0.0 V VIH VIL
When external R and C are connected.
VDD RESET
tPRZ tRSON
When input externally
tWRES tRSOFF
DA
VIH VIL
* Output Timing
All outputs
tR
tF
0.8 VDISP 0.2 VFL
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PEDL9201-03 Semiconductor Digit Output Timing (for 24-digit display, at a duty of 15/16) MSM9201-01
T=8/ fOSC
Frame cycle t1=1536T Display timing t2=60T Blank timing t3=4T
COM1 COM2 COM3 COM4 COM5 COM6
(t1=6.144 ms when fosc=2.0 MHz) (t2=240 ms when fosc=2.0 MHz) (t3=16 ms when fosc=2.0 MHz)
VDISP VFL
COM19 COM20 COM21 COM22 COM23 COM24 AD1-4 SEG1-35
VDISP VFL
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PEDL9201-03 Semiconductor MSM9201-01
FUNCTIONAL DESCRIPTION
Command List
Command 1 DCRAM data write
LSB
1st byte B1 X1 B2 X2 B3 X3 B4 X4 B5 1 B6 0
MSB
LSB
2nd byte B1 C1 B2 C2 B3 C3 B4 C4 B5 C5 B6 C6
MSB
B0 X0
B7 0
B0 C0 C0 C1
B7 C7
C5 C10 C15 C20 C25 C30 C6 C11 C16 C21 C26 C31 C7 C12 C17 C22 C27 C32 C8 C13 C18 C23 C28 C33 C9 C14 C19 C24 C29 C34 C1 : : : : : : : : C2 C3
2 CGRAM data write 1
X0
X1
X2
X3
*
0
1
0
C2 C3 C4
3 ADRAM data write 5 Display duty set 7 All lights ON/OFF Test mode
X0 D0 L
X1 P2 D1 K1 H
X2 P3 D2 K2
X3 P4
X4
1 0 1 0 1
1 0 0 1 1
0 1 1 1 1
C0
*
*
*
* * * * * *
2nd byte 3rd byte 4th byte 5th byte 6th byte
4 General output port set P1 6 Number of display digits set K0
*
K3
*
*
* * * *
*
Xn Cn Pn Dn Kn H L
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte when RAM data for the 2nd and later bytes is written. Note: The test mode is used for inspection before shipment. It is not a user function.
Don't care Address specification for each RAM Character code specification for each RAM General output port status specification Display duty specification Number of display digits specification All lights ON instruction All lights OFF instruction
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PEDL9201-03 Semiconductor Positional Relationship Between SEGn and ADn (one digit) MSM9201-01
C0 AD1 C1 AD2 C2 AD3 C3 AD4 C0
SEG1
ADRAM written data. Corresponds to 2nd byte
C1
SEG2
C2
SEG3
C3
SEG4
C4
SEG5
C5
SEG6
C6
SEG7
C7
SEG8
C8
SEG9
C9
SEG10
C10
SEG11
C11
SEG12
C12
SEG13
C13
SEG14
C14
SEG15
C15
SEG16
C16
SEG17
C17
SEG18
C18
SEG19
C19
SEG20
C20
SEG21
C21
SEG22
C22
SEG23
C23
SEG24
C24
SEG25
C25
SEG26
C26
SEG27
C27
SEG28
C28
SEG29
C29
SEG30
C30
SEG31
C31
SEG32
C32
SEG33
C33
SEG34
C34
SEG35
CGRAM data write mode. Corresponds to 2nd byte CGRAM data write mode. Corresponds to 3rd byte CGRAM data write mode. Corresponds to 4th byte
CGRAM data write mode. Corresponds to 6th byte CGRAM data write mode. Corresponds to 5th byte
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PEDL9201-03 Semiconductor Data Transfer Method and Command Write Method Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rise of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units.
CS CP tDOFF tCSH
MSM9201-01
DA
B0 B1 B2 B3 B4 B5 B6 B7 LSB 1st byte MSB
B0 B1 B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
B0 B1 B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
When data is written to DCRAM* Command and address data
Character code data
Character code data of the next address
*
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) which initializes all functions. The initial status is as follows. * Address of each RAM .................. address "00"H * Data of each RAM ........................ All contents are undefined * General output port ..................... All general output ports go "Low" * Number of display digits ............ 24 digits * Contrast adjustment ..................... 8/16 * All display lights ON or OFF ..... OFF mode * Segment output ............................ All segment outputs go "Low" * AD output ..................................... All AD outputs go "Low" After reset is executed, perform settings again according to "Initial Setting Flowchart" shown later.
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PEDL9201-03 Semiconductor Description of Commands and Functions 1. DCRAM data write (Specifies the address (00H to 1FH) of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has 5-bit addresses to store character code of CGROM and CGRAM. The character code specified in DCRAM is converted to a 57 dot matrix character pattern via CGROM or CGRAM. The DCRAM can store 24 characters. MSM9201-01
[Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 X4
LSB
1
0
0
MSB
: selects DCRAM data write mode and specifies DCRAM address. (Ex: Specifies DCRAM address 00H) : specifies character code of CGROM and CGRAM. (written into DCRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character codes as follows. Since the addresses of DCRAM are automatically incremented, they do not need to be specified.
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PEDL9201-03 Semiconductor MSM9201-01
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: specifies character code of CGROM and CGRAM. (written into DCRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (written into DCRAM address 02H)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (25th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (written into DCRAM address 17H)
Setting of CGROM and CGRAM character codes for up to 24 digits is now complete. To further specify character codes continuously from DCRAM address 00H, dummy character codes must be specified for DCRAM address 18H to 1FH (so that DCRAM address will be incremented automatically and will be reset to 00H).
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (26th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies dummy character code of CGROM and CGRAM. (not written into DCRAM address)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (33th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: specifies dummy character code of CGROM and CGRAM. (not written into DCRAM address)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (34th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM. (rewritten into DCRAM address 00H)
X0 (LSB) to X4 (MSB): DCRAM address (5 bits: 24 characters) C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters)
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PEDL9201-03 Semiconductor MSM9201-01
[COM positions and set DCRAM address]
HEX X0 X1 X2 X3 X4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COM position COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
HEX X0 X1 X2 X3 X4 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
COM position COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 -- -- -- -- -- -- -- --
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PEDL9201-03 Semiconductor MSM9201-01
2. CGRAM data write (Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has 4-bit addresses to store 57 dot matrix character patterns. A character pattern stored in CGRAM can be displayed by specifying the character code (address) in DCRAM. The addresses of CGRAM are assigned to 00H to 0FH. (All the other addresses are the CGROM addresses.) (The CGRAM can store 16 types of character patterns.) [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3
LSB
*
0
1
0
MSB
: selects CGRAM data write mode and specifies CGRAM address. (Ex: specifies CGRAM address 00H) : specifies 1st column data. (written into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) C1 C6 C11 C16 C21 C26 C31
LSB
*
MSB
: specifies 2nd column data. (written into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 4th byte (4th) C2 C7 C12 C17 C22 C27 C32
LSB
*
MSB
: specifies 3rd column data. (written into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 5th byte (5th) C3 C8 C13 C18 C23 C28 C33
LSB
*
MSB
: specifies 4th column data. (written into CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (6th) C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data. (written into CGRAM address 00H)
To specify character pattern data continuously to the next address, specify only character pattern data as follows. Since the addresses of CGRAM are automatically incremented, they do not need to be specified. The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes.
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PEDL9201-03 Semiconductor MSM9201-01
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (7th) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
: specifies 1st column data. (written into CGRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (11th) 2nd byte (12th) C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data. (written into CGRAM address 01H) : specifies 1st column data. (written into CGRAM address 02H)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (16th) C4 C9 C14 C19 C24 C29 C34
*
MSB
: specifies 5th column data. (written into CGRAM address 02H)
LSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (77th) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
: specifies 1st column data. (written into CGRAM address 0FH)
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (81th) 2nd byte (82th) C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data. (written into CGRAM address 0FH) : specifies 1st column data. (rewritten into CGRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (86th) C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data. (rewritten into CGRAM address 00H.)
X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters) C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)
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PEDL9201-03 Semiconductor [CGROM addresses and set CGRAM addresses] Refer to ROM CODE
HEX X0 X1 X2 X3 00 01 02 03 04 05 06 07 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 CGROM address RAM00(00000000B) RAM01(00000001B) RAM02(00000010B) RAM03(00000011B) RAM04(00000100B) RAM05(00000101B) RAM06(00000110B) RAM07(00000111B) HEX X0 X1 X2 X3 08 09 0A 0B 0C 0D 0E 0F 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 CGROM address RAM08(00001000B) RAM09(00001001B) RAM0A(00001010B) RAM0B(00001011B) RAM0C(00001100B) RAM0D(00001101B) RAM0E(00001110B) RAM0F(00001111B)
MSM9201-01
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PEDL9201-03 Semiconductor MSM9201-01
Positional relationship between the output area of CGROM and that of CGRAM
C0 C5 C10 C15 C20 C25 C30 Corresponds to 2nd byte (1st column) Corresponds to 3rd byte (2nd column) C1 C6 C11 C16 C21 C26 C31 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 Corresponds to 6th byte (5th column) Corresponds to 5th byte (4th column) Corresponds to 4th byte (3rd column)
Note: CGROM (Character Generator ROM) has 8-bit addresses to generate 57 dot matrix character patterns. CGRAM can store 240 types opf character patterns.
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PEDL9201-03 Semiconductor 3. ADRAM data write (specifies address of ADRAM and writes symbol data) ADRAM (Additional Data RAM) has 4-bit addresses to store symbol data. Symbol data specified in ADRAM is directly output without CGROM and CGRAM. (The DRAM can store 4 types of symbol patterns for each digit.) The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format]
LSB MSB
MSM9201-01
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 X4
LSB
1
1
0
MSB
: selects ADRAM data write mode and specifies ADRAM address. (Ex: specifies ADRAM address 00H) : specifies symbol data. (written into ADRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 * * * *
To specify symbol data continuously to the next address, specify only symbol data as follows. The addresses of ADRAM are automatically incremented. Specification of ADRAM addresses is therefore unnecessary.
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) 2nd byte (4th) C0 C1 C2 C3
LSB
*
*
*
*
MSB
: specifies symbol data. (written into ADRAM address 01H) : specifies symbol data. (written into ADRAM address 02H)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3
LSB
*
*
*
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (17th) C0 C1 C2 C3 * * * * : specifies symbol data. (written into ADRAM address 17FH)
Setting of symbol data for up to 24 digits is now complete. To further specify symbol data continuously from DCRAM address 00H, dummy symbol data must be specified for ADRAM addresses 18H to 1FH (so that the ADRAM address will be incremented automatically and will be reset to 00H).
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (18th) C0 C1 C2 C3
LSB
*
*
*
*
MSB
: specifies dummy symbol data. (not written into ADRAM address)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (65th) 2nd byte (66th) C0 C1 C2 C3
LSB
*
*
*
*
MSB
: specifies dummy symbol data. (not written into ADRAM address) : specifies symbol data. (rewritten into ADRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7
X0 (LSB) to X4 (MSB): ADRAM addresses (5 bits: 24 characters) C0 (LSB) to C3 (MSB): Symbol data (4 bits: 4-symbol data per digit) 24/35
PEDL9201-03 Semiconductor MSM9201-01
[COM positions and ADRAM addresses]
HEX X0 X1 X2 X3 X4 COM position HEX X0 X1 X2 X3 X4 COM position 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 -- -- -- -- -- -- -- --
4. General output port set (specifies the general output port status) The general output port is an output for 4-bit static operation. It is used to control other I/O devices and turn on LED. (Static operation.) The fluorescent display tube cannot be driven by this output port, because when at the "High" level this output becomes the VDD voltage and when at the "Low" level it becomes the ground potential. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte P1 P2 P3 P4 * 0 0 1 : selects general output port and specifies the output status.
P1-P4 : general output ports * : don't care [Set data and set state of general output port]
Pn 0 1 Display state of general output port Sets P1-P4 to Low Sets P1-P4 to High (The state when power is applied or when RESET is input)
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PEDL9201-03 Semiconductor MSM9201-01
5. Display duty set (writes display duty value to duty cycle register) Display duty adjusts contrast in 8 stages using 3-bit data. At the time power is turned on or the RESET signal is input, the duty cycle register value is "0". Always execute this instruction before turning the display on, then set a desired duty value. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte D0 D1 D2 * * 1 0 1 : selects display duty set mode and sets duty value.
D0 (LSB) to D2 (MSB) : display duty data (3 bits: 8 stages) * : don't care [Relation between setup data and controlled COM duty]
HEX 0 1 2 3 4 5 6 7
D2 0 0 0 0 1 1 1 1
D1 0 0 1 1 0 0 1 1
D0 0 1 0 1 0 1 0 1
COM duty 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 (The state at the time power is turned on or RESET signal is input)
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PEDL9201-03 Semiconductor 6. Number of display digits set (writes the number of display digits to the display digit register) The number of display digits set can display 9 to 24 digits using 4-bit data. At the time power is turned on or a RESET signal is input, the display digit register value is "0". Always execute this instruction to change the number of digits before turning the dispaly on. [Command format]
LSB MSB
MSM9201-01
B0 B1 B2 B3 B4 B5 B6 B7 1st byte K0 K1 K2 K3 * 0 1 1 : selects the number of display digits set mode and specifies the number of digits value.
K0 (LSB) to K3 (MSB): number of display digits data (4 bits: 16 digits) [Relation between setup data and controlled COM]
HEX 0 1 2 3 4 5 6 7 K0 K1 K2 K3 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Number of digits of COM COM1-24 COM1-9 COM1-10 COM1-11 COM1-12 COM1-13 COM1-14 COM1-15 HEX 8 9 A B C D E F K0 K1 K2 K3 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Number of digits of COM COM1-16 COM1-17 COM1-18 COM1-19 COM1-20 COM1-21 COM1-22 COM1-23
The state at the time power is turned on or RESET signal is input
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PEDL9201-03 Semiconductor MSM9201-01
7. All display lights ON/OFF set (Turns all display lights ON or OFF) The all display lights ON mode is used primarily for display testing. The all display lights OFF mode is primarily used to prevent malfunction on power-up. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte L H
***
1
1
1
: selects all display lights ON or OFF mode.
[Set data and display state of SEG and AD]
L 0 1 0 1 H 0 0 1 1 Display state of SEG and AD All outputs maintain current states Sets all outputs to Low Sets all outputs to High Sets all outputs to High (All lights ON mode has priority.) (The state at the time power is applied or RESET is input)
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PEDL9201-03 Semiconductor MSM9201-01
Initial Setting Flowchart
Start Power is applied or RESET is input
Apply VDD
Apply VFL
All display lights OFF
Status of all outputs by RESET signal input
Specify number of display digits
Specify display duty Select a RAM to be used
DCRAM Data write mode (with address set)
Address is automatically incremented
CGRAM Data write mode (with address set)
Address is automatically incremented
ADRAM Data write mode (with address set)
Address is automatically incremented
DCRAM Character code DCRAM Is character code write ended?
YES
CGRAM Character code CGRAM Is character code write ended?
YES
ADRAM Character code ADRAM Is character code write ended?
YES
NO
NO
NO
YES
Another RAM to be set?
NO
Specify general output port status Release all display lights OFF mode Normal operation status (display ON)
End
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PEDL9201-03 Semiconductor MSM9201-01
APPLICATION CIRCUIT
Heater transformer 57-dot matrix fluorescent display tube
ANODE (SEGMENT) VDD R2 VDD C2 VDD C3 Microcontroller Output Port GND 4 RESET VDD, AD1-4 VDISP1-2 CS CP DA
ANODE GRID (SEGMENT) (DIGIT) 35 SEG1-35 24 COM1-24 R4 LED P1-2 4 NPN Tr GND VDD
MSM9201-01
GND VFL1-2
OSC0 C1
OSC1 R1
VFL
C4
GND ZD
R3
GND
Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of the constants R1, R2, R4, C1, and C2 to the power supply voltage used. 2. The VFL value depends on the fluorescent display tube used. Adjust the values of the constants R3 and ZD to the power supply voltage used.
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PEDL9201-03 Semiconductor Reference data The figure below shows the relationship between the VFL voltage and the output current of each driver. Take care that the total power consumption to be used does not exceed the power dissipation. MSM9201-01
VFL Voltage vs. Output Current of Each Driver -30 -25
Output Current (mA)
-20 -15 -10 -5 0 -10
COM1 to COM24 (Condition: VOH=VDISP-1.5 V)
AD1 to AD4 (Condition: VOH=VDISP-1.5 V) SEG1 to SEG35 (Condition: VOH=VDISP-1.5 V) -20 -30 -40 -50 -60 (V)
VFL Voltage (VDD-n)
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PEDL9201-03 Semiconductor MSM9201-01
MSM9201-01 ROM CODE
00000000B (00H) to 00001111B (0FH) are the CGRAM addresses.
MSB 0000 LSB 0000 RAM0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0001 RAM1
0010 RAM2
0011 RAM3
0100 RAM4
0101 RAM5
0110 RAM6
0111 RAM7
1000 RAM8
1001 RAM9
1010 RAMA
1011 RAMB
1100 RAMC
1101 RAMD
1110 RAME
1111
RAMF
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PEDL9201-03 Semiconductor MSM9201-01
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1414-0.65-K
.
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 0.85 TYP. 3/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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PEDL9201-03 Semiconductor MSM9201-01
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 1.27 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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PEDL9201-03 Semiconductor MSM9201-01
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
2.
3.
4.
5.
6.
7.
8.
9.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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