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| STD4NS25 N-CHANNEL 250V - 0.9 - 4A DPAK/IPAK MESH OVERLAYTM MOSFET TYPE STD4NS25 s s s s VDSS 250 V RDS(on) < 1.1 ID 4A TYPICAL RDS(on) = 0.9 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED ADD SUFFIX "T4" FOR ORDERING IN TAPE & REEL 3 1 DPAK TO-252 IPAK TO-251 1 3 2 DESCRIPTION Using the latest high voltage MESH OVERLAYTM process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company's proprietary edge termination structure, makes it suitable in coverters for lighting applications. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-DC CONVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (q) PTOT dv/dt (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 250 250 20 4 2.5 16 50 0.4 5 -65 to 150 150 (1) ISD 4A, di/dt300 A/s, VDD V (BR)DSS, TjTjMAX Unit V V V A A A W W/C V/ns C C (*)Pulse width limited by safe operating area February 2001 1/9 STD4NS25 THERMAL DATA Rthj-case Rthj-amb Rthc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 2.5 100 1.5 275 C/W C/W C/W C AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 4 120 Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 250 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) ID(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance On State Drain Current Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 2 A VDS > ID(on) x RDS(on)max, VGS = 10V 4 Min. 2 Typ. 3 0.9 Max. 4 1.1 Unit V A DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 2A VDS = 25V, f = 1 MHz, VGS = 0 Min. 1 Typ. 3.5 355 64 29.5 Max. Unit S pF pF pF 2/9 STD4NS25 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 125 V, ID = 2 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 200V, ID = 4 A, VGS = 10V Min. Typ. 12 18 19 3.2 7.5 27 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(Voff) tf tr(Voff) tf tc Parameter Turn-off- Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 125V, ID = 2 A, RG = 4.7, VGS = 10V (see test circuit, Figure 3) Vclamp = 200V, ID = 4 A, RG = 4.7, VGS = 10V (see test circuit, Figure 5) Min. Typ. 70 10.5 13 10 21.5 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 4 A, VGS = 0 ISD = 4 A, di/dt = 100A/s VDD = 30V, Tj = 150C (see test circuit, Figure 5) 124 0.5 7.2 Test Conditions Min. Typ. Max. 4 16 1.5 Unit A A V ns C A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/9 STD4NS25 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STD4NS25 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STD4NS25 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STD4NS25 TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0o 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 0.8 1.00 8o 0.024 0o TYP. MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 0.039 0o inch TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 DIM. P032P_B 7/9 STD4NS25 TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H A C C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 8/9 STD4NS25 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9 |
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