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ST18-AU1
SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
PRELIMINARY DATA
FEATURES
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Single chip multi-function audio decoder able to decompress DOLBY AC-3, MPEG-1 and MPEG-2 audio streams. Maximum 5.1 channel DOLBY AC-3 decoding to 2 channel mixed down output with DOLBY surround compatible or karaoke capable option. Variable bit rate MPEG-1 layer II audio decoding, and MPEG-2 multi-channel audio decoding for karaoke capable application. Input data rates
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Interrupt controller
DMA controller
Emulation unit and TAP
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up to 448 Kbits/s for AC-3 decoder up to 912 Kbits/s for MPEG-1 or MPEG-2 audio decoder
Clocks and timers D950 DSP core I2C Host interface
24K Data memory 16K Program memory
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Supports up to 8 channel DVD linear PCM input at max rate of 6.144 Mbits/s down-mixing and/ or sub-sampling to 2 to 6 channels. Accepts MPEG-1 or DVD/MPEG-2 PES input packets. Programmable D950 core System time clock provides A/V synchronization and PTS packet extraction. Automatic error concealment on CRC or synchronization error. 6 channel PCM audio output at 16/18/20/24 bit. Sampling rate of 32/44.1/48/96 kHz. Two on-chip PLLs providing full circuit operation with only one external 27 MHz clock. I2C interface for host control Multi-format i2S serial data input port and decoded audio PCM output port. IEC-958 (S/PDIF) formatter and transmitter for DOLBY AC-3, MPEG audio bit stream, or audio PCM. Dedicated hardware for emulation and test, IEEE 1149.1 (JTAG). 3.3V power supply, I/O's 5V tolerant, 0.35M HCMOS6 technology. 160 pin PQFP package
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Bus switch unit
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2 Input serial interface
IEC-958 (S/PDIF) output
3 Output serial interface
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APPLICATIONS
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Digital video disc (DVD) player Digital TV (DBS/DVB) receiver PC multimedia Consumer digital audio
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February 98
42 1726 00
This is preliminary information on a product in development or undergoing evaluation. Details are subject to change without notice.
Table of Contents
1 2 3 4 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 4.2 5 5.1 5.2 6 HOST INTERFACE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 LIST OF HOST COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 INPUT SERIAL INTERFACE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 INPUT FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.1 6.1 6.2 7 8 9 Input FIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
INPUT SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
INPUT AND OUTPUT BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 INPUT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OUTPUT BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 7.1 8.1 9.1 9.2 Input and output buffer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OUTPUT SERIAL INTERFACE - PCM OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OUTPUT SERIAL INTERFACE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INTERRUPT CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.1 9.2.2 9.2.3 Address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Counting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DMA CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 IEC-958 TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 IEC-958 TRANSMITTER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11 MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 INTERNAL MEMORY RESOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2 I-MEMORY BUS EXTENSION - DIRECT AND THROUGH BSU . . . . . . . . . . . 47 11.3 X-MEMORY BUS EXTENSION - DIRECT AND THROUGH BSU . . . . . . . . . . . 47 11.4 Y-MEMORY BUS EXTENSION THROUGH BSU . . . . . . . . . . . . . . . . . . . . . . . 47 12 BUS SWITCH UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 BSU CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13 CLOCKS AND TIMERS UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Table of Contents
13.1.1 Audio clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2 CLOCKS AND TIMERS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14 JTAG IEEE 1149.1 TEST ACCESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15 EMULATION UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16 D950CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16.1 D950CORE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17 Y SPACE MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 CLOCKS AND TIMERS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.3 IEC-958 TRANSMITTER (S/PDIF OUTPUT) REGISTERS . . . . . . . . . . . . . . . . 63 17.4 PCM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.5 INPUT/OUTPUT BUFFER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17.6 SERIAL INPUT 1 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.7 SERIAL INPUT 0 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.8 HOST INTERFACE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.9 BUS SWITCH UNIT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.10 PLL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.11 DMA CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 17.12 INTERRUPT CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.13 D950 CORE CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.14 DATA AND PROGRAM MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.1 DC ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 18.3.1 Clocks electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 18.3.2 E-bus (I direct extension) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18.3.3 E-bus (X direct extension) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18.3.4 E-bus (I BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18.3.5 E-bus (X BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18.3.6 E-bus (Y BSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.3.7 D950 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.3.8 I2C Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18.3.9 PCM and SPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Table of Contents
18.3.10 I2S Data Input 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18.3.11 I2S Data Input 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19 ST18-AU1 PACKAGE SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19.1 ST18-AU1 PACKAGE PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19.2 160 PIN PQFP PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20 DEVICE ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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ST18-AU1
1
INTRODUCTION
The ST18-AU1 is a single-chip multi-function audio processor for Dolby AC-3, MPEG-1/ MPEG-2 Layer-I/II audio encoded bitstreams, and DVD Linear PCM. It is capable of decoding up to 5.1 channels of input Dolby AC-3 or MPEG-2 multi-channel encoded audio, and down mixing to 2 channels of PCM output audio. Maximum input data rates for Dolby AC-3 bitstream and MPEG-2 audio bitstream are 448 Kbits/s and 912 Kbits/s respectively. It also supports up to 8 channel linear PCM input with by-pass, down-sampling, and down-mixing function. The linear PCM multi-channel input modes available are: * * * * * * * 48 kHz/16-bit up to 8 ch @ max 6.144 Mbps 48 kHz/20-bit up to 6ch @ max 5.760 Mbps 48 kHz/24-bit up to 5ch @ max 5.760 Mbps 96 kHz/16-bit up to 4ch @ max 6.144 Mbps 96 kHz/20-bit up to 3ch @ max 5.760 Mbps 96 kHz/24-bit up to 2ch @ max 4.608 Mbps 44.1 kHz/16-bit 2ch (CD-DA).
The input bitstream is taken from the multi-format serial input, and decoded according to the selected MPEG-1, MPEG-2 (in the case of Karaoke capable mode), AC-3 decoder or Linear PCM processor. A Packet Demux de-multiplexes the input if it is MPEG-1 or DVD/MPEG-2 PES packetized. For an input bitstream with more than 2 encoded audio channels, the decoded channels are mixed down to 2 channels with the Dolby Surround compatible or karaoke capable option, and outputted through a multi-format serial output port. The input AC3, MPEG bitstream, or decoded PCM can be outputted through an IEC-958 (S/PDIF) Formatter/Transmitter. The AC-3 or MPEG S/PDIF output bitstream is delayed and synchronized with the output decoded PCM. The Karaoke Capable mode defined in Dolby AC-3 or DVD to allow the multi-channel audio stream to convey channels designed as L, R (2-ch stereo music), M (guide melody), and V1, V2 (one or two vocal/supplementary tracks) are supported. This Karaoke capable decoder allows the user to choose to have the decoder reproduce any of the guide melody and vocal/ supplementary channels. Centre and surround mix levels either controlled by the user or within the bitstream are used to down mix the M channel and the V1, V2 channels respectively. The selectable Linear PCM Processor functions are: * * * down-mixing to 2 channels, down-sampling for 96kHz to 48kHz, noise shaped quantization for 24-bits or 20-bits to 16-bits.
Depending on the application, the decoded PCM audio output is selectable to be 16, 18, 20 or 24 bits, and the sampling rates of the PCM output are 32 kHz, 44.1 kHz, 48 kHz or 96 kHz. External A/V synchronization can be assisted by the System Time Clock (STC) within the Timer and the PTS extracted from the packetized input. A serial I2C interface to host
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ST18-AU1 microcontroller is provided to allow ST18-AU1 operation control, bitstream information and internal status access. A typical DVD back-end system configuration is shown in Figure 1.1. Figure 1.1 Typical DVD back-end system configuration
DRAM
Video bitstream Control Compressed system input bitstreams
MPEG-2 video decoder
Video encoder
Video output
System layer controller
27 MHz osc
I2C Control I2S Audio bitstream ST18-AU1 audio processor Audio DAC
L/Lt R/Rt
IEC-958 (S/PDIF) AC-3/MPEG
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ST18-AU1
2
PIN DESCRIPTIONS
The following tables detail the ST18-AU1 pin set. There is one table for each group of pins. The tables detail the pin name, type and a short description of the pin function. Signal names have a bar above if they are active low, otherwise they are active high. Table 2.1
Pin name IDE0-15 IAE0-15 IRDE IWRE IBSE
Direct I bus extension (35 pins)
Type I/O O O O O Description Instruction data extension bus. Instruction address extension bus. I-extension bus read strobe. Active low. I-extension bus write strobe. Active low. I-extension bus strobe. Active low. Asserted at the beginning of I-bus read/ write cycle.
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ST18-AU1 Table 2.2
Pin name ED0-15 EA0-15 EIRD EIWR XBSE EYRD EYWR XRDE_EXRD
Direct X bus extension / Bus extension through bus switch unit (39 pins)
Type I/O O O O O O O O Description Bus switch unit (BSU) X/Y/I data extension bus. BSU X/Y/I address extension bus. BSU I-extension bus read strobe EIRD output. BSU I-extension bus write strobe EIWR output. X_extension bus data strobe (BSU not used). BSU Y-extension bus read strobe EYRD output. BSU Y-extension bus write strobe EYWR output. Multiplexed output. In direct X-bus extension mode (BSU not used): X-extension bus read strobe (XRDE). Active low when reading from external X-memory. In X extension through BSU mode: BSU X-extension bus read strobe (EXRD). Active low when reading from external memory (when bit I/M of XER register is `1': Intel mode). BSU extension bus data strobe (EDS). Active low when reading from or writing to external memory (when bit I/M of XER register is `0' Motorola mode). Multiplexed output. In direct X-bus extension mode (BSU not used): X-extension bus write strobe (XWRE). Active low when writing to external X-memory. In X extension through BSU mode: BSU X-extension bus write strobe (EXWR). Active low when writing to external memory (when bit I/M of XER register is `1': Intel mode). Extension bus read /write signal (ERD_WR). Low during write cycle, otherwise high (when bit I/M of XER register is `0': Motorola mode).
XWRE_EXWR
O
Table 2.3
Pin name P0-7
General purpose parallel port (8 pins)
Type I/O Description Parallel port I/O. Each pin can be programmed as input or output. On reset, all pins are inputs.
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ST18-AU1 Table 2.4
Pin name EXTAL0 XTAL0 EXTAL1 XTAL1 CLK0 CLK0_MODE
Clocks (13 pins)
Type I O I O I I Description Oscillator0 input. DSP PLL. Oscillator0 output. Nominal oscillator frequency is 27 MHz. Oscillator1 input. Audio PLL Oscillator1 output. Nominal oscillator frequency is 27 MHz. Direct clock input for D950 core. Clock0 mode select input. When low, select output of DSP PLL for DSP Clock In When high, select CLK0 (bypass DSP PLL) for DSP Clock In Direct audio clock input. Clock1 mode select input. When low, select output of audio PLL for audio clock When high, select CLK1 (bypass audio PLL) for DSP Clock In PLL mode select input When low, select oscillator 1 for audio PLL When high, select oscillator 0 for audio PLL Output clock (at input clock/2 frequency). Instruction cycle. Asserted high for 1 CLKOUT cycle at the beginning of instruction cycle. External audio clock/audio clock prescaler output SCLK mode select input When low, SCLK = output (internal audio master clock from clock prescaler) When high, SCLK = input (external audio master clock)
CLK1 CLK1_MODE
I I
PLL_MODE
I
CLKOUT INCYCLE SCLK MCLK_MODE
O O I/O I
Table 2.5
Pin name HDA HCL HSAS
I2C Host interface (3 pins)
Type I/O /O I Description I2C Data input/output (open drain output). I2C Clock input/output (open drain output). Slave address select
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ST18-AU1 Table 2.6
Pin name DIN0 CLKDIN0 WSDIN0 DREQ0
Data input 0 (4 pins)
Type I I/O I/O O Description Serial data input Data input clock Input in slave mode, output in master mode. Data input word select Input in slave mode, output in master mode. Request for data input. Active low.
Table 2.7
Pin name DIN1 CLKDIN1 WSDIN1
Data input 1 (3 pins)
Type I I O Description Serial data input Data input clock Input in slave mode, output in master mode. Data input word select Input in slave mode, output in master mode.
Table 2.8
Pin name PCM_OUT0 PCM_OUT1 PCM_OUT2 SCLKPCM WSPCM
PCM output (5 pins)
Type O O O O O Description PCM data output 0 PCM data output 1 PCM data output 2 PCM output clock (common) PCM output word select (common)
Table 2.9
Pin name SPDIFOUT
IEC-958 transmitter (SPDIF) output (1 pin)
Type O Description S/PDIF signal
Table 2.10
Pin name IRQ
Interrupt controller interface (1 pin)
Type I Description Interrupt request. Active low. Maskable, programmable as falling edge or low level triggered (default is level triggered).
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ST18-AU1 Table 2.11
Pin name RESET LP MODE_RESET
D950-Core control (3 pins)
Type I I I Description Reset input. Active low. Initializes the 950-Core to the Reset state. Low power input. Active low. Mode selection for Reset. When low, forces reset address to 0x0000. When high, forces reset address to 0xFC00.
Table 2.12
Pin name ERQ IDLE
Emulation unit (4 pins)
Type I O Description Emulator halt request. Active low. Halts program execution and enters emulation mode. Output flag asserted high when the processor is halted due to an emulation halt request or a valid breakpoint condition.Asserted low when the processor is not Halted or during execution of an instruction under control of the emulator. Halt acknowledge. Active high. Asserted high when the processor is halted from an Emulator Halt request or when a valid Breakpoint condition is met. Snapshot. Active high. Asserted high when executing an instruction if Snapshot mode is enabled.
HALTACK
O
SNAP
O
Table 2.13
Pin name TDI TCK TMS TDO TRST
JTAG IEEE 1149.1 test access port(5 pins)
Type I I I O I Description Test data input. Test clock. Test mode select. Test data output. Test logic reset (also used for Emulator module). Active low.
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ST18-AU1
3
FUNCTIONAL OVERVIEW
A functional block diagram of the ST18-AU1 is shown in Figure 3.1. The modules that comprise the ST18-AU1 are outlined below and more detailed information is given in the following chapters of this datasheet. The interconnection of these blocks and all external interfaces are shown in the block diagram in Figure 3.2. Figure 3.1 Functional block diagram
System manager
Clock inputs Commands status
Timer
Linear PCM processor Down mix (surround) (or Karaoke modes)
Host interface Serial interface
MPEG2 decoder
Serial output
2 to 6 channel PCM output
Data input
Dolby AC-3 decoder
S/PDIF formatter
Packet demux
Delay
S/PDIF output (AC-3/MPEG or 2 ch PCM)
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ST18-AU1 Figure 3.2 ST18-AU1 block diagram
MODE_RESET P0-7 ST18-AU1 LP RESET VCC
GND
IRQ
Interrupt controller
DMA controller
TAP
9 IEEE 1149.1 JTAG interface
IT I-bus Clocks (13 pins) Clocks and timers D950 DSP core HCL HDA HSAS (I2C host interface) Y-bus Host interface Bus switch unit X-bus 16K Program memory
Direct I bus (35 pins)
16K X-data memory
Direct X / bus switch (39 pins)
DIN WSDIN CLKDIN DREQ
2 Input serial interfaces
3 Output serial interfaces
IEC-958 (S/PDIF) output
8K Y-data memory
PCM_OUT WSPCM SCLKPCM SPDIFOUT (AC-3/MPEG or PCM)
Host interface The I2C serial bus interface operated in slave mode enables connection to an external host processor. It receives operating commands, and returns host requested bitstream information and internal status.
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ST18-AU1 Input serial interface The ST18-AU1 has two input serial interfaces. The interfaces are multi-format serial interfaces for inputting audio bitstreams. Supported formats include delayed (I2S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and input clock, and master/slave mode. They provide the serial to parallel conversion and transfer the input data to the input buffer for further processing. Output serial interface The ST18-AU1 has three output serial interfaces. The output serial interfaces organize the PCM audio output into the required I2S serial format and generate all the DAC control signals. IEC-958 transmitter The IEC-958 transmitter accepts either the AC-3/MPEG bitstream or the decoded audio output PCM data, and formats the input in accordance with the IEC-958 (S/PDIF) specification for output. Interrupt controller (ITC) The interrupt controller (ITC) manages the interrupts from the clocks and timers unit, the host interface, and the external interrupt for the DSP core. The interrupt can be activated and programmed as edge or level triggered. DMA controller (DMAC) The DMA controller (DMAC) controls data transfer between data input/output and internal data buffers. D950 DSP Core The D950-Core is a general purpose programmable 16-bit fixed point Digital Signal Processor Core. The main blocks of the D950-Core include an arithmetic data calculation unit, a program control unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. The DSP core processes all host commands, performs input bitstream parsing, decompression, sample down-mixing and/or subsampling, as well as input and output control. Memory There is 8 Kword Y-data memory on Y space, 16 Kword X-data memory on X space and 16 Kword instruction memory on I space. Memory can be extended off-chip in one of three ways: * * * Direct I-bus extension. Direct X-bus extension. I, X and Y -bus extension through the bus switch unit.
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ST18-AU1 Bus switch unit The bus switch unit (BSU) is a bi-directional switcher. It switches the 3 internal buses (I, X and Y) to the external (E) bus. Clocks and timers unit The clocks and timers unit provides all the necessary clocks and timer controls for DSP processing, and all input/output operations. In addition, a 90 kHz System Time Clock (STC) is provided to assist audio/video synchronization in systems which include a video decoder. Emulation unit and JTAG IEEE 1149.1 test access port The emulation unit (EMU) performs functions dedicated to emulation and test through the external IEEE 1149.1 JTAG interface.
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ST18-AU1
4
HOST INTERFACE
The host interface is a fast I2C serial bus interface operated in slave mode. It provides connection to an external host processor. It receives operating commands, and returns host requested bitstream information and internal status.
4.1 Host interface registers
HSER: Host serial shift register This 16-bit shift register is used for serial data input and output. Data is shifted MSB first. It is not visible from the D950. HDR: Host data register This register is used for transfers between the HSER register and the D950. Figure 4.1 Host interface data exchange, receive mode
HCL
HDA
msb 6
5
4
3
2
1 lsb ack msb 6
5
4
3
2
1 lsb
byte 0
byte 1 .....
HSER
msb 16-bit lsb
HSER HDA
msb lsb
HDA
8-bit
HDR
byte 0
(msb) 16-bit
HDR
byte 1
(lsb)
byte 0
8-bit 8-bit
`0'
YD (16-bit words)
YD
(msb)
(lsb)
(8-bit words)
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ST18-AU1 Figure 4.2 Host interface data exchange, send mode
HCL
HDA
msb 6
5
4
3
2
1 lsb ack msb 6
5
4
3
2
1 lsb
byte 0
byte 1 .....
HSER HDA
msb lsb
HSER HDA
msb lsb
16-bit
8-bit
HDR
byte 0
(msb) 16-bit
HDR
byte 1
(lsb)
byte 0
8-bit
YD (16-bit words)
YD
(msb)
(8-bit words)
HCR: Host control register All bits are cleared on reset.
15 14 13 12 BERRIEN Function Host interface enable 0 host interface disabled 1 host interface enabled Word size 0 8-bit word 1 16-bit word Acknowledge generation disable 0 acknowledge enabled 1 acknowledge disabled 11 ACKFIEN 10 STOPIEN 9 8 HTIEN 7 6 5 4 3 2 ACKOFF 1 WS 0 HEN
Bit HEN
WS
ACKOFF
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ST18-AU1
HTIEN Transfer interrupt enable 0 transfer interrupt disabled 1 transfer interrupt enabled Stop interrupt enable 0 stop interrupt disabled 1 stop interrupt enabled Acknowledge fail interrupt 0 acknowledge fail interrupt disabled 1 acknowledge fail interrupt enabled Bus error interrupt 0 bus error interrupt disabled 1 bus error interrupt enabled RESERVED, read as 0.
STOPIEN
ACKFIEN
BERRIEN
-
HSR: Host status register All bits are reset when the register is read. The register can only be read by the D950.
15 14 13 12 BERR 11 ACKFAIL 10 9 8 7 6 5 4 3 2 1 0 STOP HDRR HDRW RQ RQ DAT- BUSY ADIR
Bit BUSY DATADIR
Function Set when Valid slave address detected, until Stop event or Restart event with invalid slave address. Data direction (valid when Busy bit is set). 0 receive data from host 1' send data to host HDR write request. Set when data is required by the host. Data needs to be written into the HDR register, this is reset when the HSR register is read. Host read request. Set when data has been sent by the host. Data needs to be read from the HDR register, this is reset when the HSR register is read. Stop. Set when a stop condition is detected. Acknowledge fail. Set when the host does not generate an acknowledge after one data byte has been sent. Bus error. Set when a misplaced start or stop condition is detected during transmission. RESERVED, read as 0.
HDRWRQ HDRRRQ STOP ACKFAIL BERR -
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ST18-AU1 HSAR: Host slave address register (Default value for slave address on reset: HSAS (7...2) = 101000).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 Bit HSA0 HSA1 HSA2 HSA3 HSA4 HSA5 HSA6 HSA7 Function Data direction (read only, written from HSER when Slave address is send by the host. Slave address bit 1 (read only, value of pin HSAS) Slave address bit 2 Slave address bit 3 Slave address bit 4 Slave address bit 5 Slave address bit 6 Slave address bit 7 RESERVED, read as 0.
4.2 List of host commands
A list of host commands is given below.
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ST18-AU1 Table 4.1
Mnemonic HostInputMode
Write commands
Opcode 00 Size (bits) 8 Command description and Parameter values Input mode (type of bitstream). AC3 (default) MPEG -1 MPEG-2 MPEG-2 with extension PCM by pass Linear PCM Input Stream Format ES (Default) DVD/PES
00 01 02 03 04 05 00 01
HostInputStrmFormat
01
8
HostOpmode
02
8
Operating Mode Idle (no decoding) (default) 00 Start (starts selected decoder) 01 Stop and flush (stops decoder and flush buffers) 02 Reset 03 SelfTest 04 Mute Off (default) On 00 01
HostMute
03
8
HostAudiStrmIdSel HostOutputChanConf
04 05
8 8
Audio stream ID select ID = 0 (default) to 7 (e.g. language selection)00 - 07 Output channel configuration. 2/0 Lt/Rt, Dolby surround compatible 1/0 C 2/0 L/R (default) 3/0 LCR 2/1 LRl 3/1 LCRl 2/2 LRlr 3/2 LCRlr Karaoke capable no vocal Karaoke capable vocal 1 Karaoke capable vocal 2 Karaoke capable vocal 1& 2 (default Karaoke) where X = do not care Dual mono reproduction mode Stereo (default) Left mono Right mono Mixed mono X0 X1 X2 X3 X4 X5 X6 X7 0X 1X 2X 3X
HostDualMonoReproMode
06
8
00 01 02 03
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ST18-AU1 Table 4.1
Mnemonic HostDynRngeCompMode
Write commands
Opcode 07 Size (bits) 8 Command description and Parameter values Dynamic Range Compression Mode Line-out Mode Custom Mode, Analog Dialnorm Custom Mode, Digital Dialnorm (default) RF Demod Mode
00 01 02 03
HostDynRngeCutScaleFac
08
16
Dynamic Range Compression Cut Scale Factor 0 to 0x7FFF (at `0' the compression is minimum, at 0x7fff the compression is maximum). (default: 0x 7fff) Dynamic Range Compression Boost Scale Factor 0 to 7FFF (at `0' the boost is minimum, at 0x7fff the boost is maximum). (default: 0x7fff) PCM Scale Factor 0 to 7FFF (default) Output LFE Present Off (default) On 00 01
HostDynRngeBstScaleFac
09
16
HostPcmScaleFac HostOutLfeOn
0A 0B
16 8
HostSpdifOutStrmFormat
0C
8
SPDIF Output Stream Format (the SPDIF output can send either the PCM decoded output, or the input encoded elementary stream) AC3/MPEG (default) 00 PCM 01 SPDIF Output Latency Delay between the decoder and the bitstream sent via the SPDIF output. The delay is expressed in multiples of 1/Fs, where Fs is the sample frequency. The delay is signed. 0xffff to 0x7ffff (default: 0) SPDIF SMPTE Frame Rate Code not indicated 24/1001 24 25 30/1001 (default) 30 50 60/1001 60 00 01 02 03 04 05 06 07 08
HostSpdifOutputLatency
0D
16
HostSpdifSmpteFrmRatCod
0E
16
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ST18-AU1 Table 4.1
Mnemonic HostLpcmMixAlpha0-7 HostLpcmMixBeta0-7
Write commands
Opcode 0F-16 17-1E Size (bits) 16 Command description and Parameter values Linear PCM Downmixing Coefficients In LPCM mode: Alphai is the coefficient to downmix the channel i into the Left channel. Betai is the downmixing coefficient for channel i into the Right channel. In Ac-3 Karaoke mode: the Alpha0 to Alpha5 are used to downmix respectively the Left, Melody, Right, Vocal1, Vocal2 channels. Beta0 to Beta5 is respectively used to downmix into the Right channel. Alpha0 to Alpha7, Beta0 to Beta7. Error Concealment Mode Mute (default) Disabled Skip Low Power Stand-by Mode Off (default) On Serial Input Control Defines the input format. default: I2S slave Serial Input Clock Division In master mode define the clock rate of the input.) Serial Output Control Defines the output format. default: I2s master 16 Serial Output Clock Division In master mode define the clock rate of the output. default: set for 44.1 Hz Audio Clock Selection All clocks derived from the 27MHz (default) 16 Audio Sample Frequency (Hz) 3200 44100 (default) 48000 Number of bits per sample 16 (default) 18 20 System Time Clock 11 10 00 01 16 18 20 00 01 02 00 01
HostErrorConcealMod
1F
8
HostLowPower
20
8
HostSerialInputCtrl
21
HostSerialInoutDiv HostSerialOutputCtrl
22 23
HostSerialOutputDiv
24
HostAudioClockSel HostSamplFreq
25 26
HostPcmNbBits
27
16
WriteStc
80
32
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ST18-AU1 Table 4.2
Mnemonic HostVersion HostI2cStatus
Read commands
Opcode 40 41 Size (bits) 16 8 Command description and parameter value Version number I2cStatus No error Error InputStatus No error Overflow Underflow OutputStatus No error Underflow Overflow Error decoder SPDIF Status No error Error OutputMode (Refer to output channel configuration) Audio Decoder Error Status No error Sync word Sample frequency Frame size Number of channels Decoder errors Crc Input Sampling Frequency Sampling frequency specified by the bitstream. For AC-3 fscod is returned. Input Data Rate Data rate specified by the bitstream. For AC-3 frmsizecod is returned. InputMultiChannelMode For AC-3 acmod is returned. Karaoke Bitstream Non Karaoke Karaoke 00 01 0 1 2 3 4 5...f 10 00 01 00 01 02 00 01 02 04 00 01
HostInputStatus
42
8
HostOutputStatus
43
8
HostSPDIFStatus
44
8
HostOpMode HostAudDecodErrorStatus
45 46
8 16
HostInputSamplFreq
47
8
HostInputDatRate
48
8
HostInputMultiChanMode HostKaraokCapBitstrm
49 4A
8 8
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ST18-AU1 Table 4.2
Mnemonic HostLfePresent
Read commands
Opcode 4B Size (bits) 8 Command description and parameter value Lfe Present Lfe not present Lfe present Copy Protected Not protected Protected Operating Mode Idle Synchronising Decoding Input Bitstream Status Idle Searching for PES sync word Searching for audio frame sync word System Time Clock Presentation Time Stamp
00 01 00 01 00 01 02 00 01 04
HodtCopyProtect
4C
8
HostOpModeOut
4D
8
HostInputBitstrmStatus
4E
8
STC PTS
81 82
32 32
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ST18-AU1
5
INPUT SERIAL INTERFACE
The ST18-AU1 has two input serial interfaces (DIN0 and DIN1). The interfaces are multiformat serial interfaces for inputting audio bitstreams. Supported formats include delayed (I2S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and input clock, and master/slave mode. They provide the serial to parallel conversion and transfer the input data to the input buffer for further processing. Data input interface 0 (DIN0) operates with an input FIFO which regulates the input data flow transferred to the input buffer. Data input interface 1 (DIN1) operates in a similar way to DIN0 but it does not have an associated input FIFO.
5.1 Input serial interface registers
Each input serial interface has the following set of registers. DIN0-1CR: Data in control register On reset, all bits are cleared.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 WS 1 0 DINEN Mas- Justi- De- WS_p CLK_ ter fied layed ol pol
Bit DINEN
Function Input interface enable 0 input interface disabled 1' input interface enabled Input word Bit1 0 0 1 1 size Bit 0 0 1 0 1 Input word size 16 bit 18 bit 20 bit 24 bit
WS
CLK_pol
Clock polarity 0 data and WS change on Clk falling edge 1 data and WS change on Clk rising edge Word size polarity 0 Left data word = WS low, Right data word = WS high 1 Left data word = WS high, Right data word = WS low Delay inserted before first bit of data following transition of WS. 0 first bit of data occurs on transition of WS 1 first bit of data occurs with 1 Clk cycle delay relative to transition of WS (I2S compatible).
WS_pol
Delayed
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ST18-AU1
Justified If number of Clk cycles between WS transitions is > n (= word size) 0 start justified: n bits read, starting from first bit: just after WS transition if Delayed ='0' with 1 clk cycle delay after WS transition if Delayed='1' 1 end justified, end bit beein last bit received: just before WS transition if Delayed ='0' just after WS transition if Delayed ='1' Master or slave operation 0 slave 1 master NOTE: this bit must be defined before the input interface enable (DINEN) bit is set. RESERVED, read as 0.
Master
-
DIN0-1DIV: Data in division register On reset, DIN0DIV value is set to 0.
15 Bit DINDIV 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DINDIV
Function MCLK_DIN divide factor 00000000' 1 00000001 2 ..... ...... 11111111 '510 `
fCLKDIN= fMCLK_DIN/2(DIN0DIV) if DIN0DIV /= `00000
RESERVED, read as 0.
DIN1DR: Data in output register This 16-bit register contains the serial interface input data and is read by the D950.
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ST18-AU1
5.2 Input FIFO
Associated with input serial interface 0 (DIN0) is a 32 byte input FIFO. It is used for temporary storage of incoming data during processing of packet headers or AC3/MPEG decoding. The input FIFO provides the following: * * * transfer of data to the input buffer on a word basis packet header processing when operating on PES detection of FIFO overflow and FIFO filled to a predefined level
5.2.1 Input FIFO registers
FIFOCR: Input FIFO control register On reset, all bits are cleared. The FIFO is cleared and the formatter is set to the `empty' state.
15 14 13 12 CLR_Fo rm 11 10 DIN0_IE N 9 8 DREQ_ SEL 7 6 5 4 3 2 1 0 FIFO_level DMA_ DREQ mod _EN
Bit DREQ_EN
Function DREQ enable 0 DREQ= 0 1 DREQ set according to FIFO threshold/full level DMA mode 0 DMA request always enabled 1 DMA request enabled only when PDC not equal to 0 (PES processing) FIFO threshold level (MSB=7, LSB=3). Set FIFO filling level for IRQ/DREQ management. DREQ signal settings (if DREQ_EN = 1) 0 DREQ is asserted high when FIFO threshold is reached 1 DREQ is asserted high when FIFO is full (if DREQ_EN=1) DIN0 interrupt enable 0 interrupt disabled 1' interrupt enabled (when FIFO_THS = 1) Set formatter empty (active only at write time of FIFOCR) RESERVED, read as 0.
DMA_mod
FIFO_level DREQ_SEL
DIN0_IEN
CLR_Form -
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ST18-AU1 FIFOSR: Input FIFO status register FIFO_FULL and FIFO_THR are cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Form_e PDC_N FIFO_T FIFO_ FIFO_F mpty ULL HR EMPTY ULL Function FIFO full: set and reset by hardware FIFO empty: set and reset by hardware FIFO threshold: set and reset by hardware Set when PDC = 0, otherwise reset Set when formatter empty, otherwise reset RESERVED, read as 0.
Bit FIFO_FULL FIFO_EMPTY FIFO_THR PDC_NULL Form_empty -
FIFO_out: FIFO output data register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Bit Data Function Data (MSB=15, LSB=8) RESERVED, read as 0.
FORM_out: Formatter output data register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataH Bit Data L Data H Function Data least significant byte Data most significant byte DataL
PDCR: Packet data count register Cleared on reset.
15 Bit PDC 14 13 12 11 10 9 8 7 6 5 PDC 4 3 2 1 0
Function Packet data count value in bytes. Maximum count value is 2047. RESERVED, read as 0.
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ST18-AU1
6
INPUT AND OUTPUT BUFFERS
6.1 Input buffer
The input buffer is single port memory mapped on the Y space. Taking into account the requirements for AC3 decoding and SPDIF transmitter, its size is 2048 words (16-bit). It Is software defined and may be dynamically sized. Buffer overflow detection is provided. The D950 reads the buffer using its circular addressing mode of operation. The DMA controller cycles through the buffer for write word by word, using a cycle stealing mechanism: 3 D950 cycles are needed for each 16-bit word transfer. When the SPDIF transmitter is enabled, another DMA channel is assigned to retrieving encoded samples.
6.2 Output buffer
The output buffer is single port memory mapped on the X space. For 2 channel and 6 channel PCM output, the size of the output buffer is software defined and can be dynamically sized. The D950 cycles through the buffer for write by using its circular addressing mode of operation. The DMA controller cycles through the buffer for read of one sample at a time (2 or 3 words, depending on samples format), using a cycle stealing mechanism. In 2 channel output mode, one DMA channel is used. In 6 channel output mode, three DMA channels are used. The DMA channel used must operate on "Level" mode. Buffer underflow detection can be performed using on-chip dedicated resources.
6.2.1 Input and output buffer registers
BUFCR: Buffer control register All bits are cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UDF_OUT OVF_INB BUF_IEN UF_IEN UDF_ OVF_IN EN_B mod BUF UF
Bit EN_BUF OVF_INBUF
Function Enable input/output buffer logic Input buffer overflow 0 INBUFOVF= `0' 1 INBUFOVF=INBUF_FULL
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ST18-AU1
UDF_mod Output buffer underflow 0 OUTBUFUDF= `0' 1 OUTUFUDF=OUTBUF_EMPTY Input buffer overflow interrupt enable 0 disable 1 enable Output buffer underflow interrupt enable 0 disable 1 enable RESERVED, Read as 0.
OVF_INBUF_IEN
UDF_OUTBUF_IEN
-
BUFSR: Buffer status register All bits are cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUTBUF INBUF_F _EMPTY ULL
Bit INBUF_FULL OUTBUF_EMPTY -
Function Input buffer full. Set and reset by hardware. Output buffer empty. Set and reset by hardware. RESERVED, Read as 0.
INBUFRAR:Input buffer read address register This register is not initialized on Reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RADD Bit RADD Function Reference address for Compare
OUTBUFWAR: Output buffer write address register This register is not initialized on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WADD Bit WADD Function Reference address for Compare.
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ST18-AU1
7
OUTPUT SERIAL INTERFACE - PCM OUTPUT
The output serial interface organizes the PCM audio output into the required I2S serial format and generates all the DAC control signals. The PCM output interface can be programmed to meet various data formats and modes of operation. The following parameters can be configured: word size, clock polarity, WS polarity, delayed/non-delayed, start/end justified. They are defined by the content of the control register PCMCR and are described below.
7.1 Output serial interface registers
PCMPRx0-x2 (x = 0, 1, 2): Data in parallel registers The 9 PCMPR registers are 16-bit PCM parallel registers used for temporary storage of output data. * * For 16-bit format, only the PCMPRx0 and PCMPRx1 registers are used respectively for channel 2 (right) and channel 1 (left). For formats of greater than 16-bits, the PCMPRx2 registers are used for the LSB:
* * channel 2 LSB on bits 7 to 0, left justified. channel 1 LSB on bits 15 to 8, left justified.
Figure 7.1
t
PCMPR register example for 18-bit data words Bit15 Bit8 Bit7 Bit0
ch2 ..... 2
PCMPR00
ch2 17 16.........
PCMPR01
ch1 17 16.........
ch1 ..... ..2
PCMPR02
ch1 10
unused
ch2 10
unused
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ST18-AU1 PCMCR: Data in control register All bits are cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 WS 1 0 PCMEN Mute play mute PCM Mode _en _ord Function PCM output enable 0 disable 1 enable Output word size bit 1 bit 0 0 0 0 1 1 0 1 1 Clock pol 0 1 word size 16 bit 18 bit 20 bit 24 bit Justi- De- WS_p CLK_ fied layed ol pol
Bit PCMEN
WS
CLK_pol
data and WS change on SCLKPCM falling edge data and WS change on SCLKPCM rising edge
WS_pol
Word size pol 0 Left data word = WS low, Right data word = WS high 1 Left data word = WS high, Right data word = WS low first bit of data occurs on transition of WS first bit of data occurs with 1 SCLKPCM cycle delay relative to transition of WS. (I2S compatible). Note: valid only for start justified mode, see bit 6. Delayed 0 1
Delayed
Justified
If number of SCLKPCM cycles between WS transitions is > N (=Word size) 0 start justified: N bits read, starting from first bit: just after WS transition if Delayed ='0' with 1 clk cycle delay after WS transition if Delayed ='1' 1 end justified, end bit in last bit received: just before WS transition if Delayed ='0' just after WS transition if Delayed ='1' Mode 0 1 2 channels 6 channels
Mode
PCM_ord
In 16-bit word-size, 0 MSB sent first 1 LSB sent first
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ST18-AU1
mute play Play 0 0 1 1 Mute 0 1 0 1
no DMA req. serial out = 0 SCLK, WS not running no DMA req. serial out = 0 SCLK, WS running DMA req. serial out = 'data' SCLK, WS running DMA req. serial out = 0 SCLK, WS running
Mute_en
Mute enable 0 disable mute input 1 enable mute input Bit mute is set by detection of falling edge on mute input It is cleared by writing `0' to it. RESERVED, read as 0.
-
PCMDIV On reset, the PCMDIV value is set to 0. If the SPDIF transmitter is used: * If output word size is greater than 16-bit, PCMDIV must be set to at least 1 (divide by 2) for correct generation of SPDIFCLK at twice the frequency of SCLKPCM. If output word size is 16-bit, PCMDIV must be set to at least 2 (divide by 4).
13 12 11 10 9 8 7 6 5 4 3 2 1 0
*
15 Bit PCMDIV 14 -
PCMDIV
Function PCMCLK divide factor 00000000 00000001 ... 11111111 RESERVED, read as 0. 1 2 ... 510
fPCMCLK= fMCLK_PCM/2(PCMDIV) if PCMDIV /= `00000
-
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ST18-AU1
8
INTERRUPT CONTROLLER
The interrupt controller (ITC) manages the interrupts from the clocks and timers unit, the host interface, and the external interrupt for the DSP core. The interrupt controller also manages input/output buffer overflow/underflow interrupts. The interrupt controller has the following features: * * * * 8 interrupt sources interrupts can be individually enabled by software priority level between different sources can be set by software interrupt can be activated and programmed as edge or level triggered.
The interrupt controller ITRQ inputs are connected to one external interrupt request (IRQ pin) and to internal peripheral requests, as detailed in the table below. Table 8.1 Interrupt assignments
Interrupt ITRQ0 ITRQ1 ITRQ2 ITRQ3 ITRQ4 ITRQ5 ITRQ6 ITRQ7 Assignment Host interface Input FIFO Input buffer Output buffer Clock timer IRQ SPDIF timer IRQ DMA controller connected to the external IRQ pin
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ST18-AU1 Figure 8.1 D950Core interrupt controller
AS-DSP
16
YD YA
16
IT ITACK EOI D950Core YWR YRD
IT ITACK EOI INTERRUPT
ITRQ0 ITRQ1 ITRQ2 ITRQ3 ITRQ4 ITRQ5 ITRQ6 ITRQ7
YWR CONTROLLER YRD PERIPHERAL
INCYCLE
CLK
RESET VR02020C
8.1 Interrupt controller registers
The interrupt controller interface is controlled by status and control registers mapped into the Y-memory space. Status registers are not write-protected. IVO0-7: Interrupt vector0-7 address registers The IVO0-7 registers contain the first address of the interrupt routine and are associated with the respective interrupt input ITRQ, see Table 8.1. The register content of the interrupt under service is provided on the YD bus during the cycle following the ITACK falling edge. (Address = 0020-0027, No reset value, Read/Write)
15 IVi15 14 IVi14 13 IVi13 12 IVi12 11 IVi11 10 9 8 7 6 5 4 3 2 1 0
IVi10 IVi9 IVi8 IVi7 IVi6 IVi5 IVi4 IVi3 IVi2 IVi1 IVi0
ICR: Interrupt control register The ICR register displays the current priority level and up to four stacked priority levels. (Address = 0028, Reset = 000Bh, Read/Write))
15 14
SPL4 (2:0)
13
12
11
SPL3 (2:0)
10
9
8
SPL2 (2:0)
7
6
5
SPL1 (2:0)
4
3
ES
2
1
CPL (2:0)
0
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ST18-AU1
Bit CPL ES Function Current priority level (-1, 0, 1, 2 or 3) (default is 011) Empty stack flag 0: stack is used 1: stack is not used (default) 3-bit 1st stacked priority level 3-bit 2nd stacked priority level 3-bit 3rd stacked priority level 3-bit 4th stacked priority level
SPL1 SPL2 SPL3 SPL4
The current priority levels available are shown below.
Priority level -1 0 1 2 3 Reserved Coding 111 000 001 010 011 100 - 110 Acceptable IT level priority 0,1,2,3 1,2,3 2,3 3
One interrupt request is acknowledged whenever its priority level (coded in the IPR register) is higher than the current priority level. In this case, the current priority level becomes the interrupt priority level and the previous current priority level is pushed onto the stack and displayed as stack priority level (SPL)1. The process is repeated over a range of four interrupt requests and the four previous current stack priority levels are displayed on SPL1, SPL2, SPL3 and SPL4. If less than four interrupts are pushed onto the stack, the unused SPL words are set to `000'. At the end of the interrupt routine, the priority levels are popped from the stack. The empty stack (ES) flag is used to indicate whether the stack is used or not. The ISP word of the ISP register indicates the depth of the stack (see below).
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ST18-AU1 Figure 8.2 ICR and ISPR Operation
INTERRUPT LEVEL 2 INTERRUPT LEVEL 3
PROGRAM IT2
PROGRAM IT2 IT3
PROGRAM IT3
ICR SPL4 SPL3 SPL2 SPL1 ES CPL X ISPR X X X 1 -1 ISP 0 SPL4 SPL3 SPL2 SPL1 ES CPL X X X -1 0 2 ISP 1 SPL4 SPL3 SPL2 SPL1 ES CPL X X -1 2 0 3 ISP 2 VR02020D
IMR: Interrupt mask/sensitivity register (Address = 0029, Reset = 5555h, Read/Write))
15 IS7 Bit IM 14 IM7 13 IS6 12 IM6 11 IS5 10 IM5 9 IS4 8 IM4 7 IS3 6 IM3 5 IS2 4 IM2 3 IS1 2 IM1 1 IS0 0 IM0
Function Interrupt mask 0: Interrupt is not masked 1: Interrupt is masked (default) Sensitivity 0: ITRQ is active on a low level (default) 1: ITRQ is active on a falling edge
IS
Each interrupt input ITRQ0-7 can be masked individually when the corresponding IM0-7 bit is set. In this case any activity on the ITRQ0-7 pin is ignored. All IM bits are set during DSP reset. ITRQ0-7 is active either on a low level when IS0-7 is low (by default on reset) or on a falling edge when IS0-7 is high. When ITRQ0-7 is active on a low level, it must stay low until the ITACK falling edge is sampled. Note, edge sensitive mode of operation must be set for all internal interrupt sources.
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ST18-AU1 IPR: Interrupt priority register (Address = 002A, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP7(1:0) Bit IP IP6(1:0) Function Interrupt priority level (0, 1, 2 or 3) (default is 0) IP5(1:0) IP4(1:0) IP3(1:0) IP2(1:0) IP1(1:0) IP0(1:0)
The IPR register contains the priority level of each ITRQ0-7 interrupt input. IP0-7 priority level is coded using two bits. The different values of IP are 0, 1, 2, 3 (0 lowest priority, 3 highest priority). When two ITRQ with the same priority level are requesting during the same cycle, the first acknowledged interrupt is the one corresponding to the lowest number (for example, ITRQ0 acknowledged prior to ITRQ3). ISPR: Interrupt stack pointer register (Address = 002B, Reset = 0000h, Read/Write)
15 Bit ISPR Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ISP(2:0) 0
Function Number of stacked priority levels (0, 1, 2 or 3) '-' is RESERVED (read: 0, write: don't care)
ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the SPLi/CPL values are modified. So the ICR register content is no longer significant but the interrupt routine procedure is not affected. After reset, ISPR default value is 0 ISR: Interrupt status register (Address = 002C, Reset = 0000h, Read/Write)
15 Bit IPE 14 13 Function Interrupt pending bit 0: Reset when interrupt request is acknowledged (default) 1: Set when interrupt request is recorded `-' is RESERVED (read: 0, write: don't care) 12 11 10 9 8 7 6 5 4 3 2 1 0 IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0
Note:
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ST18-AU1 An interrupt pending (IPE) bit is associated with each interrupt input. IPE is set when the interrupt request is recorded and is reset when the interrupt request is acknowledged (ITACK falling edge). When the user does not want to acknowledge any of the pending interrupt requests, the IPE flag of the CCR register must first be reset and then the ISR register set to "0000". When only some pending interrupt requests need to be acknowledged, the IPE bits of the other interrupt inputs must be reset. When the IPE bit is set by a direct register write an interrupt request will be generated irrespective of the state of the ITRQ pin. When the mask (IM) bit is set, the corresponding IPE bit is reset.
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ST18-AU1
9
DMA CONTROLLER
The DMA controller manages data transfer between memories and external peripherals and has the following features: * * * four independent DMA channels transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces) cycle stealing operation:
* * 3 cycles for a single data transfer (+1 cycle for transfers on I space) (n+2) cycles for an n-data block transfer (+1 cycle for transfers on I space)
*
each channel has:
* * 1 signal: interrupt request (ITR) 4x16 bit registers for block transfer facilities
*
fixed priority between the four channels (highest for channel 0, lowest for channel 3)
9.1 DMA operation
The four channels of D950 DMAC are used for: * * DMA3: transfer data from input FIFO to input buffer (Y space). As single words are transferred, it must be programmed edge sensitive. transfer data from output buffer to PCM output (X space).
* * DMA0 in 2-channel output mode DMA0, DMA1 and DMA2 in 6-channel output mode
they must be programmed level sensitive. * DMA1: transfer data from input buffer or output buffer to SPDIF interface. This channel will be programmed for transfer with X or Y memory according to the mode of operation of the SPDIF transmitter. It must be programmed level sensitive. (not compatible with 6-channel output mode.) * DMA2: transfer data from DATA Input1 to Y memory. As single words are transferred, it must be programmed edge sensitive. (not compatible with 6-channel output mode.)
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9.2 DMA registers
9.2.1 Address registers
Two 16-bit registers (unsigned) are dedicated per channel for transfer address: * * DIA0-3: initial address. This register contains the initial address of the selected address bus (see DBC-bit of DGC register). DCA0-3: current address. This register contains the value to be transferred to the selected address bus (see DBC-bit of DGC register) during the next transfer. The different DCA values are:
DAI X 0 1 1 1 DLA X X 0 1 1 DCC X X X =0 =1 DCA(n+1) 0 DCA(n) DCA(n) + 1 DCA(n) + 1 DIA
Reset 1 0 0 0 0 Note:
See DAIC register for DAI and DLA definitions.
9.2.2 Counting registers
Two 16-bit registers (unsigned) per channel are dedicated for transfer count. For a transfer of an N data block, DIC and DCC registers have to be loaded with N-1. When DCC content is 0 (valid transfer count), it is loaded with DIC content for the next transfer. * * DIC0-3: initial count. This register contains the total number of transfers of the entire block. DCC0-3: current count. This register contains the remaining number of transfers required to fill the entire block. It is decremented after each transfer. The DCC values are:
Reset 1 0 0 DCC X =0 =1 DCA(n+1) 0 DCA(n) - 1 DIC
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ST18-AU1
9.2.3 Control registers
Three 16-bit control registers are dedicated to the DMA controller interface. These are the general control register, the address interrupt control register and the mask sensitivity control register. They are detailed below. DGC: General control register Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel 1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3). (Address = 0040, Reset = 0000h, Read/Write).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRW DBC DBC 3 1 0 Function
DRW DBC DBC 2 1 0
DRW DBC DBC 1 1 0
DRW DBC DBC 0 1 0
Bit
DBC1/DBC0 Bus choice for data transfer 00: X-bus (default) 01: Y-bus 10: I-bus 11: reserved DRWi Data transfer direction 0: Write access (default) 1: Read access
DAIC: Address/interrupt control register Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel 1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3). (Address = 0042, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAI3 DLA3 DIP3 DIE3 DAI2 DLA2 DIP2 DIE2 DAI1 DLA1 DIP1 DIE1 DAI0 DLA0 DIP0 DIE0 Bit DIEi Function Enable interrupt 0: Interrupt request output associated to channel i is masked (default) 1: Interrupt request output associated to channel i is not masked Interrupt pending 0: No pending interrupt on channel i (default) 1: Pending interrupt on channel i (enabled if DIP_ENA input is high)
DIPi
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DLAi: Load address 0: DCAi content incremented after each data transfer (default) 1: DCAi content loaded with DIA content if DCCi value is 0, or DCAi content incremented if DCCi value is not equal to 0 Address increment 0: DCAi content unchanged (default) 1: DCAi content modified according to DLAi state
DAIi
DMS: Mask sensitivity control register Two bits are dedicated to each DMA channel (bits 0 and 1 to channel 0, bits 4 and 5 to channel 1, bits 8 and 9 to channel 2, bits 12 and 13 to channel 3). (Address = 0041, Reset = x3333h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSE3 DMK3
DSE2 DMK2
DSE1 DMK1
DSE0 DMK0
Bit DMKi
DSEi
Function DMA mask 0: DMA channel not masked 1: DMA channel masked (default) DMA sensitivity 0: Low level 1: Falling edge (default)
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ST18-AU1
10 IEC-958 TRANSMITTER
The IEC-958 transmitter accepts either the AC-3/MPEG bitstream or the decoded audio output PCM data, and formats the input in accordance with the IEC-958 (S/PDIF) specification for output via the SPDIFOUT pin. For further information refer to the IEC-958 interface specification.
10.1 IEC-958 transmitter registers
CHANSTA1: Channel status register 1
Bit 0 1 Bit of C 0 1 Function 0 Consumer mode, fixed
Digital data 0 audio data, muted or pcm 1 compressed audio data Copyright indication 0 digital copy prohibited 1 digital copy permitted 000 (Reserved) Mode 0 00 (Fixed) Category code 1001100 for DVD (AC3/MPEG) 0 1 original/commercially pre-recorded no indication/1st generation or higher
2
2
3-5 6-7 8-14 15
3-5 6-7 8-14 Generation status
Note: write only register. CHANSTA2: Channel status register 2
Bit 0-7 8-11 Bit of C 16-23 24-27 Function 00000000 (Fixed) 0100 0000 1100 00 all 0, fixed Fs 48kHz Fs 44.1kHz Fs 32kHz clock precision fixed
12-13 14-15
28-29 30-191
Note: write only register.
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ST18-AU1 SPDIFCR: SPDIF Output control register
Bit 0 Name SPDIFen Function Enable 0 1 Word size bit 1 0 0 1 1 disabled enabled bit 0 0 1 0 1 word size 16 bit 18 bit 20 bit 24 bit
1-2
WS
3
X/Y
Select X/Y for data read 0 Y (input buffer) 1 X (output buffer) Validity bit 0 valid 1 defective RESERVED, written as 0.
4
V
5-15
Note: write only register. All bits of the SPDIFCR register are cleared on reset. SPDIFPR0-2: 3x 16-bit SPDIF parallel registers The SPDIFPR0-2 registers are 16 bit SPDIF parallel registers used for intermediate storage of data. They are write only registers.
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ST18-AU1
11 MEMORY
11.1 Internal memory resource
One 8 Kword and two 16 Kword single port memories are included on-chip: * * * Instruction memory on I space from address 0 to 16382 (16 K) X-Data memory on X space from address 0 to 16382 (16 K) Y-Data memory on Y space from address 256 to 8192
Note: the first 256 addresses of the Y space are reserved for the D950 memory-mapped registers and for on-chip memory mapped peripherals. Memory can be extended off-chip in one of two ways: 1: directly for I and X memory spaces 2: through the bus switch unit for all three memory spaces The specific details on the operation of the BSU are described separately in Chapter 12. Figure 11.1 Memory mapping Y-memory 64k FFFF 64k FFFF I-memory 64k
X-memory FFFF
External External External
3FFF Internal RAM 0000
16k 1FFF Internal RAM 00FF Registers 8k
3FFF Internal RAM 0000
16k
All addresses are hexadecimal External memory is accessed directly or through the bus switch
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11.2 I-memory bus extension - direct and through BSU
For direct bus extension for I-memory the internal program memory is used from address 0 to 16383 (16K). The BSU can be programmed to allow either direct extension or extension through the BSU for IA above 16383.
Note: Initial reset should occur with MODE_RESET = 1, because internal program RAM is not initialized.
11.3 X-memory bus extension - direct and through BSU
The internal program memory is used from address 0 to 16383 (16K). Direct bus extension or bus extension through the BSU is controlled by setting the X-bus related BSU registers.
11.4 Y-memory bus extension through BSU
The internal program memory is used from address 256 to 8192. Y-memory bus extension must be through the BSU. It is controlled by setting the Y-bus related BSU registers.
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ST18-AU1
12 BUS SWITCH UNIT
The bus switch unit (BSU) is a bi-directional switcher. It switches the 3 internal buses (I, X and Y) to the external (E) bus.
12.1 BSU control registers
The BSU is programmable via six control registers mapped in the Y-memory space. These define the type of memory used, internal to external boundary address crossing, exchange type (external direct or through the BSU) and software wait-states count. There are 2 registers per memory space, making it possible to define 2 sets of boundaries and wait state numbers. Figure 12.1 Default and user mapping examples
64K EXTE RNAL
64K EXTERNAL INTE RNAL1 63K 62K
VALUE 1 INTERNAL1
VALUE 1
INTERNAL 0 VALUE 0
VALUE 0 INTERNAL0
0 DEFA ULT MAPPING (RESET) USER MAPPING
0 (CAN CHANGE BY 1K STEP)
The BSU control registers include a reference address on bits 4 to 9, where the internal/ external memory boundary value is stored (see Figure 12.1), and software wait-states count on bits 0 to 3, allowing up to 16 wait-states. External addressing is recognized by comparing these address bits for each valid address from IA, XA and YA, to the reference address contained into the corresponding control register. If the address is greater or equal to the reference value, an external access proceeds.
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ST18-AU1 XER0/1: X-memory space control registers After reset, XER0/1 default values are 0x83EF/0x83FF
15 IM Bit W3:0 XA15:10 EN_X IM 14 EN_X 13 12 11 10 9 8 7 6 5 4 3 2 W2 1 W1 0 W0 XA15 XA14 XA13 XA12 XA11 XA10 W3
Function Wait state count (1 to 16) for off-chip access (X-memory space) X-memory space map for boundary on-chip or off-chip Enable for X-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) RESERVED. Read 0, write don't care.
-
YER0/1: Y-memory space control registers After reset, YER0/1 default values are 0x83EF/0x83FF
15 IM Bit W3:0 YA15:10 EN_Y IM 14 EN_Y 13 12 11 10 9 8 7 6 5 4 3 2 W2 1 W1 0 W0 YA15 YA14 YA13 YA12 YA11 YA10 W3
Function Wait state count (1 to 16) for off-chip access (Y-memory space) Y-memory space map for boundary on-chip or off-chip Enable for Y-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) RESERVED. Read 0, write don't care.
-
IER0/1: Instruction memory control registers After reset, IER0/1 default values are 0x83EF/0x83FF or 0xC3EF/0xC3FF (the EN_I value depends on the IDT_EN input value).
15 IM 14 EN_I 13 12 11 10 9 8 7 6 5 4 3 W3 2 W2 1 W1 0 W0 IA15 IA14 IA13 IA12 IA11 IA10
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Bit W3:0 IA15:10 EN_I IM Function Wait state count (1 to 16) for off-chip access (I-memory space) I-memory space map for boundary on-chip or off-chip Enable for I-space data exchanges Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) RESERVED. Read 0, write don't care.
-
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13 CLOCKS AND TIMERS UNIT
The clocks and timers unit provides all the necessary clocks and timer controls for DSP processing, and all input/output operations. In addition, a 90 kHz System Time Clock (STC) is provided to assist audio/video synchronization in systems which include a video decoder.
13.1 Operation
13.1.1 Audio clock prescaler
* inputs
* * AUDIOCLK: output of Audio Master clock PLL MCLK_MODE: select internal or external Audio System Clock: (If bit CLK_sel1 of register PSCTR='0') 0 = internal 1 = external
*
outputs
* * MCLK_PCM to PCM Output interface MCLK_DIN to Data Input interface
*
input/output
* SCLK
The programmable prescaler and clock dividers of Data Input and PCM Output interfaces are used for the generation of data bit clocks. The prescaler divide range is 1 to 510. It is defined by the content of the PSCTR register. Its output SCLKINT is a 50% duty cycle signal.
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13.2 Clocks and timers registers
PSCTR register)
15 14 13 12 11 10 9 CLK_sel 2 8 CLK_sel 1 7 6 5 4 3 2 1 0
SCLKINTDIV
Bit SCLKINTDIV
Function SCLKINTDIV prescaler divide factor 00000000 1 00000001 2 ... ... 11111111 510
fSCLKINT= fpll2/2(SCLKINTDIV) if SCLKINTDIV /= 00000000
CLK_sel1 PCM output clock select: 0 Hardware (MCLK_MODE pin) 1 Software (according to bit 9) PCM Output Clock select: 0 MCLK_PCM= output of prescaler: SCLK is system clock output 1 MCLK_PCM= SCLK: SCLK is system clock input RESERVED, read as 0.
CLK_sel2
-
STC: system time clock registers * * input = EXTAL1 (27 MHz) output = STC
A Prescaler divides by 300 the master clock and generates the input clock at 90 KHz for STC. The 90 KHz clock is synchronized to the D950 instruction clock. STC is a 32-bit counter incremented at each 90 KHz clock pulse. It can be initialized to any value and read by the D950. It is memory mapped as two registers, STCMTR and STCLTR. STCMTR: 16-bit (MSB) STCLTR: 16 bit (LSB)
Note: When initializing the STC, the STCLTR register must be written before the STCLMTR. The effective loading of the STC occurs after STCMTR loading: When reading the STC, the STCLTR register must be read first. At that time, the current value of the STC MSB is stored in the STCMTR register, which can then be read.
No interrupts are associated with the STC.
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ST18-AU1 BLKCLKTR: block clock timer register * * input = FS (Samples Frequency) output = BLKCLK_IRQ
The BLKCLKTR register is a 16-bit decrementer. It can be initialized to any value by the D950. An interrupt request is generated when the BLKCLKTR register is decremented to 0 and it is reset to its initial value. SPDIF Timer register * * input = FS (Samples Frequency) output = SPDIF_IRQ
The SPDIFTR register is a 16-bit decrementer. It can be initialized to any value by the D950. An interrupt request is generated when it is decremented to 0 and reset to its initial value.
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ST18-AU1 Figure 13.1 Clocks and timers block diagram
D950 Y-bus Div 300 STC (32 bit counter)
EXTAL0 (27 MHz)
AUDIOCLK
PSC (8-bit prescaler).
(SCLKINT) MCLK_PCM mux
SCLK (in/out)
MCLK_DIN
MCLK_MODE
FS
PCM_OUT timer (16-bit).
BLKCLK_IRQ
SPDIF timer (16-bit).
SPDIF_IRQ
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ST18-AU1
14 JTAG IEEE 1149.1 TEST ACCESS PORT
The Test Access Port (TAP) conforms to IEEE standard 1149.1. The TAP consists of five pins: TMS, TCK, TDI, TDO and TRST. TDO can be overdriven to the power rails, and TCK can be stopped in either logic state. The instruction register is 8 bits long, with no parity, and the pattern "00000001" is loaded into the register during the Capture-IR state. There are three defined public instructions, see Table 14.1. All other instruction codes are reserved. Table 14.1 Instruction codes
Instruction IDCODE EMU BYPASS Selected register Identification D950 IOscan Bypass
Instruction code1) 04h 08h FFh
1)
MSB... LSB; LSB closest to TDO
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15 EMULATION UNIT
The emulation unit (EMU) performs functions dedicated to emulation and test through the external IEEE 1149.1 JTAG interface. Refer to Chapter 14 for details on the JTAG test access port. The emulation and test operations are controlled by the JTAG Test Access Port (TAP) and the emulator by means of dedicated control I/Os. Emulation mode can entered in one of two ways: * * Asserting ERQ input pin low. Meeting a valid breakpoint condition or executing an instruction in single step mode.
The PC board emulator is able to display the processor status (memories and registers) and restore the context. The emulation resources (see Figure 15.1) include: * * * * * Four breakpoint registers (BP0-3) which can be affected by Program or Data memory. Breakpoint counter (BPC). Program counter trace buffer (PCB) able to store the address of the 6 last executed instructions. Three control registers for breakpoint condition programming (BC0-1 and ECS). Control logic for instruction execution through the PC-board emulator control.
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ST18-AU1 Figure 15.1 Emulation block diagram
BP registers
Comparators
IA XA / YA XD / YD IA
RD/WR D950 TAP
Control Registers
Control Logic
PC trace
ERQ, IDLE, SNAP
The emulation controller interface (see Table 2.12 and Table 2.13 on page 11) includes pins of different types: * * ERQ, IDLE and SNAP are used by the emulator tools. HALTACK indicates that the processor is halted in emulation mode.
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16 D950Core
The D950Core is composed of three main units. * * * Data Calculation Unit (DCU) Address Calculation Unit (ACU) Program Control Unit (PCU)
For full details of the D950 DSP core refer to the D950Core datasheet (document number 421709). These units are organized in an HARVARD architecture around three bidirectional 16-bit buses, two for data and one for instruction. Each of these buses is dedicated to an unidirectional 16-bit address bus (XA/YA/IA). An 8-bit general purpose parallel port (P0-P7) can be configured (input or output). A test condition is attached to each bit to test external events. The D950Core is controlled through interface pins related to interrupt, low-power mode, reset and miscellaneous functions. Figure 16.1 D950Core block diagram
DATA
CALCULATION
OUTPUT CLKIN 6 16 16 16 16 3 16 16
UNIT YD-bus XD-bus
ADDRESS CALCULATION
XA-bus YA-bus
UNIT
PROGRAM
CONTROL UNIT
ID-bus IA-bus
11
CONTROL
8
PO/P7
14
TEST & EMULATION
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VDD VSS
PROGRAM MEMORY
DATA MEMORY
Control
CLOCKS
ST18-AU1 Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and peripherals registers are mapped in these address spaces. Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own control interface. Table 16.1 Data/instruction bus and corresponding address bus.
Data/instruction bus XD YD ID Bidirectional Bidirectional Bidirectional 16-bit 16-bit 16-bit XA YA IA Corresponding address bus Unidirectional Unidirectional Unidirectional 16-bit 16-bit 16-bit
Depending on the calculation mode, the D950Core DCU computes operands which can be considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit, including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included. The tables below illustrate the different types of word length and word format available for manipulation. Table 16.2 Summary of possible word lengths and formats
0 70 15 31 39 32 31 16 16 Format fractional integer signed unsigned signed unsigned 15 15 0 0 0 1-bit word 8-bit word 16-bit word signed / unsigned 32-bit word signed / unsigned 40-bit word signed / unsigned Minimum -1 0 - 32768 0 Maximum + 0.999969481 + 0.99996948 + 32767 + 65535
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16.1 D950Core registers
Register BX MX BY MY POR PIR PCDR PCSR PPR Function Modulo base address for X-memory space Modulo maximum address for X-memory space Modulo base address for Y-memory space Modulo maximum address for Y-memory space Port Output Register - 8LSB are significant, 8MSB are undefined when reading Port Input Register Port Control Direction Register Port Control Sensitivity Register Program Page Register
PCDR The Port Control Direction register defines the data direction of each port pin. After reset, PCDR default value is 0 (Port pins are configured as inputs)
15 Bit PiD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P7D P6D P5D P4D P3D P2D P1D P0D
Function Port pin direction 0: Input port pin (default) 1: Output port pin RESERVED (read: undefined, write: don't care)
Bits 8 - 15
PCSR The Port Control Sensitivity register defines sensitivity of each port pin. After reset, PCSR default value is 0 (Port pins are configured as level-sensitive).
15 Bit PiS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P7S P6S P5S P4S P3S P2S P1S P0S
Bits 8 - 15
Function Port pin sensitivity 0: Level sensitive (default) 1: Edge sensitive RESERVED (read: undefined, write: don't care)
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17 Y SPACE MEMORY MAPPING
17.1 Memory map
Figure 17.1 ST18-AU1 memory mapping
RESERVED Internal Y RAM RESERVED Clocks and timers RESERVED S/PDIF RESERVED PCM output RESERVED Input/output buffer RESERVED Serial input 1 Serial input 0 RESERVED Host interface RESERVED FFFF 2000 1FFF 0100 00FF 00B5 00B4 00B0 00AF 00A6 00A5 00A0 009F 009D 009C 0090 008F 0084 0083 0080 007F 007B 007A 0078 0076 0070 006F 0064 0063 0060 005F 0056
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Bus switch unit RESERVED PLL RESERVED DMA controller RESERVED Interrupt controller RESERVED Emulator peripheral D950 core 0055 0050 004F 004A 0049 0048 0047 0043 0042 0030 002F 002D 002C 0020 001F 0019 001F 0010 000F 0000
17.2 Clocks and timers registers
Address (Hex) 00B0 00B1 00B2 00B3 00B4 Register PSCTR STCLTR STCMTR BLKCLKTR SPDIFTR Description Prescaler System Time Clock LSB System Time Clock MSB Block Clock Timer SPDIF Timer
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17.3 IEC-958 transmitter (S/PDIF output) registers
Address (Hex) 00A0 00A1 00A2 00A3 00A4 00A5 Register SPDIFCR SPDIFPR0 SPDIFPR1 SPDIFPR2 CHANSTA1 CHANSTA2 Description SPDIF Control SPDIF Data0 SPDIF Data1 SPDIF Data2 Channel Status word1 Channel Status word2
17.4 PCM registers
Address (Hex) 0090 0091 0092 0093 0095 0096 0097 0099 009A 009B 009C Register PCMCR PCMPR00 PCMPR01 PCMPR02 PCMPR10 PCMPR11 PCMPR12 PCMPR20 PCMPR21 PCMPR22 PCMDIV Description PCM Output Control PCM Output Data 00 PCM Output Data 01 PCM Output Data 02 PCM Output Data 10 PCM Output Data 11 PCM Output Data 12 PCM Output Data 20 PCM Output Data 21 PCM Output Data 22 PCM Output Clock divide factor
17.5 Input/output buffer registers
Address (Hex) 0080 0081 0082 0083 Register BUFCR BUFSR INBUFRAR Description In/Out Buffer Control In/Out Buffer Status Input Buffer Read Address
OUTBUFWAR Output Buffer Write Address
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17.6 Serial input 1 registers
Address (Hex) Register 0078 0079 007A DIN1CR DIN1DIV DIN1DR Description Data In 1 Control Data In 1 Divide factor Data In 1 Output
17.7 Serial input 0 registers
Address (Hex) Register 0070 0071 0072 0073 0074 0075 0076 DIN0CR DIN0DIV FIFOCR FIFOSR FIFOOut FORM PDCR Description Data In 0 Control Data In 0 Divide factor FIFO Control FIFO Status FIFO output Formatter Packet Data Count
17.8 Host interface registers
Address (Hex) Register 0060 0061 0062 0063 HCR HSR HSAR HDR Description Host Interface Control Host Interface Status Slave Address Host Data Register
17.9 Bus switch unit registers
Address (Hex) Register 0055 0054 0053 0052 0051 0050 YER1 XER1 IER1 YER0 XER0 IER0 Description External Y-bus control register 1 External X-bus control register 1 External I-bus control register 1 External Y-bus control register 0 External X-bus control register 0 External I-bus control register 0
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17.10 PLL registers
Address (Hex) Register 0048 0049 D950_PllDiv Audio_Plldiv Description D950_Pll divide factor Audio_Pll divide factor
17.11 DMA controller registers
Address (Hex) Register 0042 0041 0040 003F 003E 003D 003C 003B 003A 0039 0038 0037 0036 0035 0034 0033 0032 0031 0030 DAIC DMS DGC DCC3 DCC2 DCC1 DCC0 DIC3 DIC2 DIC1 DIC0 DCA3 DCA2 DCA1 DCA0 DIA3 DIA2 DIA1 DIA0 Description DMA address / interrupt control DMA mask sensitivity DMA general control DMA channel 3 current count DMA channel 2 current count DMA channel 1 current count DMA channel 0 current count DMA channel 3 initial count DMA channel 2 initial count DMA channel 1 initial count DMA channel 0 initial count DMA channel 3 current address DMA channel 2 current address DMA channel 1 current address DMA channel 0 current address DMA channel 3 initial address DMA channel 2 initial address DMA channel 1initial address DMA channel 0 initial address
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17.12 Interrupt controller registers
002C 002B 002A 0029 0028 0027 0026 0025 0024 0023 0022 0021 0020 ISR ISPR IPR IMR ICR IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 Interrupt status register Interrupt stack pointer register Interrupt priority register Interrupt mask/sensitivity register Interrupt control register Interrupt vector 7 address Interrupt vector 6 address Interrupt vector 5 address Interrupt vector 4 address Interrupt vector 3 address Interrupt vector 2 address Interrupt vector 1 address Interrupt vector 0 address
17.13 D950 core control registers
Address (Hex) Register 0007 0006 0005 0004 0003 0002 0001 0000 PCSR PCDR PIR POR MY BY MX BX Description Port control sensitivity register Port control direction register Port input register Port output register Y-memory space modulo max address Y-memory space modulo base address X-memory space modulo max address X-memory space modulo base address
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17.14 Data and program memory mapping
X Memory mapping
address (Hex) 0000 to 3FFF Name Function On chip X RAM (16K words).
Y Memory mapping
address (Hex) 007F to 1FFF Name Function On chip Y RAM (7936 words). Addresses 00 to FF (256 words) reserved for D950 and peripherals memory mapped registers.
I Memory mapping
I address (Hex) 0000 to 3FFF Name Function On chip I RAM (16K words)
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18 ELECTRICAL SPECIFICATIONS
In the following tables TBD indicates `to be defined'.
18.1 DC Absolute maximum ratings
Table 18.1 DC absolute maximum ratings
Symbol VDD Vin Ta Tstg Parameter Power supply voltage Input voltage Operating temperature range Storage temperature range Value - 0.5 / 4 -0.5 / Vdd+0.5 0 / +70 -55 / +150 Unit V V
oC oC
18.2 DC Electrical characteristics
Table 18.2
Symbol VDD VIL VIH IIN VOL VOH IDD
DC electrical characteristics
Parameter Supply voltage Input low level Input high level Input current Output low level Output high level Operating current 2.4 180 Min 2.7 -0.3 2.0 Typ 3.3 Max 3.6 0.8 VDD+0.3v 10 0.4 Unit V V V A V V mA 1 1 Notes
Notes 1: Iload = 2mA
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3
ST18-AU1
18.3 AC characteristics
The following timings are based on simulations and may change when full characterisation is completed. Figure 18.1
2.7v 90% 1.5v 10% 0.3v timing reference points 90% 1.5v 10%
Input waveforms
r , f 2.5ns
r
f
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ST18-AU1 Figure 18.2 Output load circuit and waveform
~ IOL = 1mA
From output under test
Vref
CL = 50pF
IOH = 1mA
VOH 1.5v VOL timing reference points 1.5v
Table 18.3
VDD VDDmin VDDmax
AC measurement conditions - input only or output only pins
VIL 0.3v 0.3v VIH 2.7v 2.7v VOL 1.5V 1.5V VOH 1.5V 1.5V IOL 1mA 1mA IOH 1mA 1mA
70/87
ST18-AU1 Figure 18.3 Float load circuit and waveform
~ IOL = 8mA
From output under test
Vref
CL = 50pF
IOH = 8mA
VOH VOH - 0.15v Vref + 0.1V Vref - 0.1V VOL
Vref
timing reference points VOL - 0.15v
For timing purposes a pin is no longer floating when a 100mV change from Vref occurs, but begins to float when a 150mV change from the loaded VOH/VOL level occurs.
71/87
ST18-AU1
18.3.1 Clocks electrical characteristics
CLK0
t2 t3 t1 t4
CLKOUT
t6 t5
INCYCLE
CLK1
t8 t9 t7 t10
SCLK(out)
No t1 t2 t3 t4 t5 t6 t7 t8 t9 t9 t10 t10
Parameter CLKOUT rise time CLKOUT fall time CLKOUT high delay(1) CLKOUT low delay(1) INCYCLE high delay INCYCLE low delay SCLK out rise time SCLK out fall time SCLK out high delay(2) SCLK out high delay(3) SCLK out low delay(2) SCLK out low delay(3)
Min (ns)
Typ (ns) Max (ns)
7.05 6.95 0.55 T0-0.7
6.25 7.10 6.75 7.70
(1): CLK0_MODE=0 (Bypass PLL) (2): CLK1_MODE=0 (Bypass PLL),MCLK_MODE=0 (select internal generation from CLK1) No divide option set. (3):CLK1_MODE=0 (Bypass PLL),MCLK_MODE=0 (select internal generation from CLK1) Prescaler divide by 2
72/87
ST18-AU1
18.3.2 E-bus (I direct extension)
CLKOUT INCYCLE t17 IAE IBSE t13 IRDE t19 IDE(in) t15 IWRE t21 IDE(out) t22 t16 t20 t12 t11 t14 t18
No t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22
PARAMETER IBSE low delay IBSE high delay IRDE low delay IRDE high delay IWRE low delay IWRE high delay IAE valid delay IAE hold time IDE (in) setup time IDE (in) holdtime IDE (out) valid delay (Hi to Lo Z) IDE (out) valid delay (Lo to Hi Z)
Min (ns)
Typ (ns) 0.3 T0-1.4 T0/2-1.05 0.35 T0/2+0.9 0 1.6 1.1 5.45 -4.40 T0+3.80 -0.1
Max (ns)
73/87
ST18-AU1
18.3.3 E-bus (X direct extension)
CLKOUT INCYCLE t29 EA XBSE t24 t23 t25 XRDE_EXRD t31 ED (in) t27 XWRE_EXWR t33 ED (out) t34 t28 t32 t26 t30
No t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34
PARAMETER XBSE low delay XBSE high delay XRDE_EXRD low delay XRDE_EXRD high delay XWRE_EXWR low delay XWRE_EXWR high delay EA valid delay EA hold time ED (in) setup time ED (in) hold time ED (out) valid delay (Hi to Lo Z) ED (out) valid delay (Lo to Hi Z)
Min (ns)
Typ (ns) 0.25 T0+0.3 T0+2.5 0.65 T0+2.6 0.35 T0+3.95 3.30 7.50 -5.85 T0+3 0.3
Max (ns)
74/87
ST18-AU1
18.3.4 E-bus (I BSU)
CLKOUT INCYCLE t39 EA t40
t35 EIRD t41 ED (in) t37 EIWR t43 ED (out)
t36
t42 t38
t44
No t35 t36 t37 t38 t39 t40 t41 t42 t43 t44
PARAMETER EIRD low delay EIRD high delay EIWR low delay EIWR high delay EA valid delay EA hold time ED (in) setup time ED (in) hold time ED (out) valid delay (Hi to Lo Z) ED (out) valid delay (Lo to Hi Z)
Min (ns)
Typ (ns) 2.55 1.4 2.15 1.7 T0+4.15 T0+3.90 8.25 -6.55 2 1.95
Max (ns)
75/87
ST18-AU1
18.3.5 E-bus (X BSU)
CLKOUT INCYCLE t49 EA t50
t45 XRDE_EXRD t51 ED (in) t47 XWRE_EXWR t53 ED (out)
t46
t52 t48
t54
No t45 t46 t47 t48 t49 t50 t51 t52 t53 t54
PARAMETER XRDE_EXRD low delay XRDE_EXRD high delay XWRE_EXWR low delay XWRE_EXWR high delay EA valid delay EA hold time ED (in) setup time ED (in) hold time ED (out) valid delay (Hi to Lo Z) ED (out) valid delay (Lo to Hi Z)
Min (ns)
Typ (ns) 3.65 2 3.15 1.95 T0+4.65 T0+4.40 8.35 -7.15 4.85 1.55
Max (ns)
76/87
ST18-AU1
18.3.6 E-bus (Y BSU)
CLKOUT INCYCLE t59 EA t60
t55 EYRD t61 ED (in) t57 EYWR t63 ED (out)
t56
t62 t58
t64
No t55 t56 t57 t58 t59 t60 t61 t62 t63 t64
PARAMETER EYRD low delay EYRD high delay EYWR low delay EYWR high delay EA valid delay EA hold time ED (in) setup time ED (in) hold time ED (out) valid delay (Hi to Lo Z) ED (out) valid delay (Lo to Hi Z)
Min (ns)
Typ (ns) 2.85 1.4 2.85 1.4 T0+4.1 T0+4.05 9.2 -7.55 4.20 2.05
Max (ns)
77/87
ST18-AU1
18.3.7 D950 control
CLK0 t4 CLKOUT t3
INCYCLE t65 RESET t67 t68 t69 t70 t71 P(in) t73 t74 P(out) t75 t72 t66
IRQ
LP
No t65 t66 t67 t68 t69 t70 t71 t72 t73 t74 t75
PARAMETER RESET setup time RESET hold time IRQ setup time IRQ min. pulse duration,low LP setup time LP min. pulse duration,low P (in) setup time P (in) hold time P (in) min pulse duration,low (edge P (out ) low delay P (out ) high delay
Min (ns)
Typ (ns) 8.30 6 6.2 6.05 -5.85
Max (ns)
2.6 3.0
78/87
ST18-AU1
18.3.8 I2C Host interface
CLK0 2x T0 INCYCLE SCL (in) t76 HDA (in)
t77
HCL (in) t78 HDA (out) HDA (out) t79
HCL (in) t80 t81
No t76 t77 t78* t79** t80 t81
PARAMETER HDA (in) setup time vs SCLK HDA (in) hold time vs SCLK HDA (out) low delay min HDA (out) low delay max HDA (out) lo to Hi Z delay min HDA (out) lo to Hi Z delay max START Condition setup STOP Condition setup
Min (ns)
Typ (ns) 2xT0 + 1.1ns 0 2xT0 + 6.45ns 4xT0 + 6.45ns TBD TBD TBD TBD
Max (ns)
* = External R load to Vdd = ** Rise time defined by External Rload
79/87
ST18-AU1
18.3.9 PCM and SPDIF
CLK1 t9 SCLK t82 SCLKPCM t84 WSPCM t86 PCMOUT0/1/2 t88 SPDIFOUT t89 t87 t85 t83 t10
No t82* t83* t84 t85 t86 t87 t88 t89
PARAMETER SCLKPCM high delay SCLKPCM low delay WSPCM high delay WSPCM low delay PCMOUT0/1/2 high delay PCMOUT0/1/2 low delay SPDIFOUT high delay SPDIFOUT low delay
Min (ns)
Typ (ns) 10.3 10.4 11.4 11.30 10.65 10.60 11.4 11.3
Max (ns)
* SCLKPCM generated from CLK1, Prescaler divide by 2
80/87
ST18-AU1
18.3.10 I2S Data Input 0
CLKDIN0 WSDIN0 t92 t93 DIN0 t94 DREQ0 SLAVE MODE CLK1 t96 CLKDIN0 t98 WSDIN0 t100 t101 DIN0 t102 DREQ0 MASTER MODE No t90 t91 t92 t93 t94 t95* t96 t97 t98 t99 t100 t101 t102 PARAMETER WSDIN0 to CLKDIN0 setup time CLKDIN0 to WSDIN0 hold time DIN0 to CLKDIN0 setup time CLKDIN0 to DIN0 hold time CLKDIN0 to DREQ0 rise propagation time CLK0 rise to DREQ0 fall propagation time CLK1 rise to CLKDIN0 fall propagation time CLK1 rise to CLKDIN0 rise propagation time CLK1 rise to WSDIN0 fall propagation time CLK1 rise to WSDIN0 rise propagation time DIN0 to CLK1 rise setup time CLK1 rise to DIN0 hold time CLK1 rise to DREQ0 propagation time Min (ns) Typ (ns) -1.45 2.10 -2.95 3.45 7.05 12.90 9.70 9.90 11 10.95 -4.80 -5.40 10.90 Max (ns) t102 t102 t102 t100 t101 t99 t98 t99 t97 t97 t96 t95 t94 t95 t92 t93 t92 t93 t92 t93
t90 t91
t90t91
t90 t91
t90 t91
* For this time, CLKDIN0 is halted by DREQ0.
81/87
ST18-AU1
18.3.11 I2S Data Input 1
CLKDIN1 WSDIN1 t105 t106 DIN1 SLAVE MODE CLK1 t107 CLKDIN1 t109 WSDIN1 t111 t112 DIN1 MASTER MODE t111 t112 t110 t109 t110 t108 t108 t107 t105 t106 t105 t106 t105 t106
t103 t104
t103104 t
t103 t104
t103 t104
No t103 t104 t105 t106 t107 t108 t109 t110 t111 t112
PARAMETER WSDIN1 to CLKDIN1 setup time CLKDIN1 to WSDIN1 hold time DIN1 to CLKDIN1 setup time CLKDIN1 to DIN1 hold time CLK1 rise to CLKDIN1 fall propagation time CLK1 rise to CLKDIN1 rise propagation time CLK1 rise to WSDIN1 fall propagation time CLK1 rise to WSDIN1 rise propagation time DIN1 to CLK1 rise setup time CLK1 rise to DIN1 hold time
Min (ns)
Typ (ns) -1.6 1.4 -2.05 2.35 9.50 9.50 11.10 11.15 -4.25 4.56
Max (ns)
82/87
ST18-AU1
19 ST18-AU1 PACKAGE SPECIFICATIONS
19.1 ST18-AU1 package pinout
The ST18-AU1 is available in a 160 pin plastic quad flat pack (PQFP) package. Table 19.1
Pin name
GNDE VDDE IDE<15> IDE<14> IDE<13> IDE<12> IDE<11> IDE<10> IDE<9> IDE<8> IDE<7> IDE<6> IDE<5> IDE<4> IDE<3> IDE<2> IDE<1> GNDE VDDE VDD IDE<0> IAE<15> GND IAE<14> IAE<13> IAE<12> IAE<11> IAE<10> IAE<9> IAE<8> IAE<7> IAE<6>
ST18-AU1 package pinout
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name
VDD GND VDDE GNDE PCM_OUT0 PCM_OUT1 PCM_OUT2 WSPCM SCLKPCM SPDIFOUT IRDE IWRE GND IBSE INCYCLE CLKOUT VDD GND VDD GND MCLK_MODE CLK0 CLK1 CLK0_MODE CLK1_MODE PLL_MODE EXTAL0 VDD EXTAL1 XTAL0 XTAL1 XBSE
Pin no. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin name
VDDE GNDE EA<0> EA<1> EA_<2> EA<3> EA<4> EA<5> EA<6> EA<7> EA<8> EA<9> EA<10> VDDE GNDE EA<11> EA<12> EA<13> EA<14> EA<15> ED<0> ED<1> ED<2> ED<3> ED<4> VDDE GNDE ED<5> ED<6> ED<7> ED<8> ED<9>
Pin no. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
Pin name
GND VDD P<7> P<6> P<5> P<4> P<3> P<2> P<1> P<0> MODE_RESET TDI GND VDD IRQ LP SCLK HSAS HDA HCL DREQ0 CLKDIN1 CLKDIN0 WSDIN1 WSDIN0 DIN1 VDD GND DIN0 SNAP HALTACK IDLE
Pin no. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152
83/87
ST18-AU1
Pin name
IAE<5> IAE<4> IAE<3> IAE<2> IAE<1> IAE<0> GNDE VDDE
Pin no. 33 34 35 36 37 38 39 40
Pin name
XRDE_EXRD XWRE_EXWR EYWR EIWR EIRD EYRD VDD GND
Pin no. 73 74 75 76 77 78 79 80
Pin name
ED<10> ED<11> ED<12> ED<13> ED<14> ED<15> VDDE GNDE
Pin no. 113 114 115 115 117 118 119 120
Pin name
ERQ RESET TMS TDO TCK TRST GND VDD
Pin no. 153 154 155 156 157 158 159 160
19.2 160 pin PQFP package dimensions
Table 19.2 160 pin PQFP package dimensions
REF. A A1 A2 B c D D1 D3 e E E1 E3 L L1 k 31,20 28,00 25,35 0,65 31,20 28,00 25,35 0,80 1,60 0 7 0,65 0,95 30,95 27,90 31,45 28,10 3,42 0,25 3,17 0,22 0,13 30,95 27,90 3,67 0,38 0,23 31,45 28,10 TYP MIN MAX 4,07
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ST18-AU1 Figure 19.1 Package diagram
85/87
ST18-AU1
20 DEVICE ID
The identification code for the ST18-AU1 is #m52BD041, where m is a manufacturing revision number reserved by SGS-THOMSON.
bit 31 Mask rev reserved ST18 family Variant bit 0 SGS-THOMSON manufacturers id D 0 4 1
1)
0101001010111101000001000001 5 2 B
1)
Defined as 1 in IEEE 1149.1 standard.
21 ORDERING INFORMATION
Device ST18AU1X??S Package 160 pin plastic quad flat pack (PQFP)
For further information contact your local SGS-THOMSON sales office.
86/87
Notes
Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THO MSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THO MSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express writt en approval of SGS-THOMSON Microelectronics. (c)1997 SGS-THOMS ON Microelectronics - All rights reserved. SGS-THOMS ON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
87/87
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