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W83C43 KEYBOARD CONTROLLER
GENERAL DESCRIPTION
The W83C43 is a keyboard controller designed to provide the functions needed to interface a CPU to a keyboard or to a PS/2 mouse. The W83C43 can be used with IBM(R)-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will interrupt the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until acknowledge is received for the previous byte sent. This fast keyboard controller can improve the performance of IBM PC/AT(R) 386TM DX/SX and 486TM DX/SX machines and their compatibles. Hardwire methodology is used in this controller instead of software implementation, as in the traditional 8042 keyboard BIOS. With full hardware implementation, this enables the keyboard controller to respond instantly to all commands sent from the keyboard and PS/2 mouse to the CPU BIOS. The keyboard controller enables popular programs such as AutoCAD(R), Microsoft(R) WindowsTM 3.1, NOVELL , and other programs to run much faster.
(R)
FEATURES
* * * * * * * *
Supports IBM PC/AT 386 DX/SX and 486 DX/SX system designs Full hardwire design based on advanced VLSI CMOS technology Supports PS/2 Mouse 6 MHz to 12 MHz operating frequency Supports AT mode and PS/2 mode for different hardware configurations Automatically detects PS/2 mode or AT mode Much faster than traditional keyboard controller Packaged in 40-pin DIP or 44-pin PLCC
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Publication Release Date: January 1996 Revision A2
W83C43
PIN CONFIGURATIONS
40-pin DIP
T0 X1 X2 RESET Vcc CS GND RD A2 WR NC D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc T1 P27 (KDAT) P26 (KCLK) P25 (IEMP/MINT) P24 (KINT) P17 (KINH) P16 (DISP) P15 (JUMP) P14 (RAM) P13 P12 P11 P10 NC Vcc P23 (NC/MCLK) P22 (NC/MDAT) P21 (GA20) P20 (RC)
44-pin PLCC
/ R E VS cEX cT2 6 5 4
XT 10 3 2
V NcT Cc1
P 2 7
P 2 6
P 2 5
CS GND RD A2 WR NC NC D0 D1 D2 D3
7 8 9
10 11 12 13 14 15
1 44 43 42 41 40 39 38 37 36 35 34 33
P24 P17 P16 P15 P14 NC P13 P12 P11 P10 NC
32 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 D 4 D 5 DDGNPP 67 NC22 D 01 P 2 2 P 2 3 V c c
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W83C43
PIN DESCRIPTION
PIN NO.
(40-pin DIP) (44-pin PLCC)
I/O
NAME AT MODE
FUNCTION PS/2 MODE K/B Clock Input Crystal Clock I/P Crystal Clock I/P Chip Reset Optional + 5V Power Supply Chip Select Optional Ground Power I/O Read Connect to Address A2 I/O Write Reserved Data Bus D0-D7
1 2 3 4 5 6 7 8 9 10 11, 26 12, 13, 14, 15, 16, 17, 18, 19 20 21
2 3 4 5 6 7 8 9 10 11 1, 12, 13, 23, 29, 34 14, 15, 16, 17, 18, 19, 20, 21 22 24
I I I I I I I I I/O
T0 X1 X2
RESET
K/B Clock Input Crystal Clock I/P Crystal Clock I/P Chip Reset Optional +5V Power Supply Chip Select Optional Ground Power I/O Read Connect to Address A2 I/O Write Reserved Data Bus D0-D7
VCC
CS
GND
RD
A2
WR
NC D0-D7
O
GND P20
Ground Power Supply Bit 0 of Port2 ( RC : System Reset)
Ground Power Supply Bit 0 of Port2 ( RC : System Reset) Bit 1 of Port2 ( GA20 : GATE A20) Bit 2 of Port2 (MDAT: Mouse Data Output) Bit 3 of Port2 (MCLK: Mouse Clock Output) Optional + 5V Power Supply
22
25
O
P21
Bit 1 of Port2 ( GA20 : GATE A20)
23
26
I/O
P22
Bit 2 of Port2 (NC: User-defined I/O)
24
27
I/O
P23
Bit 3 of Port2 (NC: User-defined I/O)
25
28
-
VCC
Optional +5V Power Supply
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Publication Release Date: January 1996 Revision A2
W83C43
Pin Description, continued
PIN NO.
(40-pin DIP) (44-pin PLCC)
I/O
NAME AT MODE
FUNCTION PS/2 MODE Bit 0 of Port1 (K/B Data Input) Bit 1 of Port1 (Mouse Data Input) Bit 2 of Port2 (User-defined I/O) Bit 3 of Port1 (User-defined I/O) Bit 4 of Port1 (RAM: RAM Jumper Select) Bit 5 of Port1 (JUMP: Jumper) Bit 6 of Port1 (DISP: Display Select) Bit 7 of Port1 (KINH: K/B Inhibit Switch) Bit 4 of Port2 (KINT: K/B OBF O/P Interrupt) Bit 5 of Port2 (MINT: Mouse OBF O/P Interrupt) Bit 6 of Port2 (KCLK: K/B Clock Output) Bit 7 of Port2 (KDAT: K/B Data Output) Mouse Clock Input +5V Power Supply
27 28 29 30 31
30 31 32 33 35
I/O
PU*
P10 P11 P12 P13 P14
Bit 0 of Port1 (User-defined I/O) Bit 1 of Port1 (User-defined I/O) Bit 2 of Port2 (User-defined I/O) Bit 3 of Port1 (User-defined I/O) Bit 4 of Port1 (RAM: RAM Jumper Select)
I/O
PU*
I/O I/O I
PU*
32 33 34 35
36 37 38 39
I
PU*
P15 P16 P17 P24
Bit 5 of Port1 (JUMP: Jumper) Bit 6 of Port1 (DISP: Display Select) Bit 7 of Port1 (KINH: K/B Inhibit Switch) Bit 4 of Port2 (KINT: K/B OBF O/P Interrupt)
I
PU*
I
PU*
O
36
40
O
P25
Bit 5 of Port2 (IEMP: I/P Buffer Empty)
37 38 39 40
41 42 43 44
O O I -
P26 P27 T1 Vcc
Bit 6 of Port2 (KCLK: K/B Clock Output) Bit 7 of Port2 (KDAT: K/B Data Output) K/B Data Input +5V Power Supply
* Internal pull-up resistor
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W83C43
BLOCK DIAGRAM
T0 T1 x1 x2 WR RD CS A2 RESET
RECEIVE CONTROL
SCAN CODE ROM
TRANSMIT CONTRROL
TRANSMIT REGISTER STATUS REGISTER
HARDWIRE CONTROL & SELECT LOGIC
R64
STATUS BUFFER REGISTER
INPUT & OUTPUT PORT
D0~D7
DATA BUFFER REGISTER
W60 W64
INPUT BUFFER REGISTER
INTERFACE
P10 P11 P12 P13 P14 (RAM) P15 (JUMP) P16 (DISP) P17 (KINH)
R60
OUTPUT BUFFER REGISTER OUTPUT PORT INTERFACE
P20 (RC) P21 (GA20) P22 (NC/MDAT) P23 (NC/MCLK) P24 (KINT) P25 (IEMP/MINT) P26 (KCLK) P27 (KDAT)
ABSOLUTE MAXIMUM RATINGS
PARAMETER Ambient Operating Temperature Storage Temperature Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation RATING -0 to + 85 -65 to + 150 -0.3 to + 7.0 -0.3 to + 7.0 50 UNIT C C V V mW
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Publication Release Date: January 1996 Revision A2
W83C43
ELECTRICAL CHARACTERISTICS & CAPACITANCE
(Ta = 0 C to + 70 C, VDD = +5V 5%)
SYMBOL VDD VIL VIL1 VIH1 VIH2 VIH3 VOH1 VOH2 VOL1 VOL2 RIP IOFL IIH IIL IIL1 CL
DESCRIPTION Power Supply Input Low Voltage (except RESET, T0, T1) Input Low Voltage (RESET, T0, T1) Input High Voltage (except RESET, T0, T1, P10, P11) Input High Voltage (P10, P11) Input High Voltage (T0, T1, RESET) Output High Voltage (P10-P13, P20-P27) Output High Voltage (D0-D7) Output Low Voltage (P10-P13, P20-P27) Output Low Voltage (D0-D7) Min. I/P Resist O/P Leakage Current (D0-D7, High Z State) I/P Leakage Current I/P Leakage Current (Except P10, P11, P14, P15, P16, P17) I/P Leakage Current (P10, P11, P14, P15, P16, P17) O/P Load Capacity
MIN. 4.75
TYP. 5.0
MAX. 5.25 0.8 0.6
UNIT V V V V V V
NOTE
2.0 3.0 3.5 2.4 2.4 0.4 0.4 10K -10 -10 -10 -10 15 10 10 10 550 50
V V V V A A A A pF
IOH = -2 mA IOH = -4 mA IOL = 2 mA IOL = 4 mA
VDD = 5.5V, VIN = VDD VDD = 5.5V, VIN = VSS VDD = 5.5V, VIN = VSS
STATUS REGISTER (AT MODE)
The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 1 BIT FUNCTION Output Buffer Full Input Buffer Full DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full -6-
W83C43
Status Register (AT Mode), continued
BIT 2
BIT FUNCTION System Flag
DESCRIPTION This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: No transmit time-out error 1: Transmit time-out error 0: No receive time-out error 1: Receive time-out error 0: Odd parity (no error) 1: Even parity (error)
3 4 5 6 7
Command/data Inhibit Switch Transmit Time-out Receive Time-out Parity Error
OUTPUT BUFFER
The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer should be read only when the output buffer full bit in the register is 1.
ONPUT BUFFER
The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60 sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0. (A) Input Port Definition (AT Mode) BIT 0 1 2 3 4 Undefined Undefined Undefined Undefined RAM on System Board 0: Disable second 256 KB of system board RAM 1: Enable second 256 KB of system board RAM FUNCTION
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Publication Release Date: January 1996 Revision A2
W83C43
(A) Input Port Definition (AT Mode), continued
BIT 5
FUNCTION Manufacturing Jumper Installed 0: Manufacturing jumper 1: Jumper not installed Display Type Switch 0: Primary display attached to color/graphics 1: Primary display attached to monochrome Keyboard Inhibit Switch 0: Keyboard inhibited 1: Keyboard not inhibited
6
7
(B) Output Port Definition (AT Mode) BIT 0 1 2 3 4 5 6 7 System Reset Gate A20 Undefined Undefined Output Buffer Full Input Buffer Empty Keyboard Clock (Output) Keyboard Data (Output) FUNCTION
(C) Test-input Port Definition (AT Mode) BIT 0 1 Keyboard Clock (Input) Keyboard Data (Input) FUNCTION
Status Register (PS/2 Mode)
BIT 0 1 2 BIT FUNCTION Output Buffer Full Input Buffer Full System Flag DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set to 0 or 1 by writting to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset.
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W83C43
Status Register (PS/2 Mode), continued
BIT 3 4 5 6 7
BIT FUNCTION Command/Data Inhinit Switch Auxiliary Device Output Buffer General Purpose Timeout Parity Error 0: Data byte 1: Command byte
DESCRIPTION
0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error)
Input Port Definition
BIT 0 1 2 3 4 Keyboard Data Input Mouse Data Input Undefined Undefined RAM on System Board 0: Disable second 256 KB of system board RAM 1: Enable second 256 KB of system board RAM Manufacturing Jumper 0: Manufacturing jumper 1: Jumper not installed Display Type Switch 0: Primary display attached to color/graphics 1: Primary display attached to monochrome Keyboard Input Switch 0: Keyboard inhibited 1: Keyboard not inhibited FUNCTION
5
6
7
Output Port Definition
BIT 0 1 2 3 System Reset Gate A20 Mouse Data Output Mouse Clock Output FUNCTION
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Publication Release Date: January 1996 Revision A2
W83C43
Output Port Definition, continued
BIT 4 5 6 7
FUNCTION Keyboard Output Buffer Full Interrupt Mouse Output Buffer Full Interrupt Keyboard Clock Output Keyboard Data Output
Test-input Port Definition
BIT 0 1 Keyboard Clock Input Mouse Clock Input FUNCTION
Commands (I/O Address HEX 64) (AT Mode)
COMMAND 20 60 FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller
BIT 7 6 5 4 3 2 1 0 Reserved IBM PC Compatible Mode IBM PC Mode Disable Keyboard Inhibit Override System Flag Reserved Enable Output Buffer Full Interrupt BIT DEFINITION
AA AB
Self-test Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected K/B Clock Line is Stuck Low K/B Clock Line is Stuck High K/B Data Line is Stuck Low K/B Data Line is Stuck High
AD AE
Disable Keyboard Feature Enable Keyboard Interface
- 10 -
W83C43
Commands (I/O Address HEX 64) (AT Mode), continued
COMMAND C0 D0 D1 E0 F0-FF Read Input Port Read Output Port Write Output Port Read Test Inputs Pulse Output Port
FUNCTION
Commands (I/O Address HEX 64) (PS/2 Mode)
COMMAND 20 60 FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller
BIT 7 6 5 4 3 2 1 0 Reserved IBM Keyboard Translate Mode Disable Auxiliary Device Disable Keyboard Reserve System Flag Enable Auxiliary Interrupt Enable Keyboard Interrupt BIT DEFINITION
A7 A8 A9
Disable Auxiliary Device Interface Enable Auxiliary Device Interface Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low Auxiliary Device "Data" line is stuck low
AA
Self-test
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Publication Release Date: January 1996 Revision A2
W83C43
Commands (I/O Address HEX 64) (PS/2 Mode), continued
COMMAND AB Interface Test
BIT 00 01 02 03 04 BIT DEFINITION No Error Detected
FUNCTION
Keyboard "Clock" line is stuck low Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low Keyboard "Data" line is stuck high
AD AE C0 C1 C2 D0 D1 D2 D3 D4 E0 F0-FF
Disable Keyboard Interface Enable Keyboard Interface Read Input Port Poll Input Port Low Poll Input Port High Read Output Port Write Output Port Write Keyboard Output Buffer Write Auxiliary Device Output Buffer Write to Auxiliary Device Read Test Inputs Pulse Output Port
AC TIMING
NO. T1 T2 T3 T4 T5 T6 T7 T8 T9 DESCRIPTION Address Setup Time from WRB Address Setup Time from RDB WRB Strobe Width RDB Strobe Width Address Hold Time from WRB Address Hold Time from RDB Data Setup Time Data Hold Time Gate Delay Time from WRB MIN. 0 0 20 20 0 0 50 0 10 30 MAX. UNIT nS nS nS nS nS nS nS nS nS
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W83C43
AC Timing, continued
NO. T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34
DESCRIPTION RDB to Drive Data Delay RDB to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving RC Fast Reset Pulse Delay (8 MHz) RC Pulse Width (8 MHz) Transmit Timeout Data Valid Hold Time X1/X2 Period (6-12 MHz) Duration of CLK inactive Duration of CLK active Time from inactive CLK transition, used to time when the auxiliary device sample DATA Time of inhibit mode Time from rising edge of CLK to DATA transition Duration of CLK inactive Duration of CLK active Time from DATA transition to falling edge of CLK Mode detect signal after P10 goes high High pulse of mode detect signal Low pulse of mode detect signal Mode detect signal after RESET goes high Time out of AT mode` s mode detect signal
MIN. 0
MAX. 40 20 4
UNIT nS nS S S S S S
20 10 4 20 2 6 2 0 83 30 30 5 100 5 30 30 5 167 50 50 25 300 T28-5 50 50 25 3
S S mS S nS S S S S S S S S
Typical 1 mS Typical 220 S Typical 220 S Typical 1 mS Typical 64 mS
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Publication Release Date: January 1996 Revision A2
W83C43
TIMING WAVEFORMS
Write Cycle Timing
A2, CSB
T1 T3 ACTIVE T7 T8 T5
WRB
D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND
DATA IN T9
T17
T18
Read Cycle Timing
A2,CSB AEN
T2 T4 T6
RDB
ACTIVE T10 T11
D0-D7
DATA OUT
Send Data to K/B
CLOCK (KCLK)
T12 T14 D0 D1 D2 D3 T13 D4 T19 D5 D6 D7 P T16
SERIAL DATA (KDAT)
START
STOP
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W83C43
Receive Data from K/B
CLOCK (KCLK)
T15 T14 D0 D1 D2 D3 D4 T13 D5 D6 D7 P
SERIAL DATA (T1)
START T20
STOP
X1/X2 Clock
CLOCK CLOCK T21
Send Data to Mouse
MCLK
T25 T22 T23 T24
MDAT
START Bit
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP Bit
Receive Data from Mouse
MCLK
T29 T26 T27 T28
MDAT
START
D0
D1
D2
D3
D4
D5
D6
D7
P
STOP Bit
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Publication Release Date: January 1996 Revision A2
W83C43
PS2 Mode's Mode Detect
(P10 released to high by keyboard before RESET goes high)
RESET P27
T31 T33
P10
T32
PS2 Mode's Mode Detect
(P10 released to high by keyboard after RESET goes high)
RESET P27
T31 T30
P10
T32
AT Mode's Mode Detect
(P10 internal pull high. As there is no external loop between P27 and P10 so P27 issues pulse until time out )
RESET
T34
P27
T33
T31
T32
P10
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W83C43
TYPICAL APPLICATION CIRCUITS
Application for AT Mode
2 3 RESETB SA2 8042CS# IORD# IOWR# 4 1 39 9 6 5 8 10 12 13 14 15 16 17 18 19 D[0..7] 7 20
X1 X2 RESET T0 T1 A2 CS Vcc RD WR D0 D1 D2 D3 D4 D5 D6 D7 GND GND KB8042-DIP
Vcc Vcc P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24/OB P25 P26/KCLK P27/KDAT NC NC
40 25 27 28 29 30 31 32 33 34 21 22 23 24 35 36 37 38 11 26 7407 1 2 1 2 KEYBOARD CLOCK
RAM SELECT JUMPER MANUFACTURING MODE JUMPER
RCB GATE20 KEYBOARD INTERRUPT Vcc
74ALS04 7407 1 2 KEYBOARD DATA
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Publication Release Date: January 1996 Revision A2
W83C43
Application for PS/2 Mode
KEYBOARD INTERRUPT
PS/2 MOUSE INTERRUPT
2
X1
Vcc Vcc P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24/OB P25 P26/KCLK P27/KDAT
40 25 27 28 29 30 31 32 33 34 21 22 23 24 35 36 37 38 11 26
3 RESETB 4 1 39 9 6 5 8 10 12 13 14 15 16 17 18 19 D[0..7] 7 20
X2 RESET T0 T1 A2 CS Vcc RD WR D0 D1 D2 D3 D4 D5 D6 D7 GND GND
SA2 8042CS# IORD# IOWR#
RAM SELECT JUMPER MANUFACTURING MODE JUMPER
RCB GATE20
Vcc
NC NC
7406 1
PS/2 MOUSE DATA 2
KB8042-DIP 7406 1 PS/2 MOUSE CLOCK 2 Vcc
1
2
7406 KEYBOARD CLOCK
1
2
7406 KEYBOARD DATA
- 18 -
W83C43
Driving from External Source
OPTION 1
2
X1
PCLK
1
2
3
X2
OPTION 2
PCLK
1
2
2
X1
N.C.
3
X2
OPTION 3
+5V
470
470
PCLK
1 7404
2
1 7407
2
2
X1
1 7407
2
3
X2
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Publication Release Date: January 1996 Revision A2
W83C43
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090
Min. Nom. Max.
5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 52.20 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.37 0.36 52.58 15.49 13.97 2.79 3.56 15 17.02 2.29
D 40 21
A A1 A2 B B1 c D E E1 e1 L
a
1
E
eA S
1 S
2
20 E c A
1
Notes:
1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
AA
Base Plane Seating Plane
L B B1 e1
a
eA
44-pin PLCC
HD D
6 1 44 40
Symbol
39
Dimension in inch
Dimension in mm
Min. Nom. Max.
0.185 0.020 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014
Min. Nom. Max.
4.70 0.51 3.68 0.66 0.41 0.20 3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36
7
EH
E
G
E
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC
0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 0.004 2.29 2.54 2.79 0.10
L
2
AA
e Seating Plane GD
b b1
1
A y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W83C43
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: January 1996 Revision A2

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