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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
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Single 5-V Operation Low Power Consumption: Operating Mode . . . 55 mW Typ Standby Mode . . . 8 mW Typ Power-Down Mode . . . 3 mW Typ Combined ADC, DAC, and Filters Extended Variable-Frequency Operation Pass-Band up to 10 kHz Electret Microphone Bias Reference Voltage Available Directly Drives a Piezo Speaker Compatible With All DSPs Selectable Between 8-Bit, -Law Companded and 13-Bit Linear Conversion Programmable Volume Control in Linear Mode Designed for Standard 2.048-MHz Master Clock for U.S. Analog, U.S. Digital, CT2, Battery-Powered Telephones
DW OR N PACKAGE (TOP VIEW)
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PDN EARA EARB EARGS VCC MICMUTE DCLKR DIN FSR EARMUTE
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
MICBIAS MICGS MICIN VMID GND LINSEL TSX/DCLKX DOUT FSX CLK
description
The general-purpose audio interface for digital signal processors (DSPs) is designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) together with transmit and receive filtering for voice-band audio systems. In particular, cellular telephone systems are targeted; however, this integrated circuit can function in several systems, including digital audio, multimedia telecommunications, noise cancellation, and other data acquisition. The converted data is available in two formats. The formats are pin selectable between companded and linear. When the device is in the companded mode, data is transmitted and received in eight-bit words. When the linear mode is selected, 13 bits of data are sent and received, padded with trailing zeros or volume control bits to provide a 16-bit word. The transmit section is designed to directly interface with an electret microphone element. A reference voltage equal to VCC /2, called VMID, is used to develop the midlevel virtual ground for all the amplifier circuits and the microphone bias circuit. A reference voltage called MICBIAS can be used to supply bias current for the microphone. The microphone input signal (MICIN) is buffered and amplified with provision for setting the amplifier gain to accommodate a range of signal input levels. The amplified signal is passed through antialiasing and band-pass filters. The filtered signal is then input to a compressing analog-to-digital converter (COADC) if companded mode is selected; otherwise, the analog-to-digital converter performs a linear conversion.
Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1993, Texas Instruments Incorporated
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
description (continued)
The receive section takes a frame of serial data on DIN and converts it to analog through an expanding digital-to-analog converter (EXDAC) if the companded mode is selected; otherwise, a linear conversion is performed. The analog signal then passes through switched-capacitor filters, which provide out-of-band rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The earphone amplifier has a differential output with adjustable gain that is designed to minimize static power dissipation. A single on-chip, high-precision band-gap circuit generates all voltage references, eliminating the need for external reference voltages. The TCM320AC46 device is characterized for operation from 0C to 70C.
functional block diagram
LINSEL 15 MICMUTE MICIN 6 18 Input Buffer Transmit Third-Order Antialias Transmit Sixth-Order Low Pass Transmit First-Order High Pass ADC Output Logic 13 DOUT
12 MICGS 19 256 kHz Band-Gap Voltage Reference A/D Converter Voltage Reference 256 kHz D/A Converter Voltage Reference 8 kHz Autozero 8 kHz
FSX
VMID VMID MICBIAS 17 20
VMID Generator
14 Clock Generator Clock Control
TSX/DCLKX 11 CLK 7 DCLKR
256 kHz 2 EARA 3 EARB 4 EARGS 10 EARMUTE
9
FSR
Earphone Amplifier
Receive Buffer
Receive Filter
DAC 15
Input Logic
8
DIN
5 VCC
16 GND PDN
1
LINSEL
2
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
Terminal Functions
PIN NAME CLK DCLKR NO. 11 7 I/O I I DESCRIPTION In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and receive data clock input. In the variable-data-rate mode, CLK serves only as the master clock input. Selects fixed- or variable-data-rate operation. When DCLKR is connected to VCC, the device operates in the fixed-data-rate mode. When DCLKR is not connected to VCC, the device operates in the variable-data-rate mode and DCLKR becomes the receive data clock. Receive data input. Input data is clocked in on consecutive negative transitions of the receive data clock, which is CLK for a fixed data rate and DCLKR for a variable data rate. Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit data clock, which is CLK for a fixed data rate and DCLKX for a variable data rate. Earphone output. EARA forms a differential drive when used with the EARB signal. Earphone output. EARB forms a differential drive when used with the EARA signal. Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential divider network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain occurs when EARGS is connected to EARB, and minimum gain occurs when EARGS is connected to EARA. Earphone frequency response correction is performed using an external RC filter. Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no audio is sent to the earphone. Frame synchronization clock input for receive channel. In the variable-data-rate mode, FSR must remain high for the duration of the time slot. The receive channel enters the standby state when FSR is TTL low for five frames or longer. The device enters a production test-mode condition when either FSR or FSX is held high for five frames or longer. Frame synchronization clock input for transmit channel. FSX operates independently of, but in an analogous manner to, FSR. The transmit channel enters the standby state when FSX is low for five frames or longer. The device enters a production test-mode condition when either FSX or FSR is held high for five frames or longer. Ground return for all internal analog and digital circuits I O O I I I I/O Linear selection input. When low, LINSEL selects linear coding/decoding. When high, LINSEL selects companded coding/decoding. The companded mode is -law. Bias voltage equal to VMID for the electret microphone Output of the internal microphone amplifier. MICGS used as the feedback to set the microphone amplifier gain. If sidetone is required, it is accomplished by connecting a series network between MICGS and EARGS. Electret microphone input to the internal microphone amplifier Microphone input mute control signal. When MICMUTE is active (low), the input amplifier is disabled, the microphone current is switched off, and zero code is transmitted. Power-down input. When low, the device powers down to reduce power consumption. Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the fixed-data-rate mode, this is an open-drain output that pulls to ground and is used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data clock input. 5-V supply voltage for all internal analog and digital circuits O VCC /2 bias voltage reference. An external, low-leakage, high-frequency 1-F capacitor should be connected to VMID for filtering.
DIN DOUT EARA EARB EARGS
8 13 2 3 4
I O O O I
EARMUTE FSR
10 9
I I
FSX
12
I
GND LINSEL MICBIAS MICGS MICIN MICMUTE PDN TSX/DCLKX
16 15 20 19 18 6 1 14
VCC VMID
5 17
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
general information
system reliability features The device should be powered up and initialized as follows: 1. GND is applied. 2. VCC is applied. 3. All clocks are connected. 4. TTL high is applied to PDN. 5. FSX and/or FSR synchronization pulses are applied. Even though the device is heavily protected against latch-up, it is still possible to cause it to latch-up under certain improper power conditions where excess current is forced into or out of one or more terminals. To assure that latch-up will not occur, it is good design practice to put a reverse-biased Schottky diode between VCC (power supply) and GND. On the transmit channel, digital outputs DOUT and TSX are held in the high-impedance state for approximately four frames (500 s) after power up or application of VCC. After this delay, DOUT, TSX, and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system integrity, DOUT and TSX are placed in the high-impedance state after an interruption of CLK. power-down and standby operations To minimize power consumption, a power-down mode and three standby modes are provided. For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled up to a high logic level and the device remains active. In the power-down mode, the average power consumption is reduced to 3 mW. The standby modes give the user the options of putting the entire device on standby, putting only the transmit channel on standby, or putting only the receive channel on standby. To place the entire device on standby, both FSX and FSR are held low. For transmit-only operation, FSX is pulsed and FSR is held low. For receive-only operation, FSR is pulsed and FSX is held low. In the standby mode with both transmit and receive on standby, power consumption is reduced to 8 mW. See Table 1 for power-down and standby procedures.
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
Table 1. Power-Down and Standby Procedures
DEVICE STATUS PROCEDURE PDN = high, FSX = pulses, FSR = pulses PDN = low, FSX/FSR = X/X FSX = low, FSR = low, PDN = high FSX = low, FSR = pulses, PDN = high FSR = low, FSX = pulses, PDN = high TYPICAL POWER CONSUMPTION 55 mW DIGITAL OUTPUT STATUS
Power on
Digital outputs active but not loaded
Power down
3 mW
TSX and DOUT in the high-impedance state
Entire device on standby
8 mW
TSX and DOUT in the high-impedance state
Only transmit on standby
20 mW
TSX and DOUT in the high-impedance state within 5 frames
Only receive on standby
20 mW
Digital outputs active but not loaded
fixed-data-rate timing Fixed-data-rate timing is selected by connecting DCLKR to VCC. It uses the master clock (CLK), frame synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data is received on DIN on the falling edges of CLK following FSR. A D/A conversion is performed on the received digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred to the receive filter. The data word is eight bits long in the companded mode and sixteen bits long in the linear mode. variable-data-rate timing Variable-data-rate timing is selected by connecting DCLKR to the receive data clock. In this mode, the master clock (CLK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled by DCLKR and DCLKX, respectively. This allows the data to be transferred into and out of the device at any rate up to the frequency of the master clock. DCLKR and DCLKX must be synchronous with CLK. While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DCLKX. Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of DCLKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as DCLKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than once per frame, is available only with variable-data-rate timing. asynchronous operations In order to avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters, filters, and voltage references on the transmit and receive sides to allow completely independent operation of the two channels. In either timing mode, the master clock, data clock, and time slot strobe must be synchronized at the beginning of each frame. precision voltage references A precision band-gap reference voltage is generated internally and is used to supply all the references required for operation of both the transmit and receive channels. The gain in each channel is trimmed during the manufacturing process. This process ensures very accurate, stable gain performance over variations in supply voltage and device temperature.
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
conversion laws The TCM320AC46 provides -law companding operation. The linear mode utilizes a 13-bit 2s complement format.
transmit operation
microphone input The microphone input amplifier is designed to simplify interface to electret-type microphone elements as shown in Figure 1. The VMID buffer circuit provides a voltage (MICBIAS) equal to VCC /2 as a reference for the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output (MICGS) is used in conjunction with a feedback network to the amplifier inverting input (MICIN) to set the amplifier gain. VMID is brought out to provide a place to filter the VMID voltage. microphone mute function The MICMUTE input disables the microphone amplifier and attenuates the signal on the MICGS output to a level that is 80 dB or more down from the signal on the MICIN input. MICMUTE also causes the digital circuitry to transmit all zero code on DOUT.
VMID 17 1 F MICBIAS 20
VMID Reference for Amplifiers VMID Buffer + - VMID Generator
2 k
MICGS
+ -
>10 k 0.1 F 19 MICIN 18 MICMUTE 6 TCM320AC46 Microphone Amplifier - + Electret Microphone Microcontroller To Transmit Filter
Figure 1. Typical Microphone Interface transmit filter A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the sampling frequency. No external components are required to provide the necessary antialiasing function for the switched-capacitor section of the transmit filter.
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample-and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital data representing the sample is transmitted on the first eight or 16 data clock cycles of the next frame. The autozero circuit corrects for dc offset on the input signal to the encoder using the sign-bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder. data word structure The data word is eight bits long in the companded mode. All eight bits represent one audio data sample. The sign bit is the first bit transmitted. The data word is 16 bits long in the linear mode. The first 13 bits comprise the audio data sample, and the last three bits are volume control in the receive direction (DIN) and zeros in the transmit direction (DOUT). The sign bit is transmitted first.
receive operation
decoding In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate and the last eight clock cycles in variable-data rate. The serial data word is received at DIN on the first 13 clock cycles in the linear mode. Digital-to-analog conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold capacitor. This sample is transferred to the receive filter. receive filter The receive section of the filter provides pass-band flatness. The filter contains the required compensation for the (sin x)/x response of such decoders. receive buffer The receive buffer contains the volume control. earphone amplifier The earphone amplifier has a balanced output to allow maximum flexibility in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential configuration without any additional external components. The output can also be used to drive a single-ended load with the output signal voltage centered around VCC /2. The receive-channel output level can be adjusted between specified limits by connecting an external resistor network to EARGS. receive data format Eight bits of data are received in the companded mode and are valid. The sign bit is the first bit received (see Table 2). Sixteen bits of data are received in the linear mode. The first 13 bits are the D/A code, and the remaining three bits form the volume control word (see Table 2). The volume control function is actually an attenuation control where the first bit received is the most significant. The maximum volume occurs when all three volume control bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB, when all bits are 1s. The volume control bits are not latched into the device and must be present in each received data word.
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
Table 2. Receive Data Bit Definitions
BIT NO. 0 1 2 3 4 5 6 7 8 9 A B C D E F COMPANDED MODE CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 - - - - - - - - LINEAR MODE LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 V2 V1 V0
relationship between data word and frame sync Volume control and other control bits always follow the PCM data in time:
Bit No. FSX/FSR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fixed Data Rate
FSX/FSR
Variable Data Rate
Companded Mode:
MSB (sign bit) CD7 CD6
Command Word CD5 CD4 CD3 CD2 LSB CD1 CD0
Companded Data
Linear Mode: MSB (sign bit) LD12 LD11 LD10 LD9
LD8
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0 LSB
V2
V1
V0
Linear Data Time
Volume Control
where: CD7- CD0 = Data word when in companded mode -- = Unused bits in companded mode V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 3 dBm0 111 = minimum volume, -18 dBm0 LD12- LD0 = Data word when in linear mode
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range at DOUT, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage rangeat DIN, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage value is with respect to GND. DISSIPATION RATING TABLE PACKAGE DW N TA 25C POWER RATING 1025 mW 1150 mW DERATING FACTOR ABOVE TA = 25C 8.2 mW/C 9.2 mW/C TA = 70C POWER RATING 656 mW 736 mW
recommended operating conditions (see Note 2)
MIN Supply voltage, VCC (see Note 3) High-level input voltage, VIH Low-level input voltage, VIL Load resistance between EARA and EARB, RL (see Note 4) Load capacitance between EARA and EARB, CL (see Note 4) Operating free-air temperature, TA 0 50 113 70 4.5 2.2 0.8 MAX 5.5 UNIT V V V nF C
NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the following sequence should be followed when applying power: 1. Connect to GND. 2. Connect VCC. 3. Connect the input signals. When removing power, follow the preceding steps in reverse order. 3. Voltages at analog inputs and outputs and VCC are with respect to GND. 4. RL and CL should not be applied simultaneously.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
supply current, fDCLKR or fDCLKX = 2.048 MHz, outputs not loaded
PARAMETER Operating ICC Supply current from VCC Power down Standby - one TEST CONDITIONS PDN is high with CLK signal present PDN is low for 500 s PDN is high with FSX and FSR missing for 500 s MIN MAX 14 1.5 2.5 10 mA UNIT
Standby - both PDN is high with FSX and FSR missing for 500 s
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
digital interface
PARAMETER VOH VOL IIH IIL Ci Co High-level output voltage Low-level output voltage High-level input current Low-level input current Input capacitance Output capacitance DOUT Any digital input Any digital input TEST CONDITIONS IOH = - 3.2 mA, IOL = 3.2 mA, VI = 2.2 V to VCC VI = 0 to 0.8 V 5 5 VCC = 5 V VCC = 5 V MIN 2.4 TYP 4.6 0.2 0.4 20 20 MAX UNIT V V A A pF pF
microphone interface
PARAMETER VIO IIB B1 Ci AV Input offset voltage at MICIN Input bias current at MICIN Unity-gain bandwidth, open loop at MICIN Input capacitance at MICIN Large-signal voltage amplification at MICGS Output level at MICGS with MICMUTE active IO( ) O(max) Maximum output current VMID MICBIAS VI = 4 V 1 1 1 5 10000 - 80 TEST CONDITIONS VI = 0 to 5 V MIN TYP MAX 15 200 UNIT mV nA MHz pF V/V dBm0 A mA
speaker interface
PARAMETER IIL VO(PP) VOO Ro IO(max) AV Input leakage at EARGS AC output voltage peak-to-peak Output offset voltage at EARA, EARB (single-ended) Output resistance at EARA, EARB Maximum output current Large-signal voltage amplification - 80 RL = 600 4 Relative to GND 100 1 8 TEST CONDITIONS VI = 0 to 5 V MIN TYP MAX 300 3 UNIT nA VPP mV mA V/V dB
Gain change EARMUTE low, max level when muted All typical values are at VCC = 5 V, TA = 25C. All parameters are measured between MICIN and GND (unless otherwise noted).
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
transmit gain and dynamic range, companded or linear mode, -law or A-law, VCC = 5 V, TA = 25C (unless otherwise noted) (see Notes 5 and 6)
PARAMETER Transmit reference signal level (0 dB) (see Note 7) reference-signal Overload-signal Overload signal level Absolute gain error Gain error with input level relative to gain at -10 dB Gain variation TEST CONDITIONS Linear mode selected Companded mode selected, -law Linear mode selected Companded mode selected, -law 0-dB input signal MICIN to DOUT at 3 dBm0 to - 40 dBm0 MICIN to DOUT at - 41 dBm0 to - 50 dBm0 MICIN to DOUT at - 51 dBm0 to - 55 dBm0 VCC 10%, TA = 0C to 70C MIN MAX 1.001 0.982 4 4 2 0.8 2 2.5 0.5 dB dB UNIT Vrms VPP dB
transmit filter transfer, linear mode or -law selected, over recommended ranges of supply voltage and free-air temperature, CLK = 2.048 MHz, FSX = 8 kHz (see Note 6)
PARAMETER TEST CONDITIONS Input signal = 50 Hz Input signal = 200 Hz Gain l ti t i G i relative to input signal gain at ti lit 1.02 1 02 kHz In ut amplifier Input am lifier set for unity gain, noninverting maximum gain output signal at MICIN is 0 dB Input signal = 300 Hz to 3 kHz Input signal = 3.3 kHz Input signal = 3.4 kHz Input signal = 4 kHz Input signal 4.6 kHz - 0.55 - 2.8 MIN -10 -1.8 MAX 0 0 0.35 0.2 0 -11 - 30 dB UNIT
transmit idle channel noise and distortion, companded mode, -law, over recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER Transmit noise, C-message weighted Transmit signal-to-distortion ratio with sine-wave input TEST CONDITIONS MICIN connected to MICGS through a 10-k resistor MICIN to DOUT at 0 dBm0 to - 30 dBm0 MICIN to DOUT at - 31 dBm0 to - 40 dBm0 MICIN to DOUT at- 41 dBm0 to - 45 dBm0 32 25 18 dB MIN MAX 27 UNIT dBrnC0
transmit idle channel noise and distortion, linear mode, over recommended ranges of supply voltage and operating free-air temperature (see Notes 6 and 8)
PARAMETER Transmit noise TEST CONDITIONS MICIN connected to MICGS through a 10-k resistor MICIN to DOUT at 0 dBm0 to - 6 dBm0 MICIN to DOUT at - 7 dBm0 to - 12 dBm0 Transmit signal-to-distortion ratio with sine-wave input MICIN to DOUT at - 13 dBm0 to - 18 dBm0 MICIN to DOUT at - 19 dBm0 to - 24 dBm0 MICIN to DOUT at - 25 dBm0 to - 45 dBm0 47 42 38 30 15 dB MIN MAX - 60 UNIT dB
NOTES: 5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 6. The input amplifier is set for inverting unity gain. 7. This reference-level signal, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V. 8. Transmit noise, linear mode: 200 Vrms is equivalent to -74 dB (referenced to device 0-dB level).
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
receive gain and dynamic range, linear mode, -law or A-law, VCC = 5 V, TA = 25C (unless otherwise noted) (see Notes 9 and 10)
PARAMETER Receive reference signal level (0 dB) (see Note 11) reference-signal Overload-signal Overload signal level Absolute gain error Gain error with output level relative to gain at -10 dBm0 Gain variation TEST CONDITIONS Linear mode selected Companded mode selected, -law Linear mode selected Companded mode selected, -law 0-dB input signal DIN to EARA and EARB at 3 dBm0 to - 40 dBm0 DIN to EARA and EARB at - 41 dBm0 to - 50 dBm0 DIN to EARA and EARB at - 51 dBm0 to - 55 dBm0 VCC 10%, TA = 0C to 70C MIN MAX 0.751 0.736 3 3 2 0.8 2 2.5 0.5 dB dB UNIT Vrms VPP dB
receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER TEST CONDITIONS Input signal = < 200 Hz Input signal = 200 Hz Input signal = 300 Hz to 3 kHz Gain relative to input signal gain at 1.02 kHz Input signal at DIN is 0 dBm0 Input signal = 3.3 kHz Input signal = 3.4 kHz Input signal = 4 kHz Input signal > 4.6 kHz - 0.55 -2 - 0.8 MIN MAX 0.35 0.35 0.35 0.2 0 - 11 - 28 dB UNIT
receive idle channel noise and distortion, companded mode, -law, over recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER Receive noise, C-message weighted Receive signal-to-distortion ratio with sine-wave input DIN = 11111111 DIN to EARA and EARB at 0 dBm0 to - 30 dBm0 DIN to EARA and EARB at - 31 dBm0 to - 40 dBm0 DIN to EARA and EARB at - 41 dBm0 to - 45 dBm0 32 25 18 dB TEST CONDITIONS MIN MAX 17 UNIT dBrnC0
receive idle channel noise and distortion, linear mode over recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER Receive noise TEST CONDITIONS DIN = 00000000(linear) DIN to EARA and EARB at 0 dBm0 to - 6 dBm0 DIN to EARA and EARB at - 6 dBm0 to - 12 dBm0 Receive signal-to-distortion ratio with sine-wave input DIN to EARA and EARB at - 13 dBm0 to - 18 dBm0 DIN to EARA and EARB at - 19 dBm0 to - 24 dBm0 DIN to EARA and EARB at - 25 dBm0 to - 45 dBm0 48 42 38 30 14 dB MIN MAX - 60 UNIT dB
NOTES: 8. Transmit noise, linear mode: 200 Vrms is equivalent to -74 dB (referenced to device 0-dB level). 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected. 10. Unless otherwise noted, the digital input is a word stream generated by passing a 0-dB sine wave at 1020 Hz through an ideal encoder where 0 dB is defined as the zero reference. 11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier set to unity.
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature
PARAMETER Supply voltage rejection ratio, transmit channel TEST CONDITIONS Idle channel, supply signal = 100 mVrms, f = 0 to 30 kHz (measured at DOUT) Idle channel, supply signal = 100 mVrms, EARGS connected to EARB, f = 0 to 30 kHz (measured differentially between EARA and EARB) MICIN = 0 dB, f = 1.02 kHz, unity transmit gain, EARGS connected to EARB, measured differentially between EARA and EARB DIN = 0 dBm0, f = 1.02 kHz, unity transmit gain, measured at DOUT 55 MIN TYP - 30 MAX UNIT dB
Supply voltage rejection ratio, receive channel
- 30
dB
Crosstalk attenuation, transmit-to-receive (differential) Crosstalk attenuation, receive-to-transmit All typical values are at VCC = 5 V, TA = 25C.
dB
55
dB
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 2, 3, 4, and 5)
MIN tt Transition time, CLK and DCLK Duty cycle, CLK Duty cycle, DCLK All typical values are at VCC = 5 V, TA = 25C. 45% 45% 50% 50% TYP MAX 10 55% 55% UNIT ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 3)
MIN tsu(FSX) th(FSX) Setup time, FSX Hold time, FSX 20 20 MAX 468 468 UNIT ns ns
receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 2)
MIN tsu(FSR) th(FSR) tsu(DIN) th(DIN) Setup time, FSR Hold time, FSR Setup time, DIN Hold time, DIN 20 20 20 20 MAX 468 468 UNIT ns ns ns ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 5)
MIN tsu(FSX) th(FSX) Setup time, FSX Hold time, FSX 40 35 MAX tc(DCLKX)- 40 tc(DCLKX)- 35 UNIT ns ns
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13
TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 4)
MIN tsu(FSR) th(FSR) tsu(DIN) th(DIN) Setup time, FSR Hold time, FSR Setup time, DIN Hold time, DIN 40 35 30 30 tc(DCLKR)- 35 MAX UNIT ns ns ns ns
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode, CL = 0 to 10 pF (see Figures 2 and 3)
TEST CONDITIONS tpd1 tpd2 tpd3 tpd4 tpd5 From CLK bIt 1 high to DOUT bit 1 valid From CLK high to DOUT valid, bits 2 to n From CLK bit n low to DOUT bit n Hi-Z From CLK bit 1 high to TSX active (low) From CLK bit n low to FSX inactive (high) Rpullup = 1.24 k Rpullup = 1.24 k 30 30 40 MIN MAX 35 35 UNIT ns ns ns ns ns
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see Figures 4 and 5)
TEST CONDITIONS tpd6 tpd7 tpd8 FSX high to DOUT bit 1 valid DCLKX high to DOUT valid, bits 2 to n FSX low to DOUT bit n Hi-Z CL = 0 to 10 pF CL = 0 to 10 pF 20 MIN MAX 30 40 UNIT ns ns ns
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL. Bit 1 = MSB (most significant bit) and is clocked in first on DIN or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.
Receive Time Slot 0 80% CLK 20% tsu(FSR) FSR 80% th(FSR) 20% See Note B See Note A DIN N-1 N 1 2 3 4 N-2 th(DIN) N-1 tsu(DIN) N 1 20% 1 2 3 4 N-2 N-1 N 80% N+1
See Note C NOTES: A. This window is allowed for FSR high. B. This window is allowed for FSR low. C. Transitions are measured at 50%.
Figure 2. Fixed-Data-Rate, Receive Side Timing Diagram
Transmit Time Slot CLK 0 80% 20% tsu(FSX) th(FSX) FSX 80% 20% See Note B See Note A DOUT See Note C tpd1 TSX 20% 1 2 3 tpd2 N-2 tpd3 N-1 tpd5 80% N 1 2 80% 20% 3 4 N-2 N-1 N 80% N+1
tpd4
NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations). C. Transitions are measured at 50%.
Figure 3. Fixed-Data-Rate, Transmit Side Timing Diagram
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15
TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
PARAMETER MEASUREMENT INFORMATION
Receive Time Slot 0 DCLKR 80% 20% tsu(FSR) FSR See Note A DIN N-1 N 1 2 3 4 th(DIN) N-2 See Note B N-1 tsu(DIN) N 1 tc(DCLKR) 1 2 80% 3 80% 20% 20% th(FSR) 20% 4 N-2 N-1 N 80% N+1 80%
See Note C
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations). B. This window is allowed for FSR low. C. Transitions are measured at 50%.
Figure 4. Variable-Data-Rate, Receive Side Timing Diagram
Transmit Time Slot 4 N-2 80% 80% tc(DCLKR) tpd7 See Note B tpd8 3 4 N-2 N-1 N
0 DCLKX
80%
1 20%
2 80% tsu(FSX)
3
N-1 20% th(FSX)
N
80%
N+1
FSX
80% 80% See Note A tpd6
DOUT See Note C
1
2
NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low without data repetition. C. Transitions are measured at 50%.
Figure 5. Variable-Data-Rate, Transmit Side Timing Diagram
APPLICATION INFORMATION output gain set design considerations (see Figure 6)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are: VO + at EARA VO - at EARB VOD = VO + - VO - (total differential response) R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS. A value greater than 10 k and less than 100 k for R1 + R2 is recommended because of the following: The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
16
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TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
APPLICATION INFORMATION
VA represents the maximum available digital mW output response (VA = 1.06 Vrms). VOD = A x VA where A = 1 + (R1/R2) 4 + (R1/R2)
2 R1 VO+ RL VO R2 3 4
EARA
EARGS
DIN
Digital mW Sequence Per CCITT G.712
EARB
VO -
Figure 6. Gain-Setting Configuration
higher clock frequencies and sample rates
The TCM320AC46 is designed to work with sample rates up to 24 kHz where the frequency of the frame sync determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of master clock frequency, fCLK, to frame sync frequency, fFSR/fFSX. This ratio for the device is 2.048 MHz/8 kHz or 256 master clocks per frame sync. For example, to operate the TCM320AC46 at a sampling rate of fFSR and fFSX equal to 16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the TCM320AC46 is operated above an 8-kHz sample rate, however, it is expected that the performance will be degraded.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TCM320AC46 GENERAL-PURPOSE AUDIO INTERFACE FOR DSP
SLWS001 - D4091, JUNE 1993
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1996, Texas Instruments Incorporated

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