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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
This Data Sheet is Applicable to All TMS27C128s and TMS27PC128s Symbolized with Code "B" as Described on Page 12.
J AND N PACKAGES (TOP VIEW)
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Organization . . . 16K x 8 Single 5-V Power Supply Pin Compatible With Existing 128K MOS ROMs, PROMs, and EPROMs All Inputs/Outputs Fully TTL Compatible Max Access/Min Cycle Times VCC 10% '27C128-12 '27C/PC128-15 '27C/PC128-20 '27C/PC128-25 120 150 200 250 ns ns ns ns
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC PGM A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
400-mV Minimum DC Noise Immunity With Standard TTL Loads Latchup Immunity of 250 mA on All Input and Output Lines Low Power Dissipation ( VCC = 5.25 V ) - Active . . . 158 mW Worst Case - Standby . . . 1.4 mW Worst Case (CMOS Input Levels) PEP4 Version Available With 168-Hour Burn-In and Choices of Operating Temperature Ranges 128K EPROM Available With MIL-STD-883C Class B High-Reliability Processing (SMJ27C128)
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A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 DQ0 13
A7 A12 VPP NU VCC PGM A13
4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20
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Power Saving CMOS Technology Very High-Speed SNAP! Pulse Programming 3-State Output Buffers
FM PACKAGE (TOP VIEW)
A8 A9 A11 NC G A10 E DQ7 DQ6
description
PIN NOMENCLATURE
The TMS27C128 series are 131 072-bit, ultraviolet-light erasable, electrically programmable read-only memories. The TMS27PC128 series are 131 072-bit, one time electrically programmable read-only memories.
A0-A13 E G GND NC NU PGM DQ0-DQ7 VCC VPP
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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DQ1 DQ2 VSS NU DQ3 DQ4 DQ5
Address Inputs Chip Enable/Powerdown Output Enable Ground No Connection Make No External Connection Program Inputs (programming)/Outputs 5-V Power Supply 12-13 V Programming Power Supply
Copyright (c) 1993, Texas Instruments Incorporated
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external resistors. The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs. The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature ranges of 0C to 70C (JL suffix) and - 40C to 85C (JE suffix). The TMS27C128 is also offered with 168-hour burn-in temperature ranges (JL4 and JE4 suffixes). (See table below). The TMS27PC128 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two operating temperature ranges of 0C to 70C (NL and FML suffixes) and - 40C to 85C (NE and FME suffixes). The TMS27PC128 is also offered with 168 hour burn-in temperature ranges (NL4, FML4, NE4, and FME4 suffixes). (See table below). All package styles conform to JEDEC standards.
EPROM AND PROM TMS27C128-XXX TMS27PC128-XXX TMS27PC128-XXX SUFFIX FOR OPERATING TEMPERATURE RANGES WITHOUT PEP4 BURN-IN 0C TO 70C JL NL FML - 40 C TO 85C JE NE FME SUFFIX FOR OPERATING TEMPERATURE RANGES WITH PEP4 168 HR. BURN-IN 0C TO 70C JL4 NL4 FML4 - 40 C TO 85C JE4 NE4 FME4
These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 12-13-V supply is needed for programming . All programming signals are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The SNAP! Pulse programming algorithm uses a VPP of 13.0 V and a VCC of 6.5 V for a nominal programming time of two seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
operation
The seven modes of operation are listed in the following table. Read mode requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
MODE FUNCTION E G PGM VPP VCC A9 A0 DQ0-DQ7 X can be VIL or VIH. VH = 12 V 0.5 V. READ VIL VIL VIH VCC VCC X X Data Out OUTPUT DISABLE VIL VIH VIH VCC VCC X X HI-Z STANDBY VIH X X VCC VCC X X HI-Z PROGRAMMING VIL VIH VIL VPP VCC X X Data In VERIFY VIL VIL VIH VPP VCC X X Data Out PROGRAM INHIBIT VIH X X VPP VCC X X HI-Z SIGNATURE MODE VIL VIL VIH VCC VCC VH VIL CODE MFG 97 DEVICE 83 VH VIH
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
read/output disable When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. latchup immunity Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. power down Active ICC supply current can be reduced from 30 mA to 500 A (TTL-level inputs) or 250 A (CMOS-level inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state. erasure (TMS27C128) Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light exposure dose (UV intensity x exposure time) is 15-Ws/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C128, the window should be covered with an opaque label. initializing (TMS27PC128) The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased. SNAP! Pulse programming The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will vary as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM is pulsed. The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (s) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-s pulses per byte are provided before a failure is recognized. The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, G = VIH, and E = VIL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V. program inhibit Programming may be inhibited by maintaining a high level input on the E or PGM pin.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
program verify Programmed bits may be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH. signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V 0.5 V. Two identifier bytes are accessed by A0; i.e., A0 = VIL accesses the manufacturer code, which is output on DQ0-DQ7; A0 = VIH accesses the device code, which is output on DQ0-DQ7. All other addresses must be held at VIL. The manufacturer code for these devices is 97, and the device code is 83.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
Start
Address = First Location VCC = 6.5 V 0.25 V, VPP = 13 V 0.25 V Program One Pulse = tw = 100 s Increment Address Program Mode
Last Address?
No
Yes Address = First Location X=0 Program One Pulse = tw = 100 s No
Increment Address
Verify One Byte
Fail X=X+1 X = 10? Interactive Mode
Pass
No
Last Address?
Yes VCC = VPP = 5 V 0.5 V
Yes Device Failed
Compare All Bytes To Original Data
Fail
Final Verification
Pass Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
logic symbol
EPROM 16 384 x 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 10 9 8 7 6 5 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 E 10 9 8 7 6 5 4 3 25 24 21 23 2 26 20 0
PROM 16 384 x 8
A A A
11 12 13 15 16 17 18 19
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
A A A 0 16 383 A A A A A A
11 12 13 15 16 17 18 19
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
4 3 25 24 21 23 A11 A12 2 26 A13 20 E
0 16 383
A A A A A A
*
13 [PWR DWN] &
*
13 [PWR DWN] &
G
22
EN
G
22
EN
PGM 27
PGM 27
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are J and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Supply voltage range, VPP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V Input voltage range (see Note 1), All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 13.5 V Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V Operating free-air temperature range ('27C128-_ _JL and JL4, '27PC128-_ _NL, and NL4 FML, and FML4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Operating free-air temperature range ('27C128-_ _JE and JE4, '27PC128-_ _NE, NE4, FME, and FME4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
recommended operating conditions
MIN VCC VPP VIH VIL Supply voltage Supply voltage High-level High level dc input voltage Low-level Low level dc input voltage Read mode (see Note 2) SNAP! Pulse programming algorithm Read mode SNAP! Pulse programming algorithm TTL CMOS TTL CMOS '27C128-_ _JL,JL4 '27PC128_ _NL,NL4 FML, FML4 '27C128-_ _JE,JE4 '27PC128_ _NE,NE4 FME, FME4 4.5 6.25 VCC - 0.6 12.75 2 VCC - 0.2 - 0.5 - 0.5 0 NOM 5 6.5 13 MAX 5.5 6.75 VCC + 0.6 13.25 VCC + 1 VCC + 1 0.8 0.2 70 UNIT V V V V V C
TA
Operating free-air temperature
TA
Operating free-air temperature
- 40
70
C
NOTES: 2. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied.
electrical characteristics over full ranges of operating conditions
PARAMETER VOH VOL II IO IPP1 IPP2 ICC1 High level dc output voltage High-level Low-level Low level dc output voltage Input current (leakage) Output current (leakage) VPP supply current VPP supply current (during program pulse) VCC supply current (standby) TTL-input level CMOS-input level TEST CONDITIONS IOH = - 2.5 mA IOH = - 20 A IOL = 2.1 mA IOL = 20 A VI = 0 to 5.5 V VO = 0 to VCC VPP = VCC = 5.5 V VPP = 13 V VCC = 5.5 V, E = VIH VCC = 5.5 V, E = VCC VCC = 5.5 V, E = VIL, tcycle = minimum cycle time, outputs open 1 35 250 100 15 MIN 3.5 VCC - 0.1 0.4 0.1 1 1 10 50 500 250 30 TYP MAX UNIT V V V V A A A mA A A mA
ICC2
VCC supply current (active)
Typical values are at TA = 25C and nominal voltages.
capacitance over recommended temperature, f = 1 MHz
PARAMETER Ci Input capacitance
ranges
of
supply
voltage
and
operating
TYP 6 10 MAX 10 14
free-air
UNIT pF pF
TEST CONDITIONS VI = 0, f = 1 MHz
MIN
CO Output capacitance VO = 0, f = 1 MHz Typical values are at TA = 25C and nominal voltages. Capacitance measurements are made on sample basis only.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4)
PARAMETER ta(A) ta(E) ten(G) tdis tv(A) Access time from address Access time from chip enable Output enable time from G Output disable time from G or E, whichever occurs first Output data valid time after change of address, E, or G, whichever occurs first CL = 100 pF F, 1 Series 74 TTL Load, Input tr 20 ns, In ut Input tf 20 ns TEST CONDITIONS (SEE NOTES 3 AND 4) '27C128-12 MIN MAX 120 120 55 0 0 45 0 0 '27C/PC128-15 MIN MAX 150 150 75 60 ns ns ns ns ns UNIT
TEST CONDITIONS (SEE NOTES 3 AND 4) ta(A) ta(E) ten(G) tdis tv(A) Access time from address Access time from chip enable Output enable time from G Output disable time from Go r E, whichever occurs first Output data valid time after change of address, E, or G, whichever occurs first CL = 100 pF F, 1 Series 74 TTL Load, Input tr 20 ns, In ut Input tf 20 ns
'27C/PC128-20 MIN MAX 200 200 75 0 0 60
27C/PC128-25 MIN MAX 250 250 100 0 0 60
UNIT ns ns ns ns ns
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming:VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25C (see Note 3)
PARAMETER tdis(G) ten(G) Output disable time from G Output enable time from G MIN 0 NOM MAX 130 150 UNIT ns ns
recommended timing requirements for programming: VCC = 6.5 V and VPP =13 V (SNAP! Pulse), TA = 25C (see Note 3)
MIN tw(IPGM) tsu(A) tsu(E) tsu(G) tsu(D) tsu(VPP) tsu(VCC) th(A) th(D) Initial program pulse duration Address setup time E setup time G setup time Data setup time VPP setup time VCC setup time Address hold time Data hold time SNAP! Pulse programming algorithm 95 2 2 2 2 2 2 0 2 NOM 100 MAX 105 UNIT s s s s s s s s s
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (reference page 10). 4. Common test conditions apply for tdis except during programming.
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Output Under Test CL = 100 pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4 V 0.4 V 2V 0.8 V 2V 0.8 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs.
VIH A0-A13 Addresses Valid VIL ta(A) VIH E VIL ta(E) VIH G ten(G) DQ0-DQ7 HI-Z tdis tv(A) VOH Output Valid HI-Z VOL VIL
Figure 3. Read Cycle Timing
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Verify Program A0-A13 tsu(A) DQ0-DQ7 Data In Stable tsu(D) VPP VCC tsu(VPP) VCC VCC VCC tsu(VCC) VIH E VIL tsu(E) PGM tsu(G) tw(IPGM) G VIL tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. 13-V VPP and 6.5-V VCC for SNAP! Pulse programming. ten(G) VIH VIL th(D) VIH Address Stable th(A) Data Out Valid tdis(G) VPP VIH / VOH VIL / VOL Address N+1 VIH VIL
Figure 4. Program Cycle Timing
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
device symbolization
This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the data sheet revision code "B" as shown below.
TI FML TMS27PC128
TMS 27C128
B L X P YY WW
B
L
X
P
YY
WW
Data Sheet Revision Code Wafer Fab Code Die Revision Code Assembly Site Code Year of Manufacture Month of Manufacture
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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E-OCTOBER 1984-REVISED JANUARY 1993
TYPICAL TMS27C/PC128 CHARACTERISTICS
STANDBY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.50 VCC = 5 V 1.25 1.00 0.75 0.50 -75 -50 -25 STANDBY SUPPLY CURRENT vs SUPPLY VOLTAGE 1.50 TA = 25 C 1.25 1.00 0.75 0.50 4.25
I CC1 --Standby Supply Current (Normalized)
0
25
50
75
100 125
I CC1 --Standby Supply Current (Normalized)
4.5
4.75
5
5.25
5.5
5.75
TA -- Free-Air Temperature -- C ACTIVE SUPPLY CURRENT vs FREE-AIR TEMPERATURE I CC2 -- Active Supply Current (Normalized) 1.50 VCC = 5 V 1.25 1.00 0.75 0.50 -75 -50 -25
VCC -- Supply Voltage -- V ACTIVE SUPPLY CURRENT vs SUPPLY VOLTAGE 1.50 1.25 1.00 0.75 0.50 4.25 TA = 25 C f = Max
0
25
50
75
100 125
I CC2 -- Active Supply Current (Normalized)
4.5
4.75
5
5.25
5.5
5.75
TA -- Free-Air Temperature -- C ACCESS TIME vs FREE-AIR TEMPERATURE 1.50 VCC = 5 V TA -- Acctss Time (Normalized) TA -- Access Time (Normalized) 1.25 1.00 0.75 0.50 -75 -50 -25 1.25 1.00 0.75 0.50 4.25 1.50
VCC -- Supply Voltage -- V ACCESS TIME vs SUPPLY VOLTAGE TA = 25 C
0
25
50
75
100 125
4.5
4.75
5
5.25
5.5
5.75
TA -- Free-Air Temperature -- C
VCC -- Supply Voltage -- V
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Copyright (c) 1998, Texas Instruments Incorporated

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