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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
D D D D D D D D D D
Organization TM124MBK36F . . . 1 048 576 x 36 TM248NBK36F . . . 2 097 152 x 36 Single 5-V Power Supply (10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Socket TM124MBK36F - Utilizes Two 16-Megabit and One 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248NBK36F - Utilizes Four 16-Megabit and Two 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period . . . 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
D D
Presence Detect Performance Ranges:
ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns
D D D D
'124MBK36F-60 '124MBK36F-70 '124MBK36F-80 '248NBK36F-60 '248NBK36F-70 '248NBK36F-80
Low Power Dissipation Operating Free-Air Temperature Range: 0C to 70C Gold-Tabbed Versions Available: - TM124MBK36F - TM248NBK36F Tin-Lead (Solder) Tabbed Versions Available: - TM124MBK36U - TM248NBK36U
description TM124MBK36F
The TM124MBK36F is a 4-MByte dynamic random-access memory (DRAM) organized as four times 1 048 576 x 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of two TMS418160DZ, 1 048 576 x 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead ( SOJ) package and one TMS44460DJ, 1 048 576 x 4-bit DRAM in a 24 / 26-lead plastic small-outline J-lead ( SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM124MBK36F SIMM is available in the single-sided BK leadless module for use with sockets.
TM248NBK36F
The TM248NBK36F is an 8-MByte DRAM organized as four times 2 097 152 x 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of four TMS418160DZ, 1 048 576 x 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead ( SOJ) package and two TMS44460DJ, 1 048 576 x 4-bit DRAMs, each in a 24 / 26-lead plastic small-outline (SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM248NBK36F SIMM is available in the double-sided BK leadless module for use with sockets.
operation
The TM124MBK36F operates as two TMS418160DZs and one TMS44460DJ connected as shown in the functional block diagram and NO TAG. The TM248NBK36F operates as four TMS418160DZs and two TMS44460DJs connected as shown in the functional block diagram and NO TAG. The common I / O feature dictates the use of early write cycles to prevent contention on D and Q.
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
BK SINGLE-IN-LINE MEMORY MODULE (TOP VIEW)
TM124MBK36F (SIDE VIEW)
TM248NBK36F (SIDE VIEW)
VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 RAS3 RAS2 DQ26 DQ8 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(TM248NBK36 only)
PIN NOMENCLATURE A0 - A9 CAS0 - CAS3 DQ0 - DQ35 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM124MBK36F 70 ns 60 ns 80 ns TM248NBK36F 70 ns 60 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) VSS VSS VSS NC NC NC PD3 (69) NC VSS NC NC VSS NC PD4 (70) VSS NC NC VSS NC NC
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 DQ9 - DQ16 DQ17 DQ18 - DQ25 DQ26 DQ27 - DQ34 DQ35 RASx SIDE 1 RAS0 RAS2 RAS0 RAS2 RAS2 RAS2 RAS2 RAS2 SIDE 2 RAS1 RAS3 RAS1 RAS3 RAS3 RAS3 RAS3 RAS3 CASx CAS0 CAS0 CAS1 CAS1 CAS2 CAS2 CAS3 CAS3
Side 2 applies to the TM248NBK36F only.
single in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124MBK36F and TM248NBK36F: Nickel plate and gold plate over copper Contact area for TM124MBK36U and TM248NBK36U: Nickel plate and tin / lead over copper
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
functional block diagram [TM124MBK36F and TM248NBK36F, side 1]
A0 - A9 RAS0 W 10 10 RAS2 1M x 16 A0 - A9 DQ0 - DQ7 RAS W LCAS DQ8 - UCAS DQ15 10 1M x 16 A0 - A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15 1M x 4 A0 - A9 RAS W CAS1 CAS2 CAS3 CAS4
8
D0 - D7 D9 - D16 CAS2 CAS3
8 8
D18 - D25 D27 - D34
CAS0 CAS1
8
10
CAS0 CAS1 CAS2 CAS3
DQ1 DQ2 DQ3 DQ4
DQ8 DQ17 DQ26 DQ35
functional block diagram [TM248NBK36F, side 2]
A0 - A9 RAS1 W 10 10 RAS3 1M x 16 A0 - A9 DQ0 - RAS DQ7 W LCAS DQ8 - UCAS DQ15 10 1M x 16 A0 - A9 DQ0 - DQ7 RAS W LCAS DQ8 - UCAS DQ15 1M x 4 A0 - A9 RAS W CAS1 CAS2 CAS3 CAS4
8
D9 - D16 D0 - D7 CAS3 CAS2
8
D27 - D35 D18 - D25
CAS1 CAS0
8
8
10
CAS0 CAS1 CAS2 CAS3
DQ1 DQ2 DQ3 DQ4
DQ8 DQ17 DQ26 DQ35
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation TM124MBK36F, TM124MBK36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W TM248NBK36F, TM248NBK36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, tPC = MIN, CAS cycling RAS low, '124MBK36F - 60 MIN 2.4 0.4 10 10 MAX '124MBK36F - 70 MIN 2.4 0.4 10 10 MAX '124MBK36F - 80 MIN 2.4 0.4 10 10 MAX UNIT V V A A
IO
Output current (leakage) Read- or write-cycle current
ICC1
285
250
220
mA
6
6
6
mA
ICC2
Standby current
3
3
3
mA
ICC3
Average refresh current (RAS only or CBR)
285
250
220
mA
ICC4
Average page current
250
220
190
mA
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, CAS high VCC = 5.5 V, Minimum cycle '248NBK36F - 60 MIN 2.4 0.4 10 20 391 MAX '248NBK36F - 70 MIN 2.4 0.4 10 20 256 MAX '248NBK36F - 80 MIN 2.4 0.4 10 20 226 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
12
12
12
mA
6
6
6
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
570
500
440
mA
ICC4
256
226
196
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Input capacitance, address inputs Input capacitance, RAS inputs capacitance Input capacitance, CAS inputs Input capacitance, write-enable input RAS2, RAS3 RAS0, RAS1 '124MBK36F MIN MAX 15 14 7 14 21 7 '248NBK36F MIN MAX 30 14 7 28 42 14 UNIT pF pF pF pF pF
Co(DQ) Output capacitance on DQ pins NOTE 5: Bias on pins under test is 0 V.
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tRAC tCPA tCLZ tOH Access time from column address Access time from CAS low Access time from RAS low Access time from column precharge CAS to output in low-impedance state Output disable time from start of CAS high 0 3 0 15 '124MBK36F - 60 '248NBK36F - 60 MIN MAX 30 15 60 35 0 3 0 18 '124MBK36F - 70 '248NBK36F - 70 MIN MAX 35 18 70 40 0 3 0 20 '124MBK36F - 80 '248NBK36F - 80 MIN MAX 40 20 80 45 ns ns ns ns ns ns ns UNIT
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'124MBK36F - 60 '248NBK36F - 60 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCAH tRHCP tDH tRAH tRCH tRRH tWCH tWRH Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high (precharge) Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high before RAS low (CBR refresh only) Hold time, column address after CAS low Hold time, RAS high from CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) 110 40 60 60 15 10 40 10 0 0 0 0 15 15 0 10 10 35 10 10 0 0 10 10 100 000 10 000 10 000 MAX '124MBK36F - 70 '248NBK36F - 70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 15 40 15 10 0 0 15 10 100 000 10 000 10 000 MAX '124MBK36F - 80 '248NBK36F - 80 MIN 150 50 80 80 20 10 60 10 0 0 0 0 20 20 0 10 15 45 15 10 0 0 15 10 100 000 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be tCP. 9. Either tRRH or tRCH must be satisfied for a read cycle.
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TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE
SMMS650A - APRIL 1995 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'124MBK36F - 60 '248NBK36F - 60 MIN tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Refresh time interval Transition time 3 10 5 60 5 15 30 30 20 0 15 16 30 3 45 30 MAX '124MBK36F - 70 '248NBK36F - 70 MIN 10 5 70 5 15 35 35 20 0 18 16 30 3 52 35 MAX '124MBK36F - 80 '248NBK36F - 80 MIN 10 5 80 5 15 40 40 20 0 20 16 30 60 40 MAX ns ns ns ns ns ns ns ns ns ns ms ns UNIT
NOTE 10: The maximum value is specified only to assure access time.
device symbolization (TM124MBK36F illustrated)
TM124MBK36F
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
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Copyright (c) 1998, Texas Instruments Incorporated

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