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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
D D D D D D D D D D
Organization TM497MBM36A . . . 4 194 304 x 36 TM893NBM36A . . . 8 388608 x 36 Single 5-V Power Supply (10% Tolerance) 72-Pin Leadless Single In-Line Memory Module (SIMM) for Use With Sockets TM497MBM36A - Utilizes Eight 16-Megabit and Four 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM893NBM36A - Utilizes Sixteen 16-Megabit and Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2 048 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
D D D
Present Detect Operating Free-Air Temperature Range 0C to 70C Performance Ranges:
ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns
D D
'497MBM36A-60 '497MBM36A-70 '497MBM36A-80 '893NBM36A-60 '893NBM36A-70 '893NBM36A-80
Gold-Tabbed Versions Available: TM497MBM36A TM893NBM36A Tin-Lead (Solder)-Tabbed Versions Available: TM497MBM36Q TM893NBM36Q
description
TM497MBM36A The TM497MBM36A is a 16-megabyte dynamic random-access memory ( DRAM) organized as four times 4 194 304 x 9 (bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ 4 194 304 x 4-bit DRAMs, each in a 24 / 26-lead plastic small-outline J-lead (SOJ) package, and four TMS44100DJ 4 194 304 x 1-bit DRAMs, each in a 20 / 26-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS44100DJ are described in the TMS417400 and TMS44100 data sheets, respectively. The TM497MBM36A SIMM is available in the single-sided, BM leadless module for use with sockets. TM893NBM36A The TM893NBM36A is a 32-megabyte DRAM organized as four times 8 388 608 x 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417400DJ 4 194 304 x 4-bit DRAMs, each in a 24 / 26-lead plastic SOJ package, and eight TMS44100DJ 4 194 304 x 1-bit DRAMs, each in a 20 / 26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS44100DJ are described in the TMS417400 and TMS44100 data sheets, respectively. The TM893NBM36A SIMM is available in the double-sided, BM leadless module for use with sockets.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
operation
TM497MBM36A The TM497MBM36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q. TM893NBM36A The TM893NBM36A operates as sixteen TMS417400DJs and eight TMS44100DJs connected as shown in the functional block diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms, and, during this period, each of the 2 048 rows must be strobed with RAS in order to retain data. Address line A10 must be used as the most significant refresh address line (lowest frequency) to ensure correct refresh for both TMS417400 and TMS44100. Address lines A0 - A9 must be refreshed every 16 ms as required by the TMS44100 DRAM. To conserve power, CAS can remain high during the refresh sequence. power up To achieve proper operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles must include at least one refresh (RAS-only or CBR-refresh) cycle. Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 DQ9 - DQ16 DQ17 DQ18 - DQ25 DQ26 DQ27 - DQ34 DQ35 RASx SIDE 1 RAS0 RAS0 RAS2 RAS2 SIDE 2 RAS1 RAS1 RAS3 RAS3 CASx CAS0 CAS1 CAS2 CAS3
Side 2 applies to the TM893NBM36A.
single in-line memory module and components
PC substrate: 1, 27 0,1 mm (0.05 inch) nominal thickness; inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497MBM36A and TM893NBM36A: Nickel plate and gold plate over copper Contact area for TM497MBM36Q and TM893NBM36Q: Nickel plate and tin / lead over copper
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
BM SINGLE IN-LINE PACKAGE ( TOP VIEW )
TM497MBM36A ( SIDE VIEW )
TM893NBM36A ( SIDE VIEW )
Reference
VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 RAS3 RAS2 DQ26 DQ8 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A10 CAS0 - CAS3 DQ0 - DQ35 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM497MBM36A 70 ns 60 ns 80 ns TM893NBM36A 70 ns 60 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) NC NC NC VSS VSS VSS PD3 (69) NC VSS NC NC VSS NC PD4 (70) VSS NC NC VSS NC NC
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SMMS653 - MAY 1995
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
functional block diagram (TM497MBM36A and TM893NBM36A, side 1)
11 RAS2
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Template Release Date: 7-11-94
A0 - A10 RAS0 W CAS0
CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
DQ0 - DQ3
DQ9 - DQ12
DQ18 - DQ21
DQ27 - DQ30
11
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ4 - DQ7
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ13 - DQ16
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ22 - DQ25
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
DQ31 - DQ34
11
11
11
11
DQ8
DQ17
DQ26
DQ35
functional block diagram (TM893NBM36A, side 2)
11 RAS3
A0 - A10 RAS1 W CAS0
CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
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DQ0 - DQ3
DQ9 - DQ12
DQ18 - DQ21
DQ27 - DQ30
11
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ4 - DQ7
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ13 - DQ16
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ22 - DQ25
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
DQ31 - DQ34
11
11
11
11
DQ8
DQ17
DQ26
DQ35
SMMS653 - MAY 1995
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM497MBM36A, TM497MBM36Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 W TM893NBM36A, TM893NBM36Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '497MBM36A - 60 MIN 2.4 0.4 10 10 1300 MAX '497MBM36A - 70 MIN 2.4 0.4 10 10 1160 MAX '497MBM36A - 80 MIN 2.4 0.4 10 10 1040 MAX UNIT V V A A mA
Minimum cycle
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
24
24
24
mA
12
12
12
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average page current
1300
1160
1040
mA
ICC4
920
800
680
mA
For test conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (one RAS active, see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '893NBM36A - 60 MIN 2.4 0.4 20 20 MAX '893NBM36A - 70 MIN 2.4 0.4 20 20 MAX '893NBM36A - 80 MIN 2.4 0.4 20 20 MAX UNIT V V A A
Minimum cycle
1324
1184
1064
mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS-only refresh); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
48
48
48
mA
24
24
24
mA
ICC3
Average refresh current (RAS only or CBR, see Note 3) Average page current (one RAS active, see Note 4)
1324
1184
1064
mA
ICC4
944
824
704
mA
For test conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended supply voltage range and operating free-air temperature range, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Co(DQ) (DQ) Input capacitance, A0 - A10 Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, write-enable input Output capacitance DQ pins Parity pins '497MBM36A MIN MAX 60 42 21 84 7 12 '893NMB36A MIN MAX 120 42 42 168 14 24 UNIT pF pF pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tRAC tCPA tCLZ tOFF Access time from column address Access time from CAS low Access time from RAS low Access time from column precharge CAS low to output in the low-impedance state Output disable time after CAS high (see Note 6) 0 0 3 15 '497MBM36A - 60 '893NBM36A - 60 MIN MAX 30 15 60 35 0 0 3 18 '497MBM36A - 70 '893NBM36A - 70 MIN MAX 35 18 70 40 0 0 3 20 '497MBM36A - 80 '893NBM36A - 80 MIN MAX 40 20 80 45 ns ns ns ns ns ns ns UNIT
tOH Output disable time, start of CAS high NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'497MBM36A - 60 '893NBM36A - 60 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCAH tRHCP tDH tRAH tRCH tRRH tWCH tWRH Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high before RAS low (CBR refresh only) Hold time, column address after CAS low Hold time, RAS high from CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) 110 40 60 60 15 10 40 10 0 0 0 0 15 15 0 10 10 35 10 10 0 0 10 10 100 000 10 000 10 000 MAX '497MBM36A - 70 '893NBM36A - 70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 15 40 15 10 0 0 15 10 100 000 10 000 10 000 MAX '497MBM36A - 80 '893NBM36A - 80 MIN 150 50 80 80 20 10 60 10 0 0 0 0 20 20 0 10 15 45 15 10 0 0 15 10 100 000 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
NOTES: 7. All cycle times assume tT = 5 ns. 8. To assure tPC min, tASC should be tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle.
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SMMS653B - MAY 1995 - REVISED JULY 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'497MBM36A - 60 '893NBM36A - 60 MIN tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR refresh only) Delay time, CAS low to RAS high Refresh time interval Transition time 3 10 5 60 5 15 30 30 20 0 15 32 30 3 45 30 MAX '497MBM36A - 70 '893NBM36A - 70 MIN 10 5 70 5 15 35 35 20 0 18 32 30 3 52 35 MAX '497MBM36A - 80 '893NBM36A - 80 MIN 10 5 80 5 15 40 40 20 0 20 32 30 60 40 MAX ns ns ns ns ns ns ns ns ns ns ms ns UNIT
NOTE 10: The maximum value is specified only to assure access time.
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TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B - MAY 1995 - REVISED JULY 1995
MECHANICAL DATA
BM (R-PSIM-N72) SINGLE/DOUBLE-SIDED IN-LINE MEMORY MODULE
4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP
0.054 (1,37) 0.047 (1,19)
1.305 (33,15) 1.295 (32,89)
0.050 (1,27) 0.040 (1,02) TYP
0.128 (3,25) 0.120 (3,05)
0.010 (0,25) MAX 0.400 (10,16) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX
4088175/A 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
device symbolization (TM497MBM36A illustrated)
TM497MBM36A
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
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Copyright (c) 1998, Texas Instruments Incorporated

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