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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
D D D D D D D D D D
Organization - TM497BBK32H / I: 4 194 304 x 32 - TM893CBK32H / I: 8 388 608 x 32 Single 5-V Power Supply (10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets TM497BBK32H/ I - Uses Eight 16M-Bit Dynamic Random-Access Memory (DRAM) Devices in Plastic Small-Outline J-Lead (SOJ) Packages TM893CBK32H/ I - Uses Sixteen 16M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 32 ms (2 048 Cycles) All Inputs, Outputs, Clocks Fully TTL-Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh
D D
Presence Detect Performance Ranges:
ACCESS ACCESS ACCESS TIME TIME TIME tRAC tAA tCAC (MAX) '497BBK32H / I-50 50 ns '497BBK32H / I-60 60 ns '497BBK32H / I-70 70 ns '893CBK32H / I-50 50 ns '893CBK32H / I-60 60 ns '893CBK32H / I-70 70 ns (MAX) 25 ns 30 ns 35 ns 25 ns 30 ns 35 ns (MAX) 13 ns 15 ns 18 ns 13 ns 15 ns 18 ns READ OR WRITE CYCLE (MIN) 90 ns 110 ns 130 ns 90 ns 110 ns 130 ns
D D D D
Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C Gold-Tabbed Version Available: TM497BBK32H, TM893CBK32H Tin-Lead (Solder-) Tabbed Version Available: TM497BBK32I, TM893CBK32I
description
The TM497BBK32H/I is a 16M-byte dynamic random-access memory (DRAM) device organized as 4 x 4 194 304 x 8 bits in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400ADJ, 4 194 304 x 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400ADJ is described in the TMS417400A data sheet (literature number SMKS889). The TM497BBK32H/I SIMM is available in the single-sided BK leadless module for use with sockets. The TM497BBK32H/ I features RAS access times of 50, 60, and 70 ns. This device is characterized for operation from 0C to 70C. The TM893CBK32H / I is a 32M-byte DRAM organized as 4 8 388 608 x 8 bits in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417400ADJ, 4 194 304 x 4-bit DRAMs. The TM893CBK32H / I SIMM is available in the double-sided BK leadless module for use with sockets. The TM893CBK32H/ I features RAS access times of 50, 60, and 70 ns. This device is characterized for operation from 0C to 70C.
operation
The TM497BBK32H / I operates as eight TMS417400ADJs connected as shown in the functional block diagram and in Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
operation (continued)
The TM893CBK32H / I operates as sixteen TMS417400ADJs connected as shown in the functional block diagram and in Table 2. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. Table 1 and Table 2 show TM497BBK32H / I and TM389CBK32H / I data block configurations in reference to RAS and CAS interfacing. Table 1. TM497BBK32H / I Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 RASx RAS0 RAS0 RAS2 RAS2 CASx CAS0 CAS1 CAS2 CAS3
Table 2. TM893CBK32H / I Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 RASx Side 1 RAS0 RAS0 RAS2 RAS2 Side 2 RAS1 RAS1 RAS3 RAS3 CASx CAS0 CAS1 CAS2 CAS3
single-in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497BBK32H and TM893CBK32H: Nickel plate and gold plate over copper Contact area for TM497BBK32I and TM893CBK32I: Nickel plate and tin-lead over copper refresh The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with RAS to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle.
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
BK SINGLE-IN-LINE PACKAGE ( TOP VIEW )
TM497BBK32H / I ( SIDE VIEW )
TM893CBK32H / I ( SIDE VIEW )
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A10 CAS0 - CAS3 DQ0 - DQ31 NC PD1 - PD4 RAS0 - RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 50 ns TM497BBK32H / I 60 ns 70 ns 50 ns TM893CBK32H / I 60 ns 70 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) NC NC NC VSS VSS VSS PD3 (69) VSS NC VSS VSS NC VSS PD4 (70) VSS NC NC VSS NC NC
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SMMS675A - MARCH 1997 - REVISED APRIL 1997
TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
functional block diagram of TM497BBK32H/I
A0 - A10 RAS0 W CAS0 11 RAS2 CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
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Template Release Date: 7-11-94
DQ0 - DQ3
DQ8 - DQ11
DQ16 - DQ19
DQ24 - DQ27
11
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ4 - DQ7
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ12 - DQ15
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
11
DQ20 - DQ23
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
DQ28 - DQ31
functional block diagram of TM893CBK32H/I side 1
A0 - A10 RAS0 W CAS0 11 RAS2 CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4
DQ0 - DQ3 11
DQ8 - DQ11 11
DQ16 - DQ19 11
DQ24 - DQ27
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
DQ4 - DQ7
DQ12 - DQ15
DQ20 - DQ23
DQ28 - DQ31
side 2
A0 - A10 RAS1 W CAS0 11 RAS3 CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4 4M x 4 A0 - A10 RAS W CAS OE DQ1- DQ4
SMMS675A - MARCH 1997 - REVISED APRIL 1997
DQ0 - DQ3 11
DQ8 - DQ11
DQ16 - DQ19 11
DQ24 - DQ27
11
DQ4 - DQ7
DQ12 - DQ15
DQ20 - DQ23
DQ28 - DQ31
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '497BBK32H / I-50 MIN 2.4 0.4 10 10 MAX '497BBK32H / I-60 MIN 2.4 0.4 10 10 MAX '497BBK32H / I-70 MIN 2.4 0.4 10 10 MAX UNIT V V A A
Minimum cycle
1 040
880
800
mA
ICC2
Standby current
VIH = 2.4 V (TTL), After one memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After one memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN, CAS cycling
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
1 040
880
800
mA
ICC4
720
560
480
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, CASx high VCC = 5.5 V, VO = 0 V to VCC, '893CBK32H / I-50 MIN 2.4 0.4 20 20 MAX '893CBK32H / I-60 MIN 2.4 0.4 20 20 MAX '893CBK32H / I-70 MIN 2.4 0.4 20 20 MAX UNIT V V A A
Minimum cycle
1048
888
808
mA
ICC2
Standby current
VIH = 2.4 V (TTL), After one memory cycle, RASx and CASx high VIH = VCC - 0.2 V (CMOS), After one memory cycle, RASx and CASx high VCC = 5.5 V, RASx cycling, (RASx only); Minimum cycle CASx low (CBR) CASx high RASx low after VCC = 5.5 V, RASx low, tPC = MIN, CASx cycling
32
32
32
mA
16
16
16
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
2080
1760
1600
mA
ICC4
1440
1120
960
mA
For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(R) Ci(C) Ci(W) Co(DQ) Input capacitance, address inputs Input capacitance, RAS inputs Input capacitance, CAS inputs Input capacitance, write-enable input Output capacitance on DQ pins TM497BBK32H / I MIN MAX 50 33 17 66 9 TM893CBK32H / I MIN MAX 80 28 28 112 14 UNIT pF pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOH Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low-impedance state Output disable time from start of CAS high 0 3 0 13 '497BBK32H / I-50 '893CBK32H / I-50 MIN MAX 25 13 30 50 0 3 0 15 '497BBK32H / I-60 '893CBK32H / I-60 MIN MAX 30 15 35 60 0 3 0 18 '497BBK32H / I-70 '893CBK32H / I-70 MIN MAX 35 18 40 70 ns ns ns ns ns ns ns UNIT
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
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SMMS675A - MARCH 1997 - REVISED APRIL 1997
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'497BBK32H / I-50 '893CBK32H / I-50 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCAH tRHCP tDH tRAH tRCH tRRH tWCH tWRH tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page-mode, RAS low Pulse duration, non-page-mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W-low before CAS high Setup time, W-low before RAS high Setup time, W-low before CAS low Setup time, W-high before RAS low (CBR refresh only) Hold time, column address after CAS low Hold time, RAS high after CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low (CBR only) Delay time, CAS low to RAS high Refresh time interval Transition time 2 All cycles assume tT = 5 ns. To assure tPC min, tASC should be greater than or equal to tCP. Either tRRH or tRCH must be satisfied for a read cycle. The maximum value is specified only to ensure access time. 90 35 50 50 13 8 30 10 0 0 0 0 13 13 0 10 10 30 10 8 0 0 10 10 10 5 50 5 13 25 25 18 5 13 32 30 2 37 25 100 000 10 000 10 000 MAX '497BBK32H / I-60 '893CBK32H / I-60 MIN 110 40 60 60 15 10 40 10 0 0 0 0 15 15 0 10 10 35 10 10 0 0 10 10 10 5 60 5 15 30 30 20 5 15 32 30 2 45 30 100 000 10 000 10 000 MAX '497BBK32H / I-70 '893CBK32H / I-70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 15 40 15 10 0 0 15 10 10 5 70 5 15 35 35 20 5 18 32 30 52 35 100 000 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns UNIT
NOTES: 7. 8. 9. 10.
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TM497BBK32H, TM497BBK32I 4194304 BY 32-BIT TM893CBK32H, TM893CBK32I 8388608 BY 32-BIT DYNAMIC RAM MODULES
SMMS675A - MARCH 1997 - REVISED APRIL 1997
device symbolization
TM497BBK32H
-SS
YYMMT
YY MM T -SS
= Year Code = Month Code = Assembly Site Code = Speed Code
NOTE A: The location of the part number may vary.
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SMMS675A - MARCH 1997 - REVISED APRIL 1997
MECHANICAL DATA
BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE
4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP
0.054 (1,37) 0.047 (1,19)
1.005 (25,53) 0.995 (25,27)
0.050 (1,27) 0.040 (1,02) TYP
0.128 (3,25) 0.120 (3,05)
0.010 (0,25) MAX 0.400 (10,16) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM)
4040197 / B 02/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
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Copyright (c) 1998, Texas Instruments Incorporated

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