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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
D
D D D D D D D
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 'xTTxxJPN-8 'xTTxxJPN-8A 8 ns 8 ns 10 ns 10 ns
ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 6 ns 6 ns 6 ns 7.5 ns
REFRESH INTERVAL tREF 64 ms 64 ms
description
The TM8TT64JPN is a 64M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695). The TM16TT64JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695). The TM8TT72JPN is a 64M-byte, 168-pin DIMM. The DIMM is composed of nine TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695). The TM16TT72JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS664814ADGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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Organization: - TM8TT64JPN . . . 8 388 608 x 64 Bits - TM16TT64JPN . . . 16 777 216 x 64 Bits - TM8TT72JPN . . . 8 388 608 x 72 Bits - TM16TT72JPN . . . 16 777 216 x 72 Bits Designed for 100-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM8TT64JPN -- Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M x 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM16TT64JPN -- Uses Sixteen 64M-Bit SDRAMs (8M x 8-Bit) in Plastic TSOPs TM8TT72JPN -- Uses Nine 64M-Bit SDRAMs (8M x 8-Bit) in Plastic TSOPs TM16TT72JPN -- Uses Eighteen 64M-Bit SDRAMs (8M x 8-Bit) in Plastic TSOPs Performance Ranges:
D D D D D D D D D D D
Single 3.3-V Power Supply (10% Tolerance) Byte-Read/Write Capability High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Supports Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
operation
The TM8TT64JPN operates as eight TMS664814DGE devices that are connected as shown in the TM8TT64JPN functional block diagram. The TM16TT64JPN operates as 16 TMS664814ADGE devices connected as shown in the TM16TT64JPN functional block diagram. The TM8TT72JPN operates as nine TMS664814ADGE devices that are connected as shown in the TM8TT72JPN functional block diagram. The TM16TT72JPN operates as 18 TMS664814ADGE devices connected as shown in the TM16TT72JPN functional block diagram.
PRODUCT PREVIEW
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM8TT64JPN ( SIDE VIEW )
TM16TT64JPN ( SIDE VIEW ) A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S[0:3] SA[0:2] SCL SDA VDD VSS WE WP
PIN NOMENCLATURE Row Address Inputs Column Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Check Bit In/Check Bit Out Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable Write Protect
1
10 11
40
41
84
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 A12/BA1 VDD VDD CK0 NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PIN NAME VSS NC S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 A13/BA0 A11 VDD CK1 NC NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS CKE0 S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
PRODUCT PREVIEW
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM8TT64JPN
S0 RC CS CS CK: U0, U4 CK0 U4 CK2 RC CK: U1, U5 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 DQMB4 R DQ[32:39] 8 DQM DQ[0:7] RC CK: U2, U6 RC CK: U3, U7 RC CS CS RC CK3 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] U1 DQMB5 R DQ[40:47] 8 DQ[0:7] R = 10 RC = 10 C = 10 pF DQM U5 C C
S2 CS CS VDD U[0:7] Two 0.1 F per SDRAM VSS U[0:7]
DQMB2 R DQ[16:23] 8
DQM DQ[0:7]
U2
DQMB6 R DQ[48:55] 8
DQM
U6
DQ[0:7]
CS
CS
DQMB3 R DQ[24:31] 8
DQM DQ[0:7]
U3
DQMB7 R DQ[56:63] 8
DQM DQ[0:7]
U7
SCL WP
SPD EEPROM SDA A0 SA0 A1 SA1 A2 SA2
RAS CAS WE CKE0 A[0:13]
RAS: SDRAM U[0:7] CAS: SDRAM U[0:7] WE: SDRAM U[0:7] CKE: SDRAM U[0:7] A[0:13]: SDRAM U[0:7]
47 k
LEGEND: CS = Chip select SPD = Serial Presence Detect Additional 3.3 pF capacity is used to balance loads among clocks.
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CK1
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
functional block diagram for the TM16TT64JPN
S1 S0 CS CS CS CS VSS U0 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] UB0 DQM DQ[0:7] DQMB4 R DQ[32:39] 8 U4 DQM DQ[0:7] UB4 DQM DQ[0:7] VDD CS CS CS CS CKE1 CKE0 RAS CAS WE 10 k CKE: UB[0:7] CKE: U[0:7] RAS: U[0:7], UB[0:7] CAS: U[0:7], UB[0:7] WE: U[0:7], UB[0:7] A[0:13]: U[0:7], UB[0:7] RC CK0 CS CS CS CS CK1 U2 DQMB2 R DQ[16:23] 8 DQM DQ[0:7] UB2 DQM DQ[0:7] DQMB6 R DQ[48:55] 8 U6 DQM DQ[0:7] UB6 DQM DQ[0:7] CK3 CK2 CK: U0, U4 RC CK: U1, U5 RC CK: UB0, UB4 RC CK: UB1, UB5 RC CK: U2, U6 RC CK: U3, U7 RC CK: UB2, UB6 RC CK: UB3, UB7 SPD EEPROM SCL WP 47 k A0 A1 A2 SDA CS CS CS CS R = 10 Rc = 10 VDD U[0:7], UB[0:7] Two 0.1 F per SDRAM U[0:7], UB[0:7]
U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7]
UB1 DQM DQ[0:7] DQMB5 R DQ[40:47] 8
U5 DQM DQ[0:7]
UB5 DQM DQ[0:7]
PRODUCT PREVIEW
A[0:13]
S3 S2
U3 DQMB3 R DQ[24:31] 8 DQM DQ[0:7]
UB3 DQM DQ[0:7] DQMB7 R DQ[56:63] 8
U7 DQM DQ[0:7]
UB7 DQM DQ[0:7]
SA0 SA1 SA2
Additional 3.3 pF capacity is used to balance loads among clocks.
6
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SMMS700A - APRIL 1998 - REVISED AUGUST 1998
functional block diagram for the TM8TT72JPN
S0 CS DQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 DQMB4 R DQ[32:39] 8 CS DQM DQ[0:7] U4 CK2 CK0 RB U0, U4 RB U1, U5, U8 RC U2, U6 RC U3, U7 CS DQMB1 DQ[8:15] DQM R 8 DQ[0:7] U1 DQMB5 R DQ[40:47] 8 CS DQM DQ[0:7] U5 RC CK3 R = 10 RB = 5 RC = 10 C = 10 pF C RC CK1 C
CS DQMB1 R CB[0:7] S2 CS DQMB2 R DQ[16:23] 8 DQM DQ[0:7] U2 DQMB6 R DQ[48:55] 8 CS DQM DQ[0:7] U6 8 DQM DQ[0:7] U8
VDD
U[0:8] Two 0.1 F per SDRAM
VSS
U[0:8]
CS DQMB3 R DQ[24:31] RAS CAS WE CKE0 A[0:13] 8 DQM DQ[0:7] U3 DQMB7 R DQ[56:63] 8
CS DQM DQ[0:7] U7
RAS: SDRAM U[0:8] SCL CAS: SDRAM U[0:8] WE: SDRAM U[0:8] CKE: SDRAM U[0:8] A[0:13]: SDRAM U[0:8] 47 k WP
SPD EEPROM SDA A0 SA0 A1 SA1 A2 SA2
Additional 3.3 pF capacity is used to balance loads among clocks.
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
functional block diagram for the TM16TT72JPN
S1 S0 CS CS CS CS VSS U0 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] UB0 DQM DQ[0:7] DQMB4 R DQ[32:39] 8 U4 DQM DQ[0:7] UB4 DQM DQ[0:7] R = 10 RC = 10 RB = 5 RB CS CS CS CS CK: U0, U4 CK0 RB CK: U1, U5, U8 U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] UB1 DQM DQ[0:7] DQMB5 R DQ[40:47] 8 U5 DQM DQ[0:7] UB5 DQM DQ[0:7] RC CS CS CK2 CK: U2, U6 RC CK: U3, U7 RC U8 DQMB1 R CB[0:7] 8 DQM DQ[0:7] UB8 DQM DQ[0:7] VDD S3 S2 CS CS CS CS CKE1 CKE0 RAS U2 DQMB2 R DQ[16:23] 8 DQM DQ[0:7] UB2 DQM DQ[0:7] DQMB6 R DQ[48:55] 8 U6 DQM DQ[0:7] UB6 DQM WE DQ[0:7] A[0:13] CS CS CS CS SCL U3 DQMB3 R DQ[24:31] 8 DQM DQ[0:7] UB3 DQM DQ[0:7] DQMB7 R DQ[56:63] 8 U7 DQM DQ[0:7] UB7 DQM DQ[0:7] 47 k WP A0 A1 A2 A[0:13]: U[0:8], UB[0:8] SPD EEPROM SDA WE: U[0:8], UB[0:8] CAS 10 k CKE: UB[0:8] CKE: U[0:8] RAS: U[0:8], UB[0:8] CAS: U[0:8], UB[0:8] CK3 CK: UB2, UB6 RC CK: UB3, UB7 CK1 RB CK: UB0, UB4 RB CK: UB1, UB5, UB8 VDD U[0:8], UB[0:8] Two 0.1 F per SDRAM U[0:8], UB[0:8]
PRODUCT PREVIEW
SA0 SA1 SA2
Additional 3.3 pF capacity is used to balance loads among clocks.
8
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM8TT64JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM16TT64JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W TM8TT72JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W TM16TT72JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS VIH VIH-SPD VIL TA Supply voltage Supply voltage High-level input voltage High-level input voltage for SPD device Low-level input voltage Ambient temperature 2 2 -0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V C V
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(CK) Ci(AC) Ci(CKE) Co Ci(DQMBx) Ci(Sx) Ci/o(SDA) Input capacitance, CK input Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance Input capacitance, DQMBx input Input capacitance, Sx input SDA Input/output capacitance 4 2.5 2.5 'xTTxxJPN MIN 2.5 2.5 MAX 4 5 5 6.5 5 5 9 7 UNIT pF pF pF pF pF pF pF pF
Ci(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
TMxTTxxJPN
PARAMETER VOH VOL II IO ICC1 ICC2P ICC2PS High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) TEST CONDITIONS IOH = - 2 mA IOL = 2 mA 0 V VI VDD + 0.3 V, All other pins = 0 V to VDD 0 V VO VDD +0.3 V, Output disabled Burst length = 1, tRC tRC MIN, , IOH/IOL = 0 mA (See Notes 4, 5, and 6) CAS latency = 2 CAS latency = 3 'xTTxxJPN-8 MIN 2.4 0.4 MAX 'xTTxxJPN-8A MIN 2.4 0.4 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA
"10 "10
115 125 1 1 40 5 8 8 50
"10 "10
95 95 1 1 40 5 8 8 50
Operating current
Precharge standby current in power-down mode Active standby current in y non-power-down mode
CKE VIL MAX, tCK = 15 ns (see Note 7) CKE and CK VIL, MAX, tCK = (see Note 8) CKE VIH MIN, tCK = 15 ns (see Note 7) tCK = (see Note 8) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) CKE and CK VIL MAX, tCK = (see Notes 4 and 8) CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) CKE VIH MIN, CK VIL MAX, tCK = (see Notes 4 and 8) Page burst, IOH/IOL = 0 mA All banks activated, activated nCCD = one cycle (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2
PRODUCT PREVIEW
ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
Active standby current in y power-down mode
Precharge standby current in non-power-down mode
15
15
mA
165
120
mA
ICC4
Burst current
CAS latency = 3 CAS latency = 2 CAS latency = 3
225 150 150
165 150 150
mA mA mA
ICC5
Auto-refresh Auto refresh current
ICC6 Self-refresh current CKE VIL MAX 1 1 mA Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC tRCMIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change once every cycle. 10. Continuous burst access, nCCD = 1 cycle
10
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SMMS700A - APRIL 1998 - REVISED AUGUST 1998
ac timing requirements
'xTTxxJPN-8 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tT tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 Cycle time, CK Cycle time, CK Pulse duration, CK high Pulse duraction, CK low Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out with 50-pF load Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Power down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV,MRS,REFR,or SLFR to ACTV,MRS,REFR,or SLFR command Delay time ACTV command to READ,READ-P,WRT,or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV,MRS,REFR, or SLFR command Delay time,ACTV command in one bank to ACTV command in the other bank Delay time,MRS command to ACTV,MRS,REFR,or SLFR command Final data out of READ-P operation to ACTV,MRS,SLFR,or REFR command Final data in of WRT-P operation to ACTV,MRS,SLFR,or REFR command Transition time Refresh interval Delay time, READ or WRT command to an interrupting command time Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 1 0 1 1 0 2 0 2 2 0 1 2 1 8 48 68 20 20 16 16 tRP -(CL-1)*tCK tRP + 1 tCK 1 5 64 1 0 1 1 0 2 0 2 2 0 1 100 000 CAS latency = 2 CAS latency = 3 3 1 8 2 1 8 48 68 20 20 16 16 tRP - (CL-1)* tCK tRP + 1 tCK 1 5 64 CAS latency = 2 CAS latency = 3 10 8 3 3 6 6 3 1 8 MAX 'xxTTxxJPN-8A MIN 15 8 3 3 7.5 6 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms cycles cycles cycles cycles cycles cycles cycles
All references are made to the rising transition of CK unless otherwise noted. Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
ac timing requirements (continued)
'xTTxxJPN-8 MIN nHZP3 nWCD Delay time, DEAC high-impedance state or DCAB, command to DQ in CAS latency = 3 0 1 MAX 3 0 0 1 'xTTxxJPN-8A MIN MAX 3 0 UNIT cycles cycles cycles
Delay time, WRT command to first data in
nWR Delay time, final data in of WRT operation to DEAC or DCAB command All references are made to the rising transition of CK unless otherwise noted. Specifications in this table represent a single SDRAM device.
PRODUCT PREVIEW
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SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1 -TM8TT64JPN Table 3 -TM8TT72JPN Table 2 -TM16TT64JPN Table 4 -TM16TT72JPN
Table 1. Serial-Presence-Detect Data for the TM8TT64JPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 8 ns tAC = 6 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 10 ns TM8TT64JPN-8 ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 64 bits DATA 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 80h 60h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h LVTTL tCK = 8 ns tAC = 6 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 15 ns TM8TT64JPN-8A ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 64 bits DATA 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 80h 60h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
0Eh
23
Minimum clock cycle time at CL = X - 1
A0h
F0h
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13
PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 1. Serial-Presence-Detect Data for the TM8TT64JPN (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 33 34 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Open Rev. 1.2 95 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 5Fh 9700... 00h Rev. 1.2 196 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h C4h 9700... 00h TM8TT64JPN-8 ITEM tAC = 6 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 16 ns tRAS = 48 ns 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 60h 00h 00h 14h 10h 10h 30h 10h 20h 10h 20h 10h TM8TT64JPN-8A ITEM tAC = 7.5 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 75h 00h 00h 14h 10h 14h 30h 10h 20h 10h 20h 10h
PRODUCT PREVIEW
35 36 - 61 62 63 64 - 71 72 73 - 90 91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
14
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM16TT64JPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 8 ns tAC = 6 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%). Burst read / write, precharge all, auto precharge tCK = 10 ns tAC = 6 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns TM16TT64JPN-8 ITEM 128 bytes 256 bytes SDRAM 12 9 2 banks 64 bits DATA 80h 08h 04h 0Ch 09h 02h 40h 00h 01h 80h 60h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h LVTTL tCK = 8 ns tAC = 6 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%). Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 7.5 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns TM16TT64JPN-8A ITEM 128 bytes 256 bytes SDRAM 12 9 2 banks 64 bits DATA 80h 08h 04h 0Ch 09h 02h 40h 00h 01h 80h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h 60h
22
SDRAM device attributes: general
0Eh
0Eh
23 24 25 26 27 28 29 30
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width
A0h 60h 00h 00h 14h 10h 14h 30h
F0h 75h 00h 00h 1Eh 14h 1Eh 32h
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PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM16TT64JPN (Continued)
BYTE NO. 31 32 33 34 35 36-61 62 63 64 - 71 72 73 - 90 DESCRIPTION OF FUNCTION Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Open Rev. 1.2 96 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 60h 9700... 00h Rev. 1.2 197 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h C5h 9700... 00h TM16TT64JPN-8 ITEM 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 10h 20h 10h 20h 10h TM16TT64JPN-8A ITEM 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 10h 20h 10h 20h 10h
PRODUCT PREVIEW
91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
16
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM8TT72JPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 10 ns tAC = 6 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes tIS = 2 ns TM8TT72JPN-8 ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 72 bits DATA 80h 08h 04h 0Ch 09h 01h 48h 00h 01h 80h 60h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 00h LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 7.5 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes tIS = 2 ns TM8TT72JPN-8A ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 72 bits DATA 80h 08h 04h 0Ch 09h 01h 48h 00h 01h 80h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 00h 60h
22
SDRAM device attributes: general
0Eh
0Eh
23 24 25 26 27 28 29 30 31 32
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time
A0h 60h 00h 00h 14h 10h 14h 30h 10h 20h
F0h 75h 00h 00h 14h 10h 14h 30h 10h 20h
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PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM8TT72JPN (Continued)
BYTE NO. 33 34 35 36 - 61 62 63 64 - 71 72 73 - 90 91 92 DESCRIPTION OF FUNCTION Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Open Rev. 1.2 113 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 71h 9700... 00h Rev. 1.2 214 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h D6h 9700... 00h TM8TT72JPN-8 ITEM tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 10h 20h 10h TM8TT72JPN-8A ITEM tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 10h 20h 10h
PRODUCT PREVIEW
93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
18
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 4. Serial Presence-Detect Data for the TM16TT72JPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%). Burst read / write, precharge all, auto precharge tCK = 10 ns tAC = 6 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes TM16TT72JPN-8 ITEM 128 bytes 256 bytes SDRAM 12 9 2 banks 72 bits DATA 80h 08h 04h 0Ch 09h 02h 48h 00h 01h 80h 60h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 00h LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%). Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 7.5 ns N/A N/A tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes TM16TT72JPN-8A ITEM 128 bytes 256 bytes SDRAM 12 9 2 banks 72 bits DATA 80h 08h 04h 0Ch 09h 02h 48h 00h 01h 80h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 00h 60h
22
SDRAM device attributes: general
0Eh
0Eh
23 24 25 26 27 28 29 30 31
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module
A0h 60h 00h 00h 14h 10h 14h 30h 10h
F0h 75h 00h 00h 14h 10h 14h 30h 10h
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PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM16TT72JPN (Continued)
BYTE NO. 32 33 34 35 36-61 62 63 64 - 71 72 73 - 90 91 DESCRIPTION OF FUNCTION Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Rev. 1.2 114 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 72h 9700... 00h Rev. 1.2 215 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h D7h 9700... 00h TM16TT72JPN-8 ITEM tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 20h 10h 20h 10h TM16TT72JPN-8A ITEM tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 20h 10h 20h 10h
PRODUCT PREVIEW
92 93 - 94 95 - 98 99 - 125 126 - 127 128-166
167-255 Open TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
20
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
device symbolization (TM8TT64JPN)
TM8TT64JPN Unbuffered Key Position YY MM T -SS = = = = 3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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21
PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A - APRIL 1998 - REVISED AUGUST 1998
BUV (R-PDIM-N168)
DUAL-IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.250 (6,35) x 0.089 (2,26) Deep 2 Places Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D)
Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places
0.054 (1,37) 0.046 (1,17)
2 Places
PRODUCT PREVIEW
0.039 (1,00) TYP 0.125 (3,18) 0.118 (3,00) DIA (2 Places) 0.875 (22,23) 2 Places
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.255 (31,88) 1.245 (31,62) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088192/A 01/98
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes depanelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
22
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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