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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
D D D D D D D D
Organization: - TM4SP64KPN . . . 4 194 304 x 64 Bits - TM8SP64KPN . . . 8 388 608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM4SP64KPN -- Uses Four 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (4M x 16-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM8SP64KPN -- Uses Eight 64M-Bit SDRAMs (4M x 16-Bit) in Plastic TSOPs Byte-Read/Write Capability Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 ACCESS TIME CLOCK TO OUTPUT tAC3 tAC3 7 ns 7 ns REFRESH INTERVAL tREF 64 ms
D D D D D D D D D
High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence Detect (SPD) Using EEPROM
'xSP64KPN-10
10 ns
15 ns
description
The TM4SP64KPN is a 32M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of four TMS664164ADGE, 4 194 304 x 16-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664164A data sheet (literature number SMOS695). The TM8SP64KPN is a 64M-byte, 168-pin DIMM. The DIMM is composed of eight TMS664164ADGE, 4 194 304 x 16-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664164A data sheet (literature number SMOS695).
operation
The TM4SP64KPN operates as four TMS664164ADGE devices that are connected as shown in the TM4SP64KPN functional block diagram. The TM8SP64KPN operates as eight TMS664164ADGE devices connected as shown in the TM8SP64KPN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM4SP64KPN ( SIDE VIEW )
TM8SP64KPN ( SIDE VIEW ) A[0:11] A[0:7] A13/BA0 A12/BA1 CAS CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S[0:3] SA[0:2] SCL SDA VDD VSS WE
PIN NOMENCLATURE Row-Address Inputs Column-Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
1
10 11
PRODUCT PREVIEW
40
41
84
2
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NO. 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN A12/BA1 DQMB1 DQMB0 NAME DQ15 VDD DQ14 DQ13 DQ12 DQ10 DQ11 VDD VDD VDD WE VDD DQ4 VSS DQ9 DQ8 DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VSS DQ0 VSS A0 VSS NC CK0 A10 NC NC NC NC A8 A6 A4 A2 S0 NO. 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIN NAME DQMB3 DQMB2
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Pin Assignments
DQ31
DQ30
DQ29
VDD DQ28
DQ27
DQ26
DQ25
VSS DQ24
DQ17
VSS DQ16
VDD NC
VSS NC
NC
NC
NC
NC
S2
NO.
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PIN NAME
DQ42
VSS DQ41
DQ40
DQ39
DQ38
DQ37
VDD DQ36
DQ35
DQ34
DQ33
VSS DQ32
NO.
140
VSS 139AAAAAA DQ48
138
137
136
135
134
133
132
131
130AAAAAA DQMB6
129
128
127
PIN NAME
DQMB7
DQ49
VSS CKE0
VDD NC
NC
NC
NC
NC
S3
SMMS708 - APRIL 1998
PRODUCT PREVIEW
DQ23
DQ22
VSS DQ21
CKE1
VDD DQ20
DQ19
DQ18
VDD
SDA
VSS CK2
SCL
NC
NC
NC
NC
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126 125 124 123 122 121 120 109 108 107 106 105 104 103 102 101 100 119 118 117 116 115 114 113 112 110 111 99 A13/BA0 DQMB5 DQMB4 DQ47 VDD DQ46 DQ45 DQ44 DQ43 VDD CK1 VDD CAS RAS VSS A1 VSS NC A11 NC NC NC NC A9 A7 A5 A3 S1 168 167 166 165 164 163 162 161 160 159 158 157 156AAAAAA DQ59 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 DQ63 DQ62 DQ61 VDD DQ60 DQ58 DQ57 VSS DQ56 DQ55 DQ54 VSS DQ53 VDD DQ52 DQ51 DQ50 VDD VSS CK3 SA2 SA1 SA0 NC NC NC NC
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM4SP64KPN
S0 CS DQMB0 R DQ[0:7] DQMB1 8 DQM U0 DQ[0:7] DQM R DQ[8:15] 8 DQ[0:7] DQ[32:39] DQMB4 R 8 CS DQM U2 DQ[0:7] DQM R DQ[40:47] 8 DQ[0:7] CK3 C R = 10 RC = 10 C = 10 pF CS DQMB2 R DQ[16:23] DQMB3 R DQ[24:31] 8 8 DQM U1 DQ[0:7] DQM DQ[0:7] DQ[48:55] DQMB7 R DQ[56:63] 8 DQMB6 R 8 CS DQM U3 DQ[0:7] DQM VSS DQ[0:7] VDD U[0:3] Two 0.1 F (minimum) per SDRAM U[0:3] CK0 RC CK: U0, U1 RC CK: U2, U3 RC CK1 C DQMB5 RC CK2 C RC
PRODUCT PREVIEW
S2
CKE0 RAS CAS WE A[0:13]
CKE: SDRAM U[0:3] RAS: SDRAM U[0:3] CAS: SDRAM U[0:3] WE: SDRAM U[0:3] A[0:13]: SDRAM U[0:3]
SPD EEPROM SCL A0 SA0 A1 SA1 A2 SA2 SDA
LEGEND: CS = SPD =
Chip select Serial Presence Detect
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
functional block diagram for the TM8SP64KPN
S0 CS DQMB0 R DQ[0:7] DQMB1 R DQ[32:39] S2 CS DQMB2 R DQ[16:23] DQMB3 R DQ[48:55] S0 CS DQMB4 R DQ[8:15] DQMB5 R DQ[40:47] S2 CS DQMB6 DQ[24:31] DQMB7 R DQ[56:63] 8 R 8 DQM U3 8 8 DQM DQ[0:7] DQM DQ[0:7] S3 CS DQM UB3 DQ[0:7] DQM SCL DQ[0:7] DQ[0:7] A0 SA0 A1 SA1 A2 SA2 SPD EEPROM SDA U2 8 8 DQM U1 8 8 DQM DQ[0:7] DQM DQ[0:7] S3 CK3 CS DQM UB1 DQ[0:7] DQM DQ[0:7] S1 CS DQM UB2 DQ[0:7] DQM CKE1 DQ[0:7] CKE0 RAS CAS WE A[0:13] CKE: SDRAM U[0:3] RAS: SDRAM U[0:3], UB[0:3] CAS: SDRAM U[0:3], UB[0:3] WE: SDRAM U[0:3], UB[0:3] A[0:13]: SDRAM U[0:3], UB[0:3] CKE:UB[0:3] VSS VDD 10 k VDD U[0:3], UB[0:3] Two 0.1 F (minimum) per SDRAM U[0:3], UB[0:3] R = 10 RC = 10 C = 10 pF C U0 S1 CS DQM UB0 DQ[0:7] DQM DQ[0:7] CK2 C RC CK1 CK0 RC CK: U0, U1 RC CK: U2, U3 RC CK: UB0, UB1 RC CK: UB2, UB3 RC
DQ[0:7] DQM DQ[0:7]
DQ[0:7] DQM
LEGEND: CS = SPD =
Chip select Serial Presence Detect
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PRODUCT PREVIEW
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM4SP64KPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W TM8SP64KPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
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MIN 3 2 2 0 NOM MAX 3.6 UNIT V V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH-SPD VIL TA High-level input voltage Low-level input voltage Ambient temperature High-level input voltage for SPD device VDD + 0.3 5.5 0.8 70 -0.3 C
recommended operating conditions
PRODUCT PREVIEW
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER TMxSP64KPN MIN 2.5 MAX 4 5 5 5 9 7 UNIT pF pF pF pF pF pF pF
Ci(CK) Ci(AC) Co
Input capacitance, CK input
Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance
2.5AAA pF 5 4 6.5
Ci(CKE)
Ci(DQMBx) Ci(Sx) Ci/o(SDA)
Input capacitance, DQMBx input Input capacitance, Sx input
2.5 2.5
Input/output capacitance, SDA input
Ci(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
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PARAMETER TEST CONDITIONS 'xSP64KPN-10 MIN 2.4 MAX UNIT V V VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) IOH = - 2 mA IOL = 2 mA 0.4 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, Output disabled
TMxSP64KPN
"10 "10
A A
IO
Output current (leakage)
ICC1
Operating current
Burst length = 1, tRC tRC MIN, , IOH/IOL = 0 mA (See Notes 4, 5, and 6)
CAS latency = 2 CAS latency = 3
105 115 1 1 5 5 5
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC2P ICC2PS
Precharge standby current in power down mode power-down
CKE VIL MAX, tCK = 15 ns (see Note 7)
CKE and CK VIL MAX, tCK = (see Note 8)
ICC3P
CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) CKE and CK VIL MAX, tCK = (see Notes 4 and 8)
ICC3PS ICC3N
Active standby current in power-down mode
ICC3NS
Precharge standby current in non power down non-power-down mode
CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) CKE VIH MIN, CK VIL MAX, tCK = (see Notes 4 and 8)
60 10
ICC4
Burst current
Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2 CAS latency = 3
140 200 150 150
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 2 mA Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC MIN 6. Control and address inputs change state only twice during tRC. 7. Control and address inputs change state only once every 30 ns. 8. Control and address inputs do not change (stable). 9. Control and address inputs change only once every cycle. 10. Continuous burst access, nCCD = 1 cycle
w
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PRODUCT PREVIEW
ICC2NAAAAAAAAAAAAA VIH MIN, tCK = 15 ns (see Note 7) CKE Active standby current in non power down mode non-power-down ICC2NS tCK = (see Note 8)
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
ac timing requirements
'xSP64KPN-10 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS Cycle time, CK Cycle time, CK Pulse duration, CK high Pulse duraction, CK low Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Power down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Transition time Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, WRT command to first data in CAS latency = 2 CAS latency = 3 0 1 0 1 1 0 2 0 2 2 3 0 0 1 2 1 8 50 80 30 30 20 20 tRP -(CL-1)*tCK tRP + 1 tCK 1 5 64 CAS latency = 2 CAS latency = 3 3 3 8 CAS latency = 2 CAS latency = 3 15 10 3 3 7 7 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms cycle cycle cycle cycle cycle cycle cycle cycle cycle
PRODUCT PREVIEW
tRC tRCD tRP tRRD tRSA tAPR tAPW tT tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 nWCD
nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle All references are made to the rising transition of CK unless otherwise noted. A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low). NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
8
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1 and Table 2). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Table 1 and Table 2 list the SPD contents as follows: Table 1 -TM4SP64KPN Table 2 -TM8SP64KPN
Table 1. Serial Presence Detect Data for the TM4SP64KPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+/- 10%) Burst read / write, precharge all, auto precharge tCK = 15 ns TM4SP64KPN-10 ITEM 128 bytes 256 bytes SDRAM 12 8 1 bank 64 bits DATA 80h 08h 04h 0Ch 08h 01h 40h 00h 01h A0h 70h 00h 80h 10h 00h 01h 0Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23
Minimum clock cycle time at CL = X - 1
F0h
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9
PRODUCT PREVIEW
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data for the TM4SP64KPN (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 33 34 35 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Open Rev. 1.2 8 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 08h 9700...00h TM4SP64KPN-10 ITEM tAC = 7 ns N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 32M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 70h 00h 00h 1Eh 14h 1Eh 32h 08h 20h 10h 20h 10h
PRODUCT PREVIEW
36 - 61 62 63 64 - 71 72 73 - 90 91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
10
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM8SP64KPN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+/-10%) Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 7 ns N/A N/A TM8SP64KPN-10 ITEM 128 bytes 256 bytes SDRAM 12 8 2 banks 64 bits DATA 80h 08h 04h 0Ch 08h 02h 40h 00h 01h A0h 70h 00h 80h 10h 00h 01h 0Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23 24 25 26
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2
F0h 70h 00h 00h
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11
PRODUCT PREVIEW
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM8SP64KPN (Continued)
BYTE NO. 27 28 29 30 31 32 33 34 35 36-61 62 63 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Vendor-specific data System-integrator-specific data Rev. 1.2 9 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 12h 09h 9700...00h DESCRIPTION OF FUNCTION TM8SP64KPN-10 ITEM tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS =50 ns 32M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 1Eh 14h 1Eh 32h 08h 20h 10h 20h 10h
PRODUCT PREVIEW
64 - 71 72 73 - 90 91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166
167-255 Open TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
12
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TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
device symbolization (TM4SP64KPN)
TM4SP64KPN Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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13
PRODUCT PREVIEW
TM4SP64KPN 4194304 BY 64-BIT TM8SP64KPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS708 - APRIL 1998
MECHANICAL DATA
BR (R-PDIM-N168) DUAL IN-LINE MEMORY MODULE
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP 0.125 (3,18)
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.005 (25,53) 0.995 (25,27) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only)
PRODUCT PREVIEW
0.118 (3,00) DIA 2 Places
4088180/A 07/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes de-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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Copyright (c) 1998, Texas Instruments Incorporated

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