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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
D D D D
D D
Organization: - TM8TU72JPW . . . 8 388 608 x 72 Bits Designed for 100-MHz, 72-Bit 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) With Register for Use With Socket TM8TU72JPW -- Uses Nine 64M-Bit (8M x 8-Bit) SDRAMs in Plastic Thin Small-Outline Package (TSOP), Two SN74ALVC162836 20-Bit Universal Bus Drivers in Thin Shrink Small-Outline Package (TSSOP), and One CDC2510 Phase-Lock Loop (PLL) in TSSOP Single 3.3-V Power Supply (10% Tolerance) Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 6 ns 6 ns 6 ns 7.5 ns REFRESH INTERVAL tREF 64 ms 64 ms
D D D D D D D D D D
Byte-Read/Write Capability High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Supports Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM
'8TU72JPW-8 '8TU72JPW-8A
8 ns 8 ns
10 ns 10 ns
description
The TM8TU72JPW is a 64M-byte, 168-pin registered dual-in-line memory module (DIMM). The registered DIMM is composed of nine TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP); two SN74ALVC162836DGG, 20-bit universal bus drivers, each in a 240-mil, 56-pin thin shrink small-outline package (TSSOP); and one CDC2510 phase-lock loop (PLL) in a 177-mil, 24-pin TSSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695), the SN74ALVC162836 data sheet (literature number SCES129), and the CDC2510 data sheet (literature number SCAS597) for reference.
operation
The TM8TU72JPW operates as nine TMS664814DGE devices that are connected as shown in the TM8TU72JPW functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM8TU72JPW ( SIDE VIEW ) A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS REGE S[0:3] SA[0:2] SCL SDA VDD VSS WE WP
PIN NOMENCLATURE Row-Address Inputs Column-Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Check-Bit In/Check-Bit Out Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Register Enable Chip Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable Write Protect
1
10 11
PRODUCT PREVIEW
40
41
84
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 A12/BA1 VDD VDD CK0 NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PIN NAME VSS NC S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 A13/BA0 A11 VDD CK1 NC NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS CKE0 S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
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DQ49
TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
PRODUCT PREVIEW
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
functional block diagram for the TM8TU72JPW
RS0 CS RDQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 RDQMB4 R DQ[32:39] 8 CS DQM DQ[0:7] U5 R CK2 C CS RDQMB1 DQ[8:15] DQM R 8 DQ[0:7] U1 RDQMB5 R DQ[40:47] 8 CS DQM DQ[0:7] R = 10 C = 10 pF U2 U6 CK3 C R CK1 C R
CS RDQMB1 R CB[0:7] RS2 CS RDQMB2 R DQ[16:23] 8 DQM DQ[0:7] U3 RDQMB6 R DQ[48:55] 8 CS DQM DQ[0:7] U7 8 DQM DQ[0:7]
VDD
U[0:8] One 0.0022 F and one 0.22 F per SDRAM
VSS
U[0:8]
CS RDQMB3 R DQ[24:31] 8 DQM DQ[0:7] U4 RDQMB7 R DQ[56:63] 8
CS DQM DQ[0:7] U8
S0/S2 DQMB[0:7] BA[0:1] A[0:11] RAS CAS CKE0 WE
Register
VDD REGE
10 k
SPD EEPROM SCL RS0/RS2 SDA WP RDQMB[0:7] A0 A1 A2 RBA[0:1] BA[0:1]: SDRAMs U[0:8] RA[0:11] A[0:11]: SDRAMs U[0:8] SA0 SA1 SA2 47 k RRAS RAS: SDRAMs U[0:8] RCAS CAS: SDRAMs U[0:8] RCKE0 CKE: SDRAMs U[0:8] VDD RWE WE: SDRAMs U[0:8] PCK1: U0, U1, U5 10 k PCK2: U2, U6, U7 PLL PCK3: U3, U4, U8 CK0 PCK4 PCK4: Register
LEGEND:
CS = Chip Select SPD = Serial Presence Detect PLL = Phase-Lock Loop
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS VIH VIH-SPD Supply voltage Supply voltage High-level input voltage High-level input voltage for SPD device Low-level input voltage Ambient temperature 2 2 -0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V V C
PRODUCT PREVIEW
VIL TA
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(CK) Ci(AC) Ci(CKE) Co Ci(DQMBx) Ci(Sx) Ci/o(SDA) Ci(SPD) Input capacitance, CK input Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance Input capacitance, DQMBx input Input capacitance, Sx input SDA Input/output capacitance Input capacitance, SA0, SA1, SA2, SCL inputs MIN MAX 38 10 10 15 10 9 12 10 UNIT pF pF pF pF pF pF pF pF
NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) TEST CONDITIONS IOH = - 2 mA IOL = 2 mA 0 V VI VDD + 0.3 V, All other pins = 0 V to VDD 0 V VO VDD + 0.3 V, Output disabled Burst length = 1, tRC tRC MIN, , IOH/IOL = 0 mA (see Notes 4, 5, and 6) CAS latency = 2 CAS latency = 3 '8TU72JPW-8 MIN 2.4 0.4 MAX '8TU72JPW-8A MIN 2.4 0.4 MAX UNIT V V A A
"10 "10
TBD TBD TBD TBD TBD TBD TBD
"10 "10
TBD TBD TBD TBD TBD TBD TBD
Operating current
mA
ICC2P ICC2N ICC3P ICC3N
Precharge standby current in power-down mode Active standby current in non-power-down mode Active standby current in power-down mode Precharge standby current in non-power-down mode
CKE VIL MAX, tCK = 15 ns (see Note 7) CKE VIH MIN, tCK = 15 ns (see Note 7) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) Page burst, IOH/IOL = 0 mA All banks activated activated, nCCD = one cycle (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2
mA mA mA mA
ICC4
Burst current
mA CAS latency = 3 CAS latency = 2 CAS latency = 3 TBD TBD TBD TBD TBD TBD mA mA
ICC5
Auto-refresh Auto refresh current
ICC6 Self-refresh current CKE VIL MAX TBD TBD mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC tRCMIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change state once every cycle. 10. Continuous burst access, nCCD = 1 cycle
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
ac timing requirements
'8TU72JPW-8 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tRAS Cycle time, CK Cycle time, CK Pulse duration, CK high (input clock duty cycle) Pulse duraction, CK low (input clock duty cycle) Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out with 50-pF load Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Transition time Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Power down/self-refresh exit time Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, WRT command to first data in CAS latency = 2 CAS latency = 3 0 1 0 1 1 1 0 2 0 2 2 3 0 0 1 0 2 1 48 68 20 20 16 16 tRP -(CL-1)*tCK tRP + 1 tCK 1 5 64 1 0 1 1 1 0 2 0 2 2 3 0 1 0 100 000 CAS latency = 2 CAS latency = 3 3 1 8 2 1 48 68 20 20 16 16 tRP - (CL-1)* tCK tRP + 1 tCK 1 5 64 CAS latency = 2 CAS latency = 3 10 8 40 40 60 60 6 6 3 1 8 MAX '8TU72JPW-8A MIN 15 8 40 40 60 60 7.5 6 MAX UNIT ns ns % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms cycles cycles cycles cycles cycles cycles cycles cycles cycles cycles
PRODUCT PREVIEW
tRC tRCD tRP tRRD tRSA tAPR tAPW tT tREF nCCD nCDD nCESP nCLE nCWL nDID nDOD nHZP2 nHZP3 nWCD
nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 1 cycles All references are made to the rising transition of CK unless otherwise noted. Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1 -TM8TU72JPW Table 1. Serial Presence-Detect Data for the TM8TU72JPW
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error-correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Registered, PLL VDD tolerance = (10%), Burst read / write, precharge all, auto precharge tCK = 10 ns tAC = 6 ns N/A N/A TM8TU72JPW-8 ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 72 bits DATA 80h 08h 04h 0Ch 09h 01h 48h 00h 01h 80h 60h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 16h LVTTL tCK = 8 ns tAC = 6 ns ECC 15.6 s/ self-refresh x8 x8 1 CK cycle 1, 2, 4, 8 4 banks 2, 3 0 0 Registered, PLL VDD tolerance = (10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 7.5 ns N/A N/A TM8TU72JPW-8A ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 72 bits DATA 80h
04h 0Ch 09h 01h 48h 00h 01h 80h 60h 02h 80h 08h 08h 01h 0Fh 04h 06h 01h 01h 16h
22
SDRAM device attributes: general
0Eh
0Eh
23 24 25 26
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2
A0h 60h 00h 00h
F0h 75h 00h 00h
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PRODUCT PREVIEW
08h
TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM8TU72JPW (Continued)
BYTE NO. 27 28 29 30 31 32 33 34 35 36 - 61 62 63 DESCRIPTION OF FUNCTION Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Clock Frequency SDRAM component and clock interconnection details System-integrator-specific data Open Rev. 1.2 135 97h TBD T M 8 T U 7 2 J P W - 8 SPACE SPACE TBD TBD TBD TBD TBD 100 MHz 199 TBD 64h C7h 54h 4Dh 38h 54h 55h 37h 32h 4Ah 50h 57h 2Dh 38h 20h 20h 12h 87h 9700... 00h Rev. 1.2 236 97h TBD T M 8 T U 7 2 J P W - 8 A SPACE TBD TBD TBD TBD TBD 100 MHz 199 TBD 64h C7h 54h 4Dh 38h 54h 55h 37h 32h 4Ah 50h 57h 2Dh 38h 41h 20h 12h ECh 9700... 00h TM8TU72JPW-8 ITEM tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 14h 10h 14h 30h 10h 20h 10h 20h 10h TM8TU72JPW-8A ITEM tRP = 20 ns tRRD = 16 ns tRCD = 20 ns tRAS = 48 ns 64M Bytes tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 14h 10h 14h 30h 10h 20h 10h 20h 10h
PRODUCT PREVIEW
64 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 90 91 92 93 - 94 95 - 98 99 - 125 126 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
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TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
device symbolization
TM8TU72JPW Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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PRODUCT PREVIEW
TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULE
SMMS713 - JUNE 1998
BVC (R-PDIM-N168)
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
DUAL-IN-LINE MEMORY MODULE
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.550 (39,37) 1.450 (36,83) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double-Sided DIMM Only)
PRODUCT PREVIEW
0.125 (3,18) 0.118 (3,00) DIA 2 Places
4088193/A 05/98 NOTES: A. B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes depanelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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Copyright (c) 1999, Texas Instruments Incorporated

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