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TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
D D D D D D D D
Organization: - TM2CN64EFN . . . 2 097 152 x 64 Bits - TM4CN64EFN . . . 4 194 304 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket TM2CN64EFN -- Uses Eight 16M-Bit (2M x 8-Bit) Synchronous Dynamic RAMs (SDRAMs) in Plastic Thin Small-Outline Packages (TSOPs) TM4CN64EFN -- Uses Sixteen 16M-Bit (2M x 8-Bit) SDRAMs in Plastic TSOPs Byte-Read/Write Capability Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK2 tCK3 (CL = 3) (CL = 2) ACCESS TIME CLOCK TO OUTPUT tAC2 tAC3 (CL = 3) (CL = 2) 7.5 ns 8 ns REFRESH INTERVAL
D D D D D D D D D
High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Two Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Electroless Gold-Finished Contacts Pipeline Architecture Serial Presence Detect (SPD) Using EEPROM
'xCN64EFN-10
10 ns
15 ns
64 ms
CL = CAS latency
description
The TM2CN64EFN is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight TMS626812ADGE 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812A data sheet (literature number SMOS691). The TM4CN64EFN is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812ADGE 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors.
operation
The TM2CN64EFN operates as eight TMS626812ADGE devices that are connected as shown in the TM2CN64EFN functional block diagram. The TM4CN64EFN operates as sixteen TMS626812ADGE devices connected as shown in the TM4CN64EFN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM2CN64EFN ( SIDE VIEW )
TM4CN64EFN ( SIDE VIEW ) A[0:10] A[0:8] A11/BA0 CAS CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S[0:3] SA[0:2] SCL SDA VDD VSS WE WP
PIN NOMENCLATURE Row-Address Inputs Column-Address Inputs Bank-Select Zero Column-Address Strobe Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip Select Serial Presence Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable Write Protect
1
10 11
PRODUCT PREVIEW
40
41
84
2
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Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC NC VSS NC NC VDD WE DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 NC VDD VDD CK0 NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PIN NAME VSS NC S2 DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC NC VSS NC NC VDD CAS DQMB4 DQMB5 S1 RAS VSS A1 A3 A5 A7 A9 A11/BA0 NC VDD CK1 NC NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS CKE0 S3 DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
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DQ49
TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D D D
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and electroless gold-finished contacts over copper
functional block diagram for the TM2CN64EFN
S0 RC CS CS CK: U0, U4 CK0 U4 DQMB4 R DQ[0:7] DQ[32:39] 8 DQM DQ[0:7] CK2 CK1 RC CK: U1, U5 U0 DQMB0 R DQ[0:7] 8 DQM RC CK: U2, U6 RC CK: U3, U7 RC C RC CK3 U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] DQMB5 R DQ[40:47] 8 DQM DQ[0:7] R = 10 RC = 10 C = 10 pF U5 C
PRODUCT PREVIEW
CS
CS
S2 CS CS
VDD
U[0:7]
U2 DQMB2 R DQ[16:23] 8 DQM DQ[0:7] DQMB6 R DQ[48:55] 8 DQM DQ[0:7]
U6
VSS
U[0:7]
Bypass capacitance: One 0.1 F and one 0.01 F
SPD EEPROM CS CS SCL WP U3 DQMB3 R DQ[24:31] RAS CAS WE CKE0 A[0:11] 8 DQM DQ[0:7] DQMB7 R DQ[56:63] 8 DQM DQ[0:7] U7 SA0 47 k Chip select Serial Presence Detect SA1 SA2 A0 A1 A2 SDA
RAS: SDRAM U[0:7] CAS: SDRAM U[0:7] WE: SDRAM U[0:7] CKE: SDRAM U[0:7] A[0:11]: SDRAM U[0:7]
LEGEND: CS = SPD =
4
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SMMS714 - MAY 1998
functional block diagram for the TM4CN64EFN
S1 S0 CS CS CS CS VSS U0 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] UB0 DQM DQ[0:7] DQMB4 R DQ[32:39] 8 U4 DQM DQ[0:7] UB4 DQM DQ[0:7] VDD CS CS CS CS 10 k U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] UB1 DQM DQ[0:7] DQMB5 R DQ[40:47] 8 U5 DQM DQ[0:7] UB5 DQM DQ[0:7] CKE1 CKE0 RAS CAS WE A[0:11] CKE: UB[0:7] CKE: U[0:7] RAS: U[0:7], UB[0:7] CAS: U[0:7], UB[0:7] WE: U[0:7], UB[0:7] A[0:11]: U[0:7], UB[0:7] RC CK: U0, U4 CK0 CS CS CS CS CK1 U2 DQMB2 R DQ[16:23] 8 DQM DQ[0:7] UB2 DQM DQ[0:7] DQMB6 R DQ[48:55] 8 U6 DQM DQ[0:7] UB6 DQM CK2 DQ[0:7] RC CK: U1, U5 RC CK: UB0, UB4 RC CK: UB1, UB5 RC CK: U2, U6 RC CK: U3, U7 RC CK: UB2, UB6 CS CS CS CS CK3 RC CK: UB3, UB7 SPD EEPROM SCL WP 47 k SA0 SA1 SA2 A0 A1 A2 SDA U[0:7], UB[0:7] VDD U[0:7], UB[0:7]
Bypass capacitance: One 0.1 F and one 0.01 F R = 10 RC = 10
S3 S2
U3 DQMB3 R DQ[24:31] 8 DQM DQ[0:7]
UB3 DQM DQ[0:7] DQMB7 R DQ[56:63] 8
U7 DQM DQ[0:7]
UB7 DQM DQ[0:7]
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TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2CN64EFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM4CN64EFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS VIH VIH-SPD Supply voltage Supply voltage High-level input voltage High-level input voltage for the SPD device Low-level input voltage 2 2 -0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V V C
PRODUCT PREVIEW
VIL TA Ambient temperature VIL MIN = -1.5 V ac (pulse width
v 5 ns)
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(CK) Ci(AC) Ci(CKE) Co Ci(DQMBx) Ci(Sx) Ci/o(SDA) Input capacitance, CK input Input capacitance, address and control inputs: A0 - A11, RAS, CAS, WE Input capacitance, CKE input Output capacitance Input capacitance, DQMBx input Input capacitance, Sx input Input/output capacitance, SDA input TMxCN64EFN MIN MAX 4 5 5 6.5 5 5 9 7 UNIT pF pF pF pF pF pF pF pF
Ci(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
6
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SMMS714 - MAY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) IOH = - 2 mA IOL = 2 mA 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD + 0.3 V, Output disabled Burst length = 1, CAS latency = 2 tRC tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) CKE VIL MAX, tCK = 15 ns (see Note 5) CKE and CK VIL MAX, tCK = (see Note 6) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6) CKE VIL MAX, tCK = 15 ns (see Note 5) CKE and CK VIL MAX, tCK = (see Note 6) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6) Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Note 7) tRC tRC MIN CAS latency = 2 CAS latency = 3 TEST CONDITIONS 'xCN64EFN-10 MIN 2.4 0.4 MAX UNIT V V A A mA mA mA mA mA
"10 "10
95 105 2 2 25 2 3 3 30 10 100 130 85 95
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
Operating current
Precharge standby current in power-down g y mode Precharge standby current in non-power-down non power down mode
Active standby current in power down mode power-down Active standby current in non-power-down non power down mode
mA mA mA mA mA mA mA mA
ICC4
Burst current
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 2 mA Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state twice during tRC. 5. Control, DQ, and address inputs change state once every 30 ns. 6. Control, DQ, and address inputs do not change. 7. Control, DQ, and address inputs change state once every cycle.
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mA
TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
ac timing requirements
'xCN64EFN-10 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP Cycle time, CLK, CAS latency = 2 Cycle time, CLK, CAS latency = 3 Pulse duration, CLK high Pulse duration, CLK low Access time, CLK high to data out, CAS latency = 2 (see Note 8) Access time, CLK high to data out, CAS latency = 3 (see Note 8) Hold time, CLK high to data out Delay time, CLK high to DQ in low-impedance state (see Note 9) Delay time, CLK high to DQ in high-impedance state (see Note 10) Setup time, address, control, and data input Hold time, address, control, and data input Power-down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Transition time (see Note 12) Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 Delay time, WRT command to first data in 0 1 0 1 1 0 2 0 2 2 3 0 0 1 3 1 10 50 80 30 30 20 20 tRP - (CL -1) * tCK tRP + tCK 1 5 64 100 000 3 2 8 15 10 3 3 8 7.5 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms cycle cycle cycle cycle cycle cycle cycle cycle cycle
PRODUCT PREVIEW
tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tT tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 nWCD
nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle All references are made to the rising transition of CK unless otherwise noted. NOTES: 8. tAC is referenced from the rising transition of CK that precedes to the data-out cycle. For example, the first-data out tAC is referenced from the rising transition of CK that is CAS latency - one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CK that is CAS latency - one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL.
8
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SMMS714 - MAY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1 and Table 2). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. SPD contents for the TMxCN64EFN devices are listed in the following tables: Table 1 -TM2CN64EFN Table 2 -TM4CN64EFN
Table 1. Serial Presence Detect Data for the TM2CN64EFN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 8 ns TM2CN64EFN-10 ITEM 128 bytes 256 bytes SDRAM 11 9 1 bank 64 bits DATA 80h 08h 04h 0Bh 09h 01h 40h 00h 01h A0h 75h 00h 80h 08h 00h 01h 0Fh 02h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23 24
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1
F0h 80h
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TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data for the TM2CN64EFN (Continued)
BYTE NO. 25 26 27 28 29 30 31 32 33 34 35 36- 61 DESCRIPTION OF FUNCTION Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row-precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Clock frequency SDRAM component and clock interconnection details System-integrator-specific data Open Rev. 1.2 47 97h TBD T M 2 C N 6 4 E F N - 1 0 SPACE TBD TBD TBD TBD TBD 66 MHz 199 TBD 66h C7h 54h 4Dh 32h 43h 4Eh 36h 34h 45h 46h 4Eh 2Dh 31h 30h 20h 12h 2Fh 9700...00h TM2CN64EFN-10 ITEM N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 16M Bytes tIS = 3 ns tIH = 1 ns tIS = 3 ns tIH = 1 ns DATA 00h 00h 1Eh 14h 1Eh 32h 04h 30h 10h 30h 10h
PRODUCT PREVIEW
62 63 64 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86-90 91 92 93-94 95-98 99-125 126 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
10
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serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM4CN64EFN
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X DIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = (+10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 8 ns N/A N/A TM4CN64EFN-10 ITEM 128 bytes 256 bytes SDRAM 11 9 2 banks 64 bits DATA 80h 08h 04h 0Bh 09h 02h 40h 00h 01h A0h 75h 00h 80h 08h 00h 01h 0Fh 02h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23 24 25 26
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2
F0h 80h 00h 00h
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TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM4CN64EFN (Continued)
BYTE NO. 27 28 29 30 31 32 33 34 35 36-61 62 63 Minimum row-precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Clock frequency SDRAM component and clock interconnection details System-integrator-specific data Rev. 1.2 48 97h TBD T M 4 C N 6 4 E F N - 1 0 SPACE TBD TBD TBD TBD TBD 66 MHz 247 TBD 66h F7h 54h 4Dh 34h 43h 4Eh 36h 34h 45h 46h 4Eh 2Dh 31h 30h 20h 12h 30h 9700...00h DESCRIPTION OF FUNCTION TM4CN64EFN-10 ITEM tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 16M Bytes tIS = 3 ns tIH = 1 ns tIS = 3 ns tIH = 1 ns DATA 1Eh 14h 1Eh 32h 04h 30h 10h 30h 10h
PRODUCT PREVIEW
64 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86-90 91 92 93-94 95-98 99-125 126 127 128-166
167-255 Open TBD indicates values are determined at manufacturing time and are module-dependent. These TBD values are determined and programmed by the customer (optional).
12
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device symbolization (TM2CN64EFN)
TM2CN64EFN Unbuffered Key Position YY MM T -SS = = = =
-SS
YYMMT
3.3-V Voltage Key Position Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
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PRODUCT PREVIEW
TM2CN64EFN 2097152 BY 64-BIT TM4CN64EFN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES
SMMS714 - MAY 1998
MECHANICAL DATA
BS (R-PDIM-N168)
5.255 (133,48) 5.245 (133,22) Notch 0.157 (4,00) x 0.122 (3,10) Deep 2 Places
DUAL IN-LINE MEMORY MODULE
(Note D) Notch 0.079 (2,00) x 0.122 (3,10) Deep 2 Places 0.054 (1,37) 0.046 (1,17)
0.039 (1,00) TYP
0.050 (1,27) 0.125 (3,18)
0.014 (0,35) MAX 0.118 (3,00) TYP 0.700 (17,78) TYP 1.130 (28,70) 1.120 (28,45) 0.106 (2,70) MAX 0.157 (4,00) MAX (For Double Sided DIMM Only) 4088181/A 06/97
PRODUCT PREVIEW
0.125 (3,18) 0.118 (3,00) DIA 2 Places
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MO-161 Dimension includes De-panelization variations; applies between notch and tab edge. Outline may vary above notches to allow router/panelization irregularities.
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POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
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