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Serial Presence Detect
Technical Reference
1998
Technical Documentation Services
Printed in U.S.A., January 1998
SMMU001
Book Type Two Lines
Volume #
Title Two Lines Subtitle
Line Two
year
Book Type
Volume #
Book Type Two Lines
Title Two Lines Title Subtitle
Line Two
Title Two Lines Subtitle
Title Subtitle
Book Type
Title
year
Serial Presence Detect Technical Reference
SMMU001 January 1998
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1998, Texas Instruments Incorporated
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 SPD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 SPD Specifications and Device SPD Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Appendix A Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 SPD Format for FPM/EDO DRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 SPD Bytes Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.2.1 Byte 0: Number of Bytes Written Into Serial Memory by Module Manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.2.2 Byte 1: Total Number of Bytes of the SPD Memory Device . . . . . . . . . . . . A-4 A.2.3 Byte 2: Fundamental Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.2.4 Byte 3: Number of Row Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.2.5 Byte 4: Number of Column Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.2.6 Byte 5: Number of Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.2.7 Bytes 6 and 7: Module Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 A.2.8 Byte 8: Module Interface Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 A.2.9 Byte 9: RAS Access Time (tRAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 A.2.10 Byte 10: CAS Access Time (tCAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14 A.2.11 Byte 11: DIMM Configuration Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15 A.2.12 Byte 12: Refresh Rate/Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16 A.2.13 Byte 13: DRAM Width (Base DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18 A.2.14 Byte 14: Error-Checking DRAM Data Width . . . . . . . . . . . . . . . . . . . . . . . . A-19 A.2.15 Bytes 15-31: Reserved for Future Offerings . . . . . . . . . . . . . . . . . . . . . . . . A-20 A.2.16 Bytes 32-61: Superset Features (Possibly Used in the Future) . . . . . . . . A-20 A.2.17 Byte 62: Serial Presence Detect Revision . . . . . . . . . . . . . . . . . . . . . . . . . . A-20 A.2.18 Byte 63: Checksum for Bytes 0-62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20 A.2.19 Bytes 64-125: Manufacturer's Serial-Presence-Detect Format . . . . . . . . A-21 A.2.20 Bytes 126-127: Reserved for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . A-21 A.2.21 Bytes 128-255: System Integrator's SPD Format . . . . . . . . . . . . . . . . . . . A-21 Appendix B Serial-Presence-Detect Format for Synchronous DRAM Modules . . . . . . . . . . B-1 B.1 SPD Format for SDRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.2 SPD Bytes Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2.1 Byte 0: Number of Bytes Written Into Serial Memory by Module Manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2.2 Byte 1: Total Number of Bytes of SPD Serial Memory . . . . . . . . . . . . . . . . . B-4 B.2.3 Byte 2: Fundamental Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.2.4 Byte 3: Number of Row Addresses on This Assembly . . . . . . . . . . . . . . . . . B-5 B.2.5 Byte 4: Number of Column Addresses on This Assembly . . . . . . . . . . . . . . B-8 B.2.6 Byte 5: Number of Module Rows on This Assembly . . . . . . . . . . . . . . . . . B-10 B.2.7 Bytes 6 and 7: Module Data Width of This Assembly . . . . . . . . . . . . . . . . B-10 B.2.8 Byte 8: Module Interface Standard of This Assembly . . . . . . . . . . . . . . . . B-12 B.2.9 Byte 9: SDRAM Cycle Time at Maximum Supported CAS Latency (CL), CL=X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
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B.2.10 B.2.11 B.2.12 B.2.13 B.2.14 B.2.15 B.2.16 B.2.17 B.2.18 B.2.19 B.2.20 B.2.21 B.2.22 B.2.23 B.2.24 B.2.25 B.2.26 B.2.27 B.2.28 B.2.29 B.2.30 B.2.31 B.2.32 B.2.33 B.2.34 B.2.35 B.2.36 B.2.37 B.2.38 B.2.39 B.2.40 B.2.41 B.2.42
Byte 10: SDRAM Access From Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 11: DIMM Configuration Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 12: Refresh Rate/Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 13: SDRAM Width, Primary SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 14: Error-Checking SDRAM Data Width . . . . . . . . . . . . . . . . . . . . . . . Byte 15: Minimum Clock Delay, Back-to-Back Random Column Addresses (nCCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 16: Burst Lengths Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 17: Number of Banks on Each SDRAM Device . . . . . . . . . . . . . . . . . Byte 18: CAS Latencies Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 19: CS Latencies Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 20: Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 21: SDRAM Module Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 22: General SDRAM Device Attributes . . . . . . . . . . . . . . . . . . . . . . . . Byte 23: Minimum Clock Cycle Time at CL of X-1 . . . . . . . . . . . . . . . . . . . Byte 24: Maximum Data Access Time from CLK at CAS Latency of X-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 25: Minimum Clock Cycle Time at CAS Latency of X-2 . . . . . . . . . . Byte 26: Maximum Data Access Time From CLK at CAS Latency of X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 27: Minimum Row Precharge Time (tRP) . . . . . . . . . . . . . . . . . . . . . . Byte 28: Minimum Row-Active-to-Row-Active Delay (tRRD) . . . . . . . . . . . Byte 29: Minimum RAS-to-CAS Delay (tRCD) . . . . . . . . . . . . . . . . . . . . . . . Byte 30: Minimum RAS Pulse Width (tRAS) . . . . . . . . . . . . . . . . . . . . . . . . . Byte 31: Module Bank Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 32: Command and Address Signal Input Setup Time . . . . . . . . . . . . Byte 33: Command and Address Signal Input Hold Time . . . . . . . . . . . . . Byte 34: Data Signal Input Setup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 35: Data Signal Input Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bytes 36 - 61: Superset Features (May be Used in the Future) . . . . . . . Byte 62: Serial-Presence-Detect Revision . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 63: Checksum for Bytes 0 - 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bytes 64-125: Manufacturer's Serial-Presence-Detect Format . . . . . . . . Byte 126: Intel Specification Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte 127: Intel Specification Details for 100 MHz Support . . . . . . . . . . . . Bytes 128-255: System Integrator's SPD Format . . . . . . . . . . . . . . . . . . .
B-14 B-16 B-17 B-18 B-20 B-22 B-22 B-22 B-23 B-23 B-24 B-24 B-24 B-25 B-27 B-29 B-31 B-33 B-34 B-35 B-36 B-36 B-37 B-38 B-39 B-39 B-39 B-40 B-40 B-41 B-41 B-42 B-43 C-1 C-1 C-1 C-1 C-2 C-2 C-3 C-3 C-3
Appendix C Manufacturer's and System Integrator's Serial-Presence-Detect Format . . . C.1 Bytes 64-71 : Manufacturer's JEDEC ID Code (see W.E.G.7.2 per JEP-106-E) . . . . C.2 Byte 72: Manufacturing Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.3 Bytes 73-90: Manufacturer's Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.4 Bytes 91-92: Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.5 Bytes 93-94: Manufacturing Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.6 Bytes 95-98: Assembly Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.7 Bytes 99-125: Manufacturer's Specific Data (for Future Use) . . . . . . . . . . . . . . . . . . . C.8 Bytes 128-255: System Integrator's Specific Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Appendix D EEPROM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.1 EEPROM Component Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.2 EEPROM Component Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.3 Example of SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-1 D-1 D-3 D-7
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Figures
List of Figures
D-1 D-2 D-3 D-4 D-5 D-6 D-7 D-8 D-9 EEPROM Component A.C. Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Byte Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Page Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Current Address Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Random Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Sequential Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 D-3 D-4 D-4 D-5 D-5 D-5 D-6 D-6
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Tables
List of Tables
1 2 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 B-12 B-13 B-14 Serial-Presence-Detect Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Serial-Presence-Detect (SPD) Definitions/Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPD Format for FPM/EDO DRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Byte 0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Byte 1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Byte 2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Byte 3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Byte 3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Byte 4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Byte 4 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 Byte 5 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Bytes 6 and 7 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Byte 6 (LSB Byte) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Byte 7 (MSB Byte) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Byte 8 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 Byte 9 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 Byte 10 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14 Byte 11 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15 Byte 12 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16 Byte 13 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18 Byte 13 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18 Byte 14 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19 Byte 14 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19 Byte 62 SPD Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20 SPD Format for SDRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Byte 0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Byte 1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Byte 2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Byte 3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Byte 3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Byte 4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 Byte 4 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 Byte 5 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 Bytes 6 and 7 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10 Byte 6 (LSB Byte) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 Byte 7 (MSB Byte) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 Byte 8 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 Byte 9 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
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B-15 B-16 B-17 B-18 B-19 B-20 B-21 B-22 B-23 B-24 B-25 B-26 B-27 B-28 B-29 B-30 B-31 B-32 B-33 B-34 B-35 B-36 B-37 B-38 B-39 B-40 B-41 B-42 B-43 B-44 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 D-1
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Byte 10 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 Byte 11 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16 Byte 12 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17 Byte 13 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18 Byte 13 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19 Byte 14 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20 Byte 14 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21 Byte 15 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22 Byte 16 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22 Byte 17 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-23 Byte 18 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-23 Byte 19 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24 Byte 20 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24 Byte 21 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24 Byte 22 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-25 Byte 23 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26 Byte 24 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28 Byte 25 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30 Byte 26 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-32 Byte 27 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-33 Byte 28 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-34 Byte 29 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-35 Byte 30 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-36 Byte-31 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37 Byte-31 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37 Byte-32 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37 Byte-33 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38 Byte-62 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-40 Byte-126 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41 Byte-127 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42 Bytes 64-71 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Byte 72 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Bytes 73-81 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Bytes 82-90 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Byte-91 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Byte-92 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Byte-93 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Byte-94 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 EEPROM Component Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
SMMU001
Tables
D-2 D-3 D-4 D-5
EEPROM Component Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Component A.C. and D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Component A.C. Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DIMM Module TM2SR64EPU-12A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-1 D-1 D-2 D-7
Serial Presence Detect Technical Reference
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x
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Serial Presence Detect Technical Reference
ABSTRACT
The serial-presence-detect (SPD) is a memory module detecting device that provides the host computer information about the memory module. The SPD definition is broken into a series of bytes describing the configuration of the memory module. The SPD describes required and/or optional features in one or more bytes. The required data describes the particular aspects of a module and are fixed in size by the SPD standard. The optional features include the manufacturers' ID, serial numbers, and other data.
1 Introduction
Memory devices are rapidly changing to meet the needs of today's technologies. Under the current parallel presence detect method, the flexibility to adapt new memory technologies to existing module form factors is not possible. Hence, the serial presence detect (SPD) method was developed. This scheme not only allows designers to implement current memory technologies, but to also implement new memory technologies without concern about existing module form factors. The objective of this technical reference is to introduce the SPD, which, in its base form, is independent of the memory technology and module form factor. The implementation of any memory technology using SPD can be achieved as long as it has been defined in the SPD standard.
1.1
SPD Definition
The SPD data, which conforms to the current JEDEC standard, is written into a nonvolatile serial device by the DIMM manufacturer. The SPD definition is broken down into a series of bytes that describes the configuration of the memory module. Each required or optional feature of the SPD is described in one or more bytes that can consist of table look-up entries or binary data. The required data that describes particular aspects of a module is fixed in size by the SPD standard. The optional data, which is supplied by system integrators, can consist of manufacture's IDs, serial numbers, or other data. These optional features will be described in a future appendix. Table 1 shows the general features that must be defined for an SPD to be implemented. When a specific memory technology (FPM, EDO, SDRAM,...) or feature is implemented in an SPD scheme, a corresponding appendix will be updated/added to this document.
Serial Presence Detect Technical Reference
1
Introduction
Table 1. Serial-Presence-Detect Format
BYTE NUMBER 0 1 2 3-35 36-61 62-127 128+ FUNCTION Defines # of bytes written into the SPD device Total # of bytes in the SPD device Fundamental memory type Defines features specific to the fundamental memory Defines superset features Manufacturing information User information
1.2
SPD Specifications and Device SPD Definitions
The SPD device is contained in a 2K-bit serial EEPROM located on the module. Table 2 refers to the SPD EEPROM specifications and the relevent appendix. Table 2 also references the SPD devices to the appropriate appendix containing SPD definitions. Table 2. Serial-Presence-Detect (SPD) Definitions/Specifications
SPD DEVICE DEFINITIONS SPD for EDO/FPM Devices Definition SPD for SDRAM Devices Definition Manufacturer and System Integrator's SPD Format EEPROM Component Specifications APPENDIX Appendix A Appendix B Appendix C Appendix D
2
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Appendix A
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
This appendix describes the serial-presence-detect format for fast-page mode and extended data out DRAM modules. All features follow the JEDEC standard on the serial presence detect and will be updated when changes or new features become available. Table A-1 outlines these features; each feature is defined in section A.2.
A.1
SPD Format for FPM/EDO DRAM Modules
Table A-1. SPD Format for FPM/EDO DRAM Modules
BYTE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-31 32-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-125 FUNCTION Defines number of bytes written into serial memory at module mfg.{ Total number of bytes of the SPD memory device} Fundamental memory type (FPM or EDO) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly... ... Data width continuation Voltage interface standard of this assembly RAS access time of the module CAS access time of the module DIMM configuration type (nonparity, parity, ECC) Refresh rate/type DRAM width, base DRAM Error-checking DRAM data width Reserved for future offerings Superset memory specific features (may be used in the future) SPD revision designator Checksum for bytes 0-62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Revision code Manufacturing date Assembly serial number
Manufacturer specific data This is 128 bytes for FPM and EDO DRAM modules. This is typically 256 bytes.
Serial Presence Detect Technical Reference
A-1
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-1. SPD Format for FPM/EDO DRAM Modules (Continued)
BYTE NUMBER 126-127 128-135 136-150 151-152 153-165 166 167-189 190-221 222 223-253 254 255 Vendor specific System integrator's ID System integrator's P/N System integrator's D/C System integrator's S/N Checksum for bytes 128-165 Top-level system serial number Open Checksum for bytes 167-221 Open Checksum for bytes 223-253 Checksum for bytes 0-128 FUNCTION
A-2
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2
SPD Bytes Defined
A.2.1 Byte 0: Number of Bytes Written Into Serial Memory by Module Manufacturer
This 8-bit field, shown in Table A-2, describes the total number of bytes used by the module manufacturer for the SPD data and any (optional) specific supplier information. The byte count includes the fields for all required and optional data. Table A-2. Byte 0 Definition
NUMBER OF SPD BYTES Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
Serial Presence Detect Technical Reference
A-3
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.2 Byte 1: Total Number of Bytes of the SPD Memory Device
This 8-bit field, shown in Table A-3, describes the total size of the serial memory used to hold the serial-presence-detect data. Table A-3. Byte 1 Definition
SERIAL MEMORY RFU 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes 8192 Bytes 16264 Bytes : : : : BIT 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : : 1 1 BIT 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 : : 1 1 BIT 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 : : 1 1 BIT 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 : : 0 1
A-4
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Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.3 Byte 2: Fundamental Memory Type
This byte, shown in Table A-4, defines the fundamental memory type of the module. Table A-4. Byte 2 Definition
FUNDAMENTAL MEMORY TYPE Reserved Standard FPM EDO PNEDO Sync. DRAM TBD TBD : : TBD TBD 255 BIT 7 0 0 0 0 0 0 0 : : 1 1 1 BIT 6 0 0 0 0 0 0 0 : : 1 1 1 BIT 5 0 0 0 0 0 0 0 : : 1 1 1 BIT 4 0 0 0 0 0 0 0 : : 1 1 1 BIT 3 0 0 0 0 0 0 0 : : 1 1 1 BIT 2 0 0 0 0 1 1 1 : : 1 1 1 BIT 1 0 0 1 1 0 0 1 : : 0 1 1 BIT 0 0 1 0 1 0 1 0 : : 1 0 1 SEE APPENDIX N/A A A TBD B TBD TBD : : TBD TBD TBD
A.2.4 Byte 3: Number of Row Addresses
This field describes the row addressing on the module. If there is one physical bank on the module, or, if there are two physical banks of the same size and organization, then bits 0-3 are used to represent the number of row addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of row addresses for physical bank 1 and bits 4-7 represent the number of row addresses for physical bank 2. These do not include the bank address (BA) pin since physical bank selection on DIMM modules is asserted on dedicated BA pins. Note that if the module employs redundant addressing, then it is denoted in byte 21, bit 6. Examples of Byte 3 are shown in Table A-5. Table A-6 shows the byte definition.
Serial Presence Detect Technical Reference
A-5
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-5. Byte 3 Examples
# BANKS 1 # ROW ADDR BANK 1 11, RA0-RA1 0 11, RA0-RA1 0 11, RA0-RA1 0 # ROW ADDR BANK 2 N/A MODULE ORGANIZATION 2M x 64 DISCRETE USED 2M x 8 BYTE 3 CONTENTS 0000 1011
2
11, RA0-RA1 0 11, RA0-RA1 0
2 x 2M x 64
2M x 8
0000 1011
2
2M x 64 & 1M x 64
2M x 8 & 1M x 16
1011 1011
A-6
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-6. Byte 3 Definition
TABLE SUBFIELD A: Number of row addresses on Bank 1 -OR- Number of row addresses on Bank 1 or 2 if both banks are the same depth, bits 0-3 BIT 3 Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 # ROW ADDR Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 TABLE SUBFIELD B: Number of row addresses on Bank 2 (if different from Bank 1), bits 4-7 BIT 7 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 : 1 0 1 0 1 0 1 0 1 See Subfield A See Subfield B 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 2 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 1 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 : 1 0 1 0 1 0 1 0 1
# ROW ADDR
Serial Presence Detect Technical Reference
A-7
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.5 Byte 4: Number of Column Addresses
This field describes the column addressing on the module. If there is one physical bank on the module, or, if there are two physical banks of the same size, then bits 0-3 are used to represent the number of column addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of column addresses for physical bank 1 and bits 4-7 represent the number of column addresses for physical bank 2. Examples of Byte 4 are shown in Table A-7. Table A-8 shows the byte definition. Table A-7. Byte 4 Examples
# BANKS 1 # COL ADDR BANK 1 9, CA0-C A8 9, CA0-C A8 9, CA0-C A8 # COL ADDR BANK 2 N/A MODULE ORGANIZATION 2M x 64 DISCRETE USED 2M x 8 BYTE 3 CONTENTS 0000 1001 0000 1001 1000 1001
2
11, CA0-C A10 8, CA0-C A7
2 x 2M x 64
2M x 8
2
2M x 64 & 1M x 64
2M x 8 & 1M x 16
A-8
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-8. Byte 4 Definition
TABLE SUBFIELD A: Number of column addresses on Bank 1 -OR- Number of row addresses on Bank 1 or 2 if both banks are the same depth, bits 0-3 BIT 3 Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 # COLUMN ADDR Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 TABLE SUBFIELD B: Number of column addresses on Bank 2 (if different from Bank 1), bits 4-7 BIT 7 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 : 1 0 1 0 1 0 1 0 1 See Subfield A See Subfield B 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 2 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 1 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 : 1 0 1 0 1 0 1 0 1
# COLUMN ADDR
Serial Presence Detect Technical Reference
A-9
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.6 Byte 5: Number of Banks
This field, shown in Table A-9, describes the number of banks on the DRAM module. Table A-9. Byte 5 Definition
NUMBER OF BANKS Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
A.2.7 Bytes 6 and 7: Module Data Width
This 16-bit field, divided among bytes 6 and 7, represents the data width of the module. Bit 0 of byte 6 represents the LSB of the 16-bit identifier, and bit 7 of byte 7 represents the MSB. If the width is less then 255 bits, then byte 7 becomes 00h. If the width is 256 bits, then bytes 6 and 7 are used to designate the total module width. Examples are shown in Table A-10. Table A-11 and Table A-12 show the byte definition. Table A-10. Bytes 6 and 7 Examples
MODULE DATA WIDTH 64 72 780 BYTE 7 0000 0000 0000 0000 0000 0011 BYTE 6 0100 0000 0100 1000 0000 1100
A-10
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-11. Byte 6 (LSB Byte) Definition
DATA WIDTH Undefined 1 2 : : 25 26 27 28 29 30 : 64 : 72 : 80 : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 0 : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : 1 : 1 : 1 : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 0 : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : 0 : 0 : 1 : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : 0 : 1 : 0 : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : 0 : 0 : 0 : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : 0 : 0 : 0 : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 0 : 0 : 0 : 0 : 0 1
Table A-12. Byte 7 (MSB Byte) Definition
MODULE DATA WIDTH 0(+) 256(+) 512(+) 1024(+) 2048(+) : : BIT 7 0 0 0 0 0 : : BIT 6 0 0 0 0 0 : : BIT 5 0 0 0 0 0 : : BIT 4 0 0 0 0 0 : : BIT 3 0 0 0 0 0 : : BIT 2 0 0 0 0 1 : : BIT 1 0 0 1 1 0 : : BIT 0 0 1 0 1 0 : :
Serial Presence Detect Technical Reference
A-11
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.8 Byte 8: Module Interface Levels
This field, shown in Table A-13, describes the module's interface. Table A-13. Byte 8 Definition
VOLTAGE INTERFACE 5.0 Volt/TTL LVTTL HSTL 1.5 SSTL 3.3 SSTL 2.5 TBD TBD : : New Table
BIT 7 0 0 0 0 0 0 0 : : 1
BIT 6 0 0 0 0 0 0 0 : : 1
BIT 5 0 0 0 0 0 0 0 : : 1
BIT 4 0 0 0 0 0 0 0 : : 1
BIT 3 0 0 0 0 0 0 0 : : 1
BIT 2 0 0 0 0 1 1 1 : : 1
BIT 1 0 0 1 1 0 0 1 : : 1
BIT 0 0 1 0 1 0 1 0 : : 1
A-12
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.9 Byte 9: RAS Access Time (tRAC )
This field, shown in Table A-14, describes the module's RAS access time. Table A-14. Byte 9 Definition
RAS ACCESS TIME Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
Serial Presence Detect Technical Reference
A-13
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.10 Byte 10: CAS Access Time (tCAC )
This field, shown in Table A-15, describes the module's CAS access time. Table A-15. Byte 10 Definition
CAS ACCESS TIME Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
A-14
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.11 Byte 11: DIMM Configuration Type
This field, shown in Table A-16, describes the module's error detection and/or correction schemes. Table A-16. Byte 11 Definition
ERROR DET/COR None Parity ECC TBD TBD TBD TBD : : TBD BIT 7 0 0 0 0 0 0 0 : : 1 BIT 6 0 0 0 0 0 0 0 : : 1 BIT 5 0 0 0 0 0 0 0 : : 1 BIT 4 0 0 0 0 0 0 0 : : 1 BIT 3 0 0 0 0 0 0 0 : : 1 BIT 2 0 0 0 0 1 1 1 : : 1 BIT 1 0 0 1 1 0 0 1 : : 1 BIT 0 0 1 0 1 0 1 0 : : 1
Serial Presence Detect Technical Reference
A-15
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.12 Byte 12: Refresh Rate/Type
This field, shown in Table A-17, describes the module's refresh rate and type. Table A-17. Byte 12 Definition
REFRESH PERIOD Normal (15.625us) Reduced (.25x)...3.9us Reduced (.5x)...7.8us Extended (2x)...31.3us Extended (4x)...62.5us Extended (8x)...125us TBD TBD TBD TBD : : BIT 7, SELFREFRESH FLAG 0 0 0 0 0 0 0 0 0 0 : :
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0 0 0 0 0 0 0 0 0 : :
0 0 0 0 0 0 0 0 0 0 : :
0 0 0 0 0 0 0 0 0 0 : :
0 0 0 0 0 0 0 0 1 1 : :
0 0 0 0 1 1 1 1 0 0 : :
0 0 1 1 0 0 1 1 0 0 : :
0 1 0 1 0 1 0 1 0 1 : :
A-16
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Table A-17. Byte 12 Definition (Continued)
REFRESH PERIOD BIT 7, SELFREFRESH FLAG 1 1 1 1 1 1 1 : : 1 1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SELF-REFRESH ENTRIES Normal (15.625us) Reduced (.25x)...3.9us Reduced (.5x)...7.8us Extended (2x)...31.3us Extended (4x)...62.5us Extended (8x)...125us TBD TBD TBD TBD TBD 0 0 0 0 0 0 0 : : 1 1 0 0 0 0 0 0 0 : : 1 1 0 0 0 0 0 0 0 : : 1 1 0 0 0 0 0 0 0 : : 1 1 0 0 0 0 1 1 1 : : 1 1 0 0 1 1 0 0 1 : : 1 1 0 1 0 1 0 1 0 : : 0 1
Serial Presence Detect Technical Reference
A-17
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.13 Byte 13: DRAM Width (Base DRAM)
This field describes the width of the base DRAMs used on the module. Examples of base DRAMs widths are x4,x8, x9, x16, x18 and x32. DRAMs that provide extra bits for error checking are also included. Examples are shown in Table A-18. Table A-19 shows byte definition. Table A-18. Byte 13 Examples
MODULE WIDTH x72 x72 x72 BASE DRAM WIDTH x8 x9 x16 ERROR CHECKING DRAM WIDTH x8 - x1 QTY OF BASE DRAMS 9 8 4 BYTE 13 (BINARY) 0000 1000 0000 1001 0001 0000
Table A-19. Byte 13 Definition
DRAM WIDTH, PRIMARY DRAM Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
A-18
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.14 Byte 14: Error-Checking DRAM Data Width
This field describes the width of error-checking DRAMs if they are present on the module. If the base DRAMs defined in byte 13 incorporate error checking, then this byte is left blank (00h). Examples are shown in Table A-20. Table A-21 shows byte definition. Table A-20. Byte 14 Examples
MODULE WIDTH x72 x72 x72 BASE DRAM WIDTH x8 x9 x16 ERROR-CHECKING DRAM WIDTH x8 - x1 QTY OF ERROR-CHECKING DRAMS 1 - 8 BYTE 14 (BINARY) 0000 1000 0000 0000 0000 0001
Table A-21. Byte 14 Definition
DRAM WIDTH, ERROR CHECKING DRAM Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
Serial Presence Detect Technical Reference
A-19
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
A.2.15 Bytes 15-31: Reserved for Future Offerings
These bytes will be programmed with "0s" if not used.
A.2.16 Bytes 32-61: Superset Features (Possibly Used in the Future)
These bytes will be programmed with "0s" if not used.
A.2.17 Byte 62: Serial Presence Detect Revision
As the SPD definition is updated, it becomes necessary to identify the version of SPD that is being discussed. This TI specification follows JEDEC SPD specification revision 1. Table A-22 shows the definition of Byte 62. Table A-22. Byte 62 SPD Revisions
SPD REVISION Initial Release Rev 1 Rev 2 : : BIT 7 0 0 0 : : BIT 6 0 0 0 : : BIT 5 0 0 0 : : BIT 4 0 0 0 : : BIT 3 0 0 0 : : BIT 2 0 0 0 : : BIT 1 0 0 1 : : BIT 0 0 1 0 : :
A.2.18 Byte 63: Checksum for Bytes 0-62
The checksum calculation process is as follows: 1. Convert binary information, in byte locations 0-62, to decimal. 2. Add together (sum) all decimal values for byte locations 0-62. 3. Divide the `sum' by 256. 4. Convert the remainder to binary (will be < 256). 5. Store the result (a single byte) in address 63 as the checksum.
A-20
SMMU001
Serial-Presence-Detect Format for Fast-Page Mode and Extended-Data-Out DRAM Modules
Example A-1.
Checksum Calculation Process
SERIAL PD CONVERT TO DECIMAL ---- > ---- > ---- > ---- > . . ---- > ---- > ---- > + + + 36 254 0 0 . . 0 0 0 ------ 290 (Sum of all decimal l ) values) 290/256 (Divide by 256.) =1 With a remainder of 34
SPD BYTE ADDRESS 0 1 2 3 . . 60 61 62
0010 0100 1111 1110 0000 0000 0000 0000 . . . . 0000 0000 0000 0000 0000 0000
+ + +
34 (Keep remainder.) 0010 0010 (Convert remainder to binary.) 63 0010 0010 <--- -- Store in byte location 63.
A.2.19 Bytes 64-125: Manufacturer's Serial-Presence-Detect Format
See Appendix C.
A.2.20 Bytes 126-127: Reserved for Future Use A.2.21 Bytes 128-255: System Integrator's SPD Format
See Appendix C.
Serial Presence Detect Technical Reference
A-21
A-22
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Appendix B
Serial-Presence-Detect Format for Synchronous DRAM Modules
This appendix describes the serial-presence-detect format for synchronous DRAM modules. All features follow the JEDEC standard on the serial presence detect and will be updated when changes or new features become available. Table B-1 outlines these features; each feature is defined in section B.2.
B.1
SPD Format for SDRAM Modules
Table B-1. SPD Format for SDRAM Modules
BYTE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FUNCTION Defines number of bytes written into serial memory at module mfg.{ Total number of bytes of the SPD memory device} Fundamental memory type (SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly... ... Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum-supported CAS latency (CL), CL=X SDRAM access from clock DIMM configuration type (nonparity, parity, ECC) Refresh rate/type SDRAM width, primary SDRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latencies supported Write latencies supported SDRAM module attributes General SDRAM device attributes Minimum clock cycle time at CL X-1 Maximum data access time from clock at CL X-1
Minimum clock cycle time at CL X-2 This is typically programmed as 128 bytes. This is typically 256 bytes.
Serial Presence Detect Technical Reference
B-1
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-1. SPD Format for SDRAM Modules (Continued)
BYTE NUMBER 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128-135 136-150 151-152 153-165 166 167-189 190-221 222 223-253 254 255 FUNCTION Maximum data access time from clock at CL X-2 Minimum row precharge time Minimum row-active-to-row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Module bank density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision designator Checksum for bytes 0-62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Revision code Manufacturing date Assembly serial number Manufacturer-specific data Intel specification frequency Intel specification details for PC100 support System integrator's ID System integrator's P/N System integrator's D/C System integrator's S/N Checksum for bytes 128-165 Top-level system serial number Open Checksum for bytes 167-221 Open Checksum for bytes 223-253 Checksum for bytes 0-128
B-2
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2
SPD Bytes Defined
B.2.1 Byte 0: Number of Bytes Written Into Serial Memory by Module Manufacturer
This 8-bit field, shown in Table B-2, describes the total number of bytes used by the module manufacturer for the SPD data and any (optional) specific supplier information. The byte count includes the fields for all required and optional data. This byte is typically programmed as 128 bytes. Table B-2. Byte 0 Definition
NUMBER OF SPD BYTES Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
Serial Presence Detect Technical Reference
B-3
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.2 Byte 1: Total Number of Bytes of SPD Serial Memory
This 8-bit field, shown in Table B-3, describes the total size of the serial memory used to hold the serial-presence-detect data. Table B-3. Byte 1 Definition
SERIAL MEMORY RFU 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes 8192 Bytes 16264 Bytes : : : : BIT 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 BIT 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : : 1 1 BIT 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 : : 1 1 BIT 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 : : 1 1 BIT 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 : : 0 1
B-4
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.3 Byte 2: Fundamental Memory Type
This byte, shown in Table B-4, defines the fundamental memory type of the module. Table B-4. Byte 2 Definition
FUNDAMENTAL MEMORY TYPE Reserved Standard FPM DRAM EDO PNEDO Sync. DRAM TBD TBD : : TBD TBD 255 BIT 7 0 0 0 0 0 0 0 : : 1 1 1 BIT 6 0 0 0 0 0 0 0 : : 1 1 1 BIT 5 0 0 0 0 0 0 0 : : 1 1 1 BIT 4 0 0 0 0 0 0 0 : : 1 1 1 BIT 3 0 0 0 0 0 0 0 : : 1 1 1 BIT 2 0 0 0 0 1 1 1 : : 1 1 1 BIT 1 0 0 1 1 0 0 1 : : 0 1 1 BIT 0 0 1 0 1 0 1 0 : : 1 0 1 SEE APPENDIX N/A A A TBD B TBD TBD : : TBD TBD TBD
B.2.4 Byte 3: Number of Row Addresses on This Assembly
This field describes the row addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size and organization, then bits 0-3 are used to represent the number of row addresses for each physical bank. If the module has two physical banks of different sizes, then bits 0-3 represent the number of row addresses for physical bank 1 and bits 4-7 represent the number of row addresses for physical bank 2. These do not include the bank address (BA) pin, since physical bank selection on DIMM modules is asserted on dedicated BA pins. Note that if the module employs redundant addressing, then it is denoted in byte 21, bit 6. Examples of byte 3 are shown in Table B-5. Table B-6 shows the byte definition.
Serial Presence Detect Technical Reference
B-5
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-5. Byte 3 Examples
# BANKS 1 # ROW ADDR BANK 1 11, RA0-RA 10 11, RA0-RA 10 11, RA0-RA 10 # ROW ADDR BANK 2 N/A MODULE ORGANIZATION 2M x 64 DISCRETE USED 2M x 8 BYTE 3 CONTENTS 0000 1011 0000 1011 1011 1011
2
11, RA0-RA 10 11, RA0-RA 10
2 x 2M x 64
2M x 8
2
2M x 64 & 1M x 64
2M x 8 & 1M x 16
B-6
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-6. Byte 3 Definition
TABLE SUBFIELD A: Number of row addresses on Bank 1 -OR- Number of row addresses on Bank 1 or 2 if both banks are the same depth, bits 0-3 BIT 3 Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 # ROW ADDR Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 TABLE SUBFIELD B: Number of row addresses on Bank 2 (if different from Bank 1), bits 4-7 BIT 7 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 : 1 0 1 0 1 0 1 0 1 See Subfield A See Subfield B 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 2 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 1 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 : 1 0 1 0 1 0 1 0 1
# ROW ADDR
Serial Presence Detect Technical Reference
B-7
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.5 Byte 4: Number of Column Addresses on This Assembly
This field describes the column addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size, then bits 0-3 are used to represent the number of column addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of column addresses for physical bank 1 and bits 4-7 represent the number of column addresses for physical bank 2. Examples are shown in Table B-7. Table B-8 shows the byte definition. Table B-7. Byte 4 Examples
# BANKS 1 # COL ADDR BANK 1 9, CA0-CA 8 9, CA0-CA 8 9, CA0-CA 8 # COL ADDR BANK 2 N/A MODULE ORGANIZATION 2M x 64 DISCRETE USED 2M x 8 BYTE 3 CONTENTS 0000 1001 0000 1001 1000 1001
2
11, CA0-CA 10 8, CA0-CA 7
2 x 2M x 64
2M x 8
2
2M x 64 & 1M x 64
2M x 8 & 1M x 16
B-8
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-8. Byte 4 Definition
TABLE SUBFIELD A: Number of column addresses on Bank 1 -OR- Number of column addresses on Bank 1 or 2 if both banks are the same depth, bits 0-3 BIT 3 Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 # COLUMN ADDR Undefined 1/16 2/17 : 7 8 9 10 11 12 13 14 15 TABLE SUBFIELD B: Number of column addresses on Bank 2 (if different from Bank 1), bits 4-7 BIT 7 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 : 1 0 1 0 1 0 1 0 1 See Subfield A See Subfield B 0 0 0 : 0 1 1 1 1 1 1 1 1 BIT 2 0 0 0 : 1 0 0 0 0 1 1 1 1 BIT 1 0 0 1 : 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 : 1 0 1 0 1 0 1 0 1
# COLUMN ADDR
Serial Presence Detect Technical Reference
B-9
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.6 Byte 5: Number of Module Rows on This Assembly
This field, shown in Table B-9, indicates the number of physical rows on the module. Table B-9. Byte 5 Definition
NUMBER OF BANKS Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
B.2.7 Bytes 6 and 7: Module Data Width of This Assembly
This 16-bit field, divided between bytes 6 and 7, represents the data width of the module. Bit 0 of byte 6 represents the LSB of the 16-bit identifier, and bit 7 of byte 7 represents the MSB. If the width is less than 255 bits, then byte 7 becomes 00h. If the width is 256 bits, then bytes 6 and 7 are used to designate the total module width. Examples are shown in Table B-10. Table B-11 and Table B-12 show the byte definition. Table B-10. Bytes 6 and 7 Examples
MODULE DATA WIDTH 64 72 780 BYTE 7 0000 0000 0000 0000 0000 0011 BYTE 6 0100 0000 0100 1000 0000 1100
B-10
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-11. Byte 6 (LSB Byte) Definition
DATA WIDTH Undefined 1 2 : : 25 26 27 28 29 30 : 64 : 72 : 80 : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 0 : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : 1 : 1 : 1 : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 0 : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : 0 : 0 : 1 : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : 0 : 1 : 0 : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : 0 : 0 : 0 : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : 0 : 0 : 0 : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 0 : 0 : 0 : 0 : 0 1
Table B-12. Byte 7 (MSB Byte) Definition
MODULE DATA WIDTH 0(+) 256(+) 512(+) 1024(+) 2048(+) : : BIT 7 0 0 0 0 0 : : BIT 6 0 0 0 0 0 : : BIT 5 0 0 0 0 0 : : BIT 4 0 0 0 0 0 : : BIT 3 0 0 0 0 0 : : BIT 2 0 0 0 0 1 : : BIT 1 0 0 1 1 0 : : BIT 0 0 1 0 1 0 : :
Serial Presence Detect Technical Reference
B-11
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.8 Byte 8: Module Interface Standard of This Assembly
This field, shown in Table B-13, describes the module's voltage interface. Table B-13. Byte 8 Definition
VOLTAGE INTERFACE 5.0 Volt/TTL LVTTL HSTL 1.5 SSTL 3.3 SSTL 2.5 TBD TBD : : New Table BIT 7 0 0 0 0 0 0 0 : : 1 BIT 6 0 0 0 0 0 0 0 : : 1 BIT 5 0 0 0 0 0 0 0 : : 1 BIT 4 0 0 0 0 0 0 0 : : 1 BIT 3 0 0 0 0 0 0 0 : : 1 BIT 2 0 0 0 0 1 1 1 : : 1 BIT 1 0 0 1 1 0 0 1 : : 1 BIT 0 0 1 0 1 0 1 0 : : 1
B.2.9 Byte 9: SDRAM Cycle Time at Maximum Supported CAS Latency (CL), CL =X
This byte, shown in Table B-14, defines the total minimum cycle time for the SDRAM module at the maximum CAS latency specified in byte 18. The byte is broken into two nibbles: the higher order nibble (bits 4-7) designates the cycle time to a granularity of 1ns; the value presented by the lower order nibble (bits 0-3) has a granularity of 1/10ns and is added to the value designated by the higher order nibble. For example, if:
Bits 7:4 are 1010 (10ns) + and bits 3:0 are 0101 (0.5ns) = 10.5ns then the cycle time is
B-12
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-14. Byte 9 Definition
NANOSECONDS Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +0ns +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 RFU : Undefined : 1 : 1 : 1 : 1 See Subfield Table A BIT 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 : 1 0 0 0 0 1 1 1 1 0 0 0 : 1 0 0 1 1 0 0 1 1 0 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 : 1 See Subfield Table B BIT 3 BIT 2 BIT 1 BIT 0
SDRAM CYCLE TIME SUBFIELD A: Units of ns (bits 4 through 7)
SDRAM CYCLE TIME SUBFIELD B: Tenths of ns (bits 0 through 3)
Serial Presence Detect Technical Reference
B-13
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.10 Byte 10: SDRAM Access From Clock
This byte, shown in Table B-15, defines the maximum clock to data out for the SDRAM module. These are the clock-to-data out specifications at the maximum CAS latency specified in byte 18. The byte is broken into two nibbles: the higher order nibble (bits 4-7) designates the cycle time to a granularity of 1ns; the value presented by the lower order nibble (bits 0-3) has a granularity of 1/10ns and is added to the value designated by the higher order nibble. For example, if:
Bits 7:4 are 1010 (10ns) + and bits 3:0 are 0101 (0.5ns) = 10.5ns then the cycle time is
B-14
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-15. Byte 10 Definition
NANOSECONDS Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +0ns +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 RFU : Undefined : 1 : 1 : 1 : 1 See Subfield Table A BIT 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BIT 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BIT 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BIT 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 : 1 0 0 0 0 1 1 1 1 0 0 0 : 1 0 0 1 1 0 0 1 1 0 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 : 1 See Subfield Table B BIT 3 BIT 2 BIT 1 BIT 0 SDRAM CYCLE TIME SUBFIELD A: Units of ns (bits 4 through 7)
SDRAM CYCLE TIME SUBFIELD B: Tenths of ns (bits 0 through 3)
Serial Presence Detect Technical Reference
B-15
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.11 Byte 11: DIMM Configuration Type
This field, shown in Table B-16, describes the module's error-detection and/or correction schemes. Table B-16. Byte 11 Definition
ERROR DET/COR None Parity ECC TBD TBD TBD TBD : : TBD BIT 7 0 0 0 0 0 0 0 : : 1 BIT 6 0 0 0 0 0 0 0 : : 1 BIT 5 0 0 0 0 0 0 0 : : 1 BIT 4 0 0 0 0 0 0 0 : : 1 BIT 3 0 0 0 0 0 0 0 : : 1 BIT 2 0 0 0 0 1 1 1 : : 1 BIT 1 0 0 1 1 0 0 1 : : 1 BIT 0 0 1 0 1 0 1 0 : : 1
B-16
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.12 Byte 12: Refresh Rate/Type
This field, shown in Table B-17, describes the module's refresh rate and type. Table B-17. Byte 12 Definition
REFRESH PERIOD Normal (15.625us) Reduced (.25x)...3.9us Reduced (.5x)...7.8us Extended (2x)...31.3us Extended (4x)...62.5us Extended (8x)...125us TBD TBD TBD TBD : : Normal (15.625us) Reduced (.25x)...3.9us Reduced (.5x)...7.8us Extended (2x)...31.3us Extended (4x)...62.5us Extended (8x)...125us BIT 7, SELFREFRESH FLAG 0 0 0 0 0 0 0 0 0 0 : : 1 1 1 1 1 1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0 0 0 0 0 0 0 0 0 : : 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 : : 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 : : 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 : : 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 : : 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0 : : 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 : : 0 1 0 1 0 1
Serial Presence Detect Technical Reference
B-17
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-17. Byte 12 Definition (Continued)
REFRESH PERIOD TBD TBD TBD TBD TBD BIT 7, SELFREFRESH FLAG 1 : : 1 1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 : : 1 1
0 : : 1 1
0 : : 1 1
0 : : 1 1
1 : : 1 1
1 : : 1 1
0 : : 0 1
B.2.13 Byte 13: SDRAM Width, Primary SDRAM
Bits 0-6 of this byte relate to the primary SDRAM's data width. Bit 7 is a flag that is set to 1 when there is a second physical bank on the module whose size differs from that of the first physical bank. A1 in bit 7 indicates that the second physical bank's data RAMs are twice the width of those on the first physical bank. If there is a second physical bank of the same size and organization as the first, then bit 7 remains 0 and bits 0-6 indicates the error-checking SDRAM width for both banks. The primary SDRAM is the one that is used for data; examples of primary (data) SDRAM widths are x4, x8, x16, and x32. Note that if the module contains SDRAMs that provide for data and error checking (e.g. x9, x18, and x36), then it is also designated in this field. Table B-18 shows examples of SDRAM DIMMs using 1 and 2 banks of symmetrical and asymmetrical size. Table B-19 shows the byte definition. Table B-18. Byte 13 Examples
PHYS. BANK 1 PRIMARY SDRAM WIDTH x9 x8 x16 x8 x8 PHYS. BANK 2 PRIMARY SDRAM WIDTH N/A N/A N/A x8 x16 PHYS. BANK 1 ERRORCHECKING SDRAM WIDTH -- x8 x4 x8 N/A PHYS. BANK 2 ERRORCHECKING SDRAM WIDTH N/A N/A N/A x8 N/A POSSIBLE (16MB-BASED) MODULE DENSITY 16MB 16MB 8MB 32MB 24MB
MODULE WIDTH
BYTE 13 CONTENTS
x72 x72 x72 x72 x64
0000 1001 0000 1000 0001 0000 0000 1000 1000 1000
B-18
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-19. Byte 13 Definition
SUBFIELD A: DATA SDRAM WIDTH DATA SDRAM WIDTH N/A 1 : 4 : 8 9 : 15 16 17 : 32 : 36 : 127 BANK 2 DATA SDRAM WIDTH MULTIPLIER No Bank 2 -OR- Bank 2 uses same width SDRAM as bank 1 Bank 2's SDRAM is 2X the width of Bank 1's SDRAM See Subfield B BIT 7 BIT 6 0 0 : 0 : 0 0 : 0 0 0 : 0 : 0 : 1 BIT 5 0 0 : 0 : 0 0 : 0 0 0 : 1 : 1 : 1 BIT 4 0 0 : 0 : 0 0 : 0 1 1 : 0 : 0 : 1 BIT 3 0 0 : 0 : 1 1 : 1 0 0 : 0 : 0 : 1 BIT 2 0 0 : 1 : 0 0 : 1 0 0 : 0 : 1 : 1 : 0 0 : 1 0 0 : 0 : 0 : 1 BIT 1 0 0 : BIT 0 0 1 : 0 : 0 1 : 1 0 1 : 0 : 0 : 1
SUBFIELD B: BANK 2 DATA SDRAM WIDTH MULTIPLIER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
See Subfield A 1
Serial Presence Detect Technical Reference
B-19
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.14 Byte 14: Error-Checking SDRAM Data Width
If the module incorporates error checking and the primary SDRAM does not include these bits (i.e. there are separate error checking SDRAMs), then the error-checking SDRAM's width is expressed in bits 0-6 of byte 14. Bit 7 is a flag that is set to 1 when there is a second physical bank on the module whose size differs from the first physical bank A1 in bit 7 indicates that the error-checking RAMs in bank 2 are twice as wide as those on the first physical bank. If there is a second physical bank of same size and organization as the first, then bit 7 remains 0 and bits 0-6 indicate the error checking SDRAM width for both physical banks. Table B-20 shows examples of error-checking SDRAM widths with physical banks of symmetric and asymmetric sizing. Table B-21 shows the byte definition. Table B-20. Byte 14 Examples
MODULE WIDTH x72 x72 x72 x72 x72 x72 PHYS. BANK 1 PRIMARY SDRAM WIDTH x9 x8 x16 x8 x8 x8 PHYS. BANK 2 PRIMARY SDRAM WIDTH N/A N/A N/A x8 x16 x16 PHYS. BANK 1 ERRORCHECKING SDRAM WIDTH -- x8 x4 x8 x8 x8 PHYS. BANK 2 ERRORCHECKING SDRAM WIDTH N/A N/A N/A x8 x16 x16 POSSIBLE (16MB-BASED) MODULE DENSITY 8MB 16MB 8MB 32MB 24MB 24MB BYTE 14 CONTENTS 0000 0000 0000 1000 0000 0100 0000 1000 1000 1000 1000 1000
B-20
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-21. Byte 14 Definition
SUBFIELD A: ERROR-CHECKING SDRAM WIDTH DATA SDRAM WIDTH N/A 1 : 4 : 8 9 : 15 16 17 : 32 : 36 : 127 BANK 2 ERRORCHECKING SDRAM WIDTH MULTIPLIER No Bank 2 -OR- Bank 2 uses same width SDRAM as bank 1 Bank 2's SDRAM is 2X the width of Bank 1's SDRAM See Subfield B BIT 7 BIT 6 0 0 : 0 : 0 0 : 0 0 0 : 0 : 0 : 1 BIT 5 0 0 : 0 : 0 0 : 0 0 0 : 1 : 1 : 1 BIT 4 0 0 : 0 : 0 0 : 0 1 1 : 0 : 0 : 1 BIT 3 0 0 : 0 : 1 1 : 1 0 0 : 0 : 0 : 1 BIT 2 0 0 : 1 : 0 0 : 1 0 0 : 0 : 1 : 1 : 0 0 : 1 0 0 : 0 : 0 : 1 BIT 1 0 0 : BIT 0 0 1 : 0 : 0 1 : 1 0 1 : 0 : 0 : 1
SUBFIELD B: BANK 2 ERROR-CHECKING SDRAM WIDTH MULTIPLIER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
See Subfield A 1
Serial Presence Detect Technical Reference
B-21
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.15 Byte 15: Minimum Clock Delay, Back-to-Back Random Column Addresses (nCCD)
Table B-22 shows the definition for byte 15. Table B-22. Byte 15 Definition
NUMBER OF CLOCKS Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
B.2.16 Byte 16: Burst Lengths Supported
This byte, shown in Table B-23, defines which burst lengths are supported. If the burst length is supported, then the corresponding bit is 1. Table B-23. Byte 16 Definition
BIT 7 Burst Length = Page 1 or 0 BIT 6 TBD 0 BIT 5 TBD 0 BIT 4 TBD 0 BIT 3 Burst Length =8 1 or 0 BIT 2 Burst Length =4 1 or 0 BIT 1 Burst Length =2 1 or 0 BIT 0 Burst Length =1 1 or 0
B.2.17 Byte 17: Number of Banks on Each SDRAM Device
This byte, shown in Table B-24, defines the number of banks internal to each discrete SDRAM device on the module.
B-22
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-24. Byte 17 Definition
NUMBER OF BANKS Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 0 : : 1 0 : : 0 1
B.2.18 Byte 18: CAS Latencies Supported
This byte, shown in Table B-25, defines which CAS latencies are supported. If the bit is 1, then that CAS latency is supported; otherwise, it is 0. Table B-25. Byte 18 Definition
BIT 7 TBD 1 or 0
BIT 6 CAS latency = 7 1 or 0
BIT 5 CAS latency = 6 1 or 0
BIT 4 CAS latency = 5 1 or 0
BIT 3 CAS latency = 4 1 or 0
BIT 2 CAS latency = 3 1 or 0
BIT 1 CAS latency = 2 1 or 0
BIT 0 CAS latency = 1 1 or 0
B.2.19 Byte 19: CS Latencies Supported
This byte, shown in Table B-26, defines which CS latencies are acceptable for the module. If the bit is 1, then that CS latency is supported; otherwise, it is 0.
Serial Presence Detect Technical Reference
B-23
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-26. Byte 19 Definition
BIT 7 TBD 1 or 0 BIT 6 CS latency = 6 1 or 0 BIT 5 CS latency = 5 1 or 0 BIT 4 CS latency = 4 1 or 0 BIT 3 CS latency = 3 1 or 0 BIT 2 CS latency = 2 1 or 0 BIT 1 CS latency = 1 1 or 0 BIT 0 CS latency = 0 1 or 0
B.2.20 Byte 20: Write Latency
This byte, shown in Table B-27, defines which write latencies are acceptable for the module. If the bit is 1, then that WE latency is supported; otherwise, it is 0. Table B-27. Byte 20 Definition
BIT 7 TBD 1 or 0 BIT 6 WE latency = 6 1 or 0 BIT 5 WE latency = 5 1 or 0 BIT 4 WE latency = 4 1 or 0 BIT 3 WE latency = 3 1 or 0 BIT 2 WE latency = 2 1 or 0 BIT 1 WE latency = 1 1 or 0 BIT 0 WE Latency = 0 1 or 0
B.2.21 Byte 21: SDRAM Module Attributes
This byte, shown in Table B-28, defines certain features of the module. If the feature is present, then the bit is 1. Conversely, if the feature is not present, then the bit is 0. Table B-28. Byte 21 Definition
BIT 7 TBD BIT 6 Redundant addressing{ BIT 5 Differential clock input BIT 4 Registered DQMB inputs 1 or 0 BIT 3 Buffered DQMB inputs 1 or 0 BIT 2 On-card PLL (clock) BIT 1 Registered address and control inputs} 1 or 0 BIT 0 Buffered address and control inputs} 1 or 0
0
1 or 0
1 or 0
1 or 0
Redundant Addressing implies the use of SDRAMs having the same address depth (e.g. 4Mx4 mixed with 4Mx16) in the same 8 byte quad word, but having different RAS/CAS addressing and/or different numbers of device banks. Actual implementation is not yet determined. Address, RAS, CAS, WE, CKE, CS
B.2.22 Byte 22: General SDRAM Device Attributes
This byte, shown in Table B-29, defines certain features of the SDRAMs on the module. Unless otherwise specified, if the feature is present, then the bit is 1. Conversely, if the feature is not present, then the designated bit is 0.
B-24
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-29. Byte 22 Definition
BIT 7 TBD BIT 6 TBD BIT 5 Upper Vcc tolerance: 0=10% 1=5% 1 or 0 BIT 4 Lower Vcc tolerance: 0=10% 1=5% 1 or 0 BIT 3 Supports Write1/Read Burst 0=false 1=true 1 or 0 BIT 2 Supports Precharge All 0=false 1=true 1 or 0 BIT 1 Supports auto Precharge 0=false 1=true 1 or 0 BIT 0 Supports Early RAS# Precharge 0=false 1=true 1 or 0
0
1 or 0
Tolerance refers to the voltage range under which the SDRAMs operate to the timings specified in SPD bytes 9, 10, 23-30.
B.2.23 Byte 23: Minimum Clock Cycle Time at CL of X-1
The highest CAS latency identified in byte 18 is X; bytes 9 and 10 identify the timing values associated with CAS latency X. Byte 23 identifies the minimum cycle time at CAS X-1. For example, if byte 18 indicates CAS latencies of 1-3, then X is 3 and X-1 is 2. Byte 23 then splits the minimum cycle time at CAS latency = 2. Byte 23 is broken down into two nibbles designating cycle time. The value in the higher order nibble (bits 4-7) has a granularity of 1ns. The value in the lower order nibble (bits 0-3) has a granularity of 1/10ns and is added to the value in the higher order nibble. For example, if:
Bits 7:4 are 1001 (9ns) + and bits 3:0 are 0101 (0.5ns) = 9.5ns then the cycle time is
Table B-30 shows the definition for byte 23.
Serial Presence Detect Technical Reference
B-25
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-30. Byte 23 Definition
NANOSECONDS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SDRAM MINIMUM CYCLE TIME AT CL OF X-1: Subfield A: Units of ns (Bits 4 through 7) Undefined 1/16 2/17 3/18 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 See Subfield Table B
SDRAM MINIMUM CYCLE TIME AT CL OF X-1: Subfield B: Tenths of ns (Bits 0 through 3) +0ns +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 RFU : Undefined : 1 : 1 : 1 : 1 See Subfield Table A 0 0 0 0 0 0 0 0 1 1 1 : 1 0 0 0 0 1 1 1 1 0 0 0 : 1 0 0 1 1 0 0 1 1 0 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 : 1
B-26
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.24 Byte 24: Maximum Data Access Time from CLK at CAS Latency of X-1
The highest CAS latency identified in byte 18 is X. Byte 24 indicates the maximum access time from CLK at CAS latency of X-1. For example, if byte 18 indicates supported CAS latencies of 1-3, then X is 3 and X-1 is 2. Byte 24 then indicates the maximum data access time from CLK at CAS latency of 2. The byte is split into two nibbles designating access time: the value in the higher order nibble (bits 4-7) has a granularity of 1ns; the value in the lower order nibble (bits 0-3) has a granularity of 1/10ns and is added to the value in the higher order nibble. For example, if:
Bits 7:4 are 1001 (9ns) + and bits 3:0 are 0101 (0.5ns) = 9.5ns then the cycle time is
Table B-31 shows the definition for byte 24.
Serial Presence Detect Technical Reference
B-27
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-31. Byte 24 Definition
NANOSECONDS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SDRAM ACCESS TIME FROM CLOCK AT CL OF X-1: Subfield A: Units of ns (bits 4 through 7) Undefined 1/16 2/17 3/18 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 See Subfield Table B
SDRAM ACCESS TIME FROM CLOCK AT CL OF X-1: Subfield B: Tenths of ns (bits 0 through 3) +0ns +0.1 +0.2 +0.3 +0.4 +0.5 +0.6 +0.7 +0.8 +0.9 RFU : Undefined : 1 : 1 : 1 : 1 See Subfield Table A 0 0 0 0 0 0 0 0 1 1 1 : 1 0 0 0 0 1 1 1 1 0 0 0 : 1 0 0 1 1 0 0 1 1 0 0 1 : 1 0 1 0 1 0 1 0 1 0 1 0 : 1
B-28
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.25 Byte 25: Minimum Clock Cycle Time at CAS Latency of X-2
The highest CAS latency identified in byte 18 is X. Byte 25 indicates the minimum cycle time at CAS Latency X-2. For example, if byte 18 indicates CAS latencies of 1-3, then X is 3 and X-2 is 1. Byte 25 then indicates the minimum cycle time at CAS Latency 1. Byte 25 is split into two orders of bits (high and low) designating cycle time: the higher order bits (bits 2-7) designate the cycle time to a granularity of 1ns; the value presented by the lower order bits (0-1) has a granularity of 1/4ns and is added to the value in the higher order bits. For example, if:
Bits 7:2 are 011001 (25ns) Bits 7:2 are 100001 (9ns) + + and bits 1:0 are 00 (0.0ns) and bits 1:0 are 11 (0.75ns) = 9.75ns = 25.0ns then the cycle time is then the cycle time is
Table B-32 shows the definition for byte 25.
Serial Presence Detect Technical Reference
B-29
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-32. Byte 25 Definition
NANOSECONDS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SDRAM MINIMUM CYCLE TIME AT CL OF X-2: Subfield A: Units of ns (bits 2 through 7) Undefined 1 2 3 4 5 6 7 8 9 10 : : 61 62 63 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 1 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 1 0 0 0 0 0 0 0 0 1 1 1 : : 1 1 1 0 0 0 0 1 1 1 1 0 0 0 : : 1 1 1 0 0 1 1 0 0 1 1 0 0 1 : : 0 1 1 0 1 0 1 0 1 0 1 0 1 0 : : 1 0 1 SDRAM MINIMUM CYCLE TIME AT CL = X-2: Subfield B: Quarters of ns (bits 0 through 1) +0ns +0.25 +0.5 +0.75 See Subfield Table A 0 0 1 1 0 1 0 1 See Subfield Table B
B-30
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.26 Byte 26: Maximum Data Access Time From CLK at CAS Latency of X-2
The highest CAS latency identified in byte 18 is X. Byte 26 indicates the maximum access time from the CLK at CAS latencies X-2. For example, if byte 18 indicates CAS latencies of 1-3, then X is 3 and X-2 is 1. Byte 26 then indicates the maximum data access time from CLK at CAS latency of 1. The byte is split into two orders (high and low) of bits designating a data access time: the higher order bits (bits 2-7) have a granularity of 1ns; the value in the lower order bits (bits 0-1) has a granularity of 1/4ns, and is added to the value in the higher order bits. For example, if:
Bits 7:2 are 001001 (9ns) + and bits 1:0 are 01 (0.25ns) = 9.25ns then the maximum access time is
Table B-33 shows the definition of byte 26.
Serial Presence Detect Technical Reference
B-31
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-33. Byte 26 Definition
NANOSECONDS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SDRAM MINIMUM CYCLE TIME AT CL X-2: Subfield A: Units of ns (bits 2 through 7) Undefined 1 2 3 4 5 6 7 8 9 10 : : 61 62 63 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 1 0 0 0 0 0 0 0 0 0 0 0 : : 1 1 1 0 0 0 0 0 0 0 0 1 1 1 : : 1 1 1 0 0 0 0 1 1 1 1 0 0 0 : : 1 1 1 0 0 1 1 0 0 1 1 0 0 1 : : 0 1 1 0 1 0 1 0 1 0 1 0 1 0 : : 1 0 1 SDRAM MINIMUM CYCLE TIME AT CL = X-2: Subfield B: Quarters of ns (Bits 0 through 1) +0ns +0.25 +0.5 +0.75 See Subfield Table A 0 0 1 1 0 1 0 1 See Subfield Table B
B-32
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.27 Byte 27: Minimum Row Precharge Time (tRP )
Byte 27, shown in Table B-34, indicates the module's minimum row precharge time. Table B-34. Byte 27 Definition
MINIMUM ROW PRECHARGE TIME (NANOSECONDS) Undefined 1 2 : : 25 26 27 28 29 30 31 32 33 34 35 36 : : 254 255
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1
0 0 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 1
0 0 0 : : 0 0 0 0 0 0 0 1 1 1 1 1 : : 1 1
0 0 0 : : 1 1 1 1 1 1 1 0 0 0 0 0 : : 1 1
0 0 0 : : 1 1 1 1 1 1 1 0 0 0 0 0 : : 1 1
0 0 0 : : 0 0 0 1 1 1 1 0 0 0 0 1 : : 1 1
0 0 1 : : 0 1 1 0 0 1 1 0 0 1 1 0 : : 1 1
0 1 0 : : 1 0 1 0 1 0 1 0 1 0 1 0 : : 0 1
Serial Presence Detect Technical Reference
B-33
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.28 Byte 28: Minimum Row-Active-to-Row-Active Delay (tRRD )
This field, shown in Table B-35, indicates the minimum required delay between row activations. Table B-35. Byte 28 Definition
MINIMUM ROW-ACTIVETO-ROWACTIVE DELAY (NANOSECONDS) Undefined 1 2 : 20 21 22 23 24 25 26 27 28 29 30 : 127 128 : 254 255
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 0 0 : 0 0 0 0 0 0 0 0 0 0 0 : 0 1 : 1 1
0 0 0 : 0 0 0 0 0 0 0 0 0 0 : 1 0 : 1 1
0 0 0 : 0 0 0 0 0 0 0 0 0 0 0 : 1 0 : 1 1
0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 0 : 1 1
0 0 0 : 0 0 0 0 1 1 1 1 1 1 1 : 1 0 : 1 1
0 0 0 : 1 1 1 1 0 0 0 0 1 1 1 : 1 0 : 1 1
0 0 1 : 0 0 1 1 0 0 1 1 0 0 1 : 1 0 : 1 1
0 1 0 : 0 1 0 1 0 1 0 1 0 1 1 : 1 0 : 0 1
B-34
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.29 Byte 29: Minimum RAS-to-CAS Delay (tRCD )
Byte 29, shown in Table B-36, indicates the minimum delay required between assertions of RAS and CAS. Table B-36. Byte 29 Definition
MINIMUM RAS TO CAS DELAY (NANOSECONDS) Undefined 1 2 : : 25 26 27 28 29 30 : : 127 128 : : 254 255
BIT 7 0 0 0 : : 0 0 0 0 0 0 : : 0 1 : : 1 1
BIT 6 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 5 0 0 0 : : 0 0 0 0 0 0 : : 1 0 : : 1 1
BIT 4 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 3 0 0 0 : : 1 1 1 1 1 1 : : 1 0 : : 1 1
BIT 2 0 0 0 : : 0 0 0 1 1 1 : : 1 0 : : 1 1
BIT 1 0 0 1 : : 0 1 1 0 0 1 : : 1 0 : : 1 1
BIT 0 0 1 0 : : 1 0 1 0 1 1 : : 1 0 : : 0 1
Serial Presence Detect Technical Reference
B-35
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.30 Byte 30: Minimum RAS Pulse Width (tRAS )
Byte 30, shown in Table B-37, defines the minimum RAS pulse width. Table B-37. Byte 30 Definition
MINIMUM RAS PULSE WIDTH (NANOSECONDS) Undefined 1 2 : : 25 26 27 28 29 30 : 50 : 60 : 70 : 127 128 : : 254 255 BIT 7 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 0 : 0 1 : : 1 1 BIT 6 0 0 0 : : 0 0 0 0 0 0 : 0 : 0 : 1 : 1 0 : : 1 1 BIT 5 0 0 0 : : 0 0 0 0 0 0 : 1 : 1 : 0 : 1 0 : : 1 1 BIT 4 0 0 0 : : 1 1 1 1 1 1 : 1 : 1 : 0 : 1 0 : : 1 1 BIT 3 0 0 0 : : 1 1 1 1 1 1 : 0 : 1 : 0 : 1 0 : : 1 1 BIT 2 0 0 0 : : 0 0 0 1 1 1 : 0 : 1 : 1 : 1 0 : : 1 1 BIT 1 0 0 1 : : 0 1 1 0 0 1 : 1 : 0 : 1 : 1 0 : : 1 1 BIT 0 0 1 0 : : 1 0 1 0 1 1 : 0 : 0 : 0 : 1 0 : : 0 1
B.2.31 Byte 31: Module Bank Density
This byte indicates the density of each physical bank on the SDRAM DIMM. This byte will have at least one bit set to 1 to represent the density of at least one bank. If there is more than one physical bank on the module (indicated by byte 5) and all banks have the same density, then only one bit in this field is set. If the module has more than one physical bank of different sizes, then more than one bit will be set; each bit set for each density represented. Examples are shown in Table B-38. Table B-39 shows byte definition.
B-36
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Table B-38. Byte-31 Examples
# BANKS 1 2 2 DENSITY OF PHYSICAL BANK 1 32M byte 32M byte 32M byte DENSITY OF PHYSICAL BANK 2 N/A 32M byte 16M byte BYTE 31 CONTENTS 0000 1000 0000 1000 0000 1100
Table B-39. Byte-31 Definition
BIT 7 DENSITY N/Y 512M byte 0/1
BIT 6 256M byte 0/1
BIT 5 128M byte 0/1
BIT 4 64M byte 0/1
BIT 3 32M byte 0/1
BIT 2 16M byte 0/1
BIT 1 8M byte 0/1
BIT 0 4M byte 0/1
B.2.32 Byte 32: Command and Address Signal Input Setup Time
This byte describes the command and address signal input setup time with respect to the rising edge of the clock input. Both positive and negative setup times are supported. If bit 7 is equal to 0, then the signal input setup time is positive with respect to the clock. If bit 7 is equal to 1, then, the signal input setup time is negative with repect to the clock. Bit 4 through bit 6 define the setup time in nanoseconds (ns) and bit 0 through bit 3 define the signal input setup time in a tenth of a nanosecond. Table B-40. Byte-32 Definition
BIT 7 POSITIVE/ NEGATIVE 0/1
BIT 6
BIT 5 Setup time in ns
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Setup time in tenths of a ns 0/1 0/1 0/1 0/1 0/1
0/1
0/1
For example if:
Bit 7 is 0 + and bits 6:4 are 010 2 ns + and bits 3:0 are 0101 0.05 ns = 2.5 ns then the signal input setup time is
For example if:
Bit 7 is 1 - and bits 6:4 are 000 (0 ns) = and bits 3:0 are 0101 0.05 ns = -0.5ns then the signal input setup time is
Serial Presence Detect Technical Reference
B-37
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.33 Byte 33: Command and Address Signal Input Hold Time
This byte describes the command and address signal input hold time with respect to the rising edge of the clock input. Both positive and negative hold times are supported. If bit 7 is equal to 0, then the signal input hold time is positive with respect to the clock. If bit 7 is equal to 1, then the signal input hold time is negative with respect to the clock. Bits 6 through bit 4 define the hold time in nanoseconds (ns) and bits 3 through 0 define the signal input hold time in a tenth of a nanosecond. Table B-41. Byte-33 Definition
BIT 7 POSITIVE/ NEGATIVE 0/1 0/1 BIT 6 BIT 5 Setup time in ns 0/1 0/1 0/1 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Setup time in tenths of a ns 0/1 0/1 0/1
For example if:
Bit 7 is 0 + and bits 6:4 are 010 2 ns + and bits 3:0 are 0101 0.05 ns = 2.5 ns then the signal input hold time is
For example if:
Bit 7 is 1 - and bits 6:4 are 000 (0 ns) = and bits 3:0 are 0101 0.05 ns = -0.5ns then the signal input hold time is
B-38
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.34 Byte 34: Data Signal Input Setup Time
This byte describes the data signal input setup time with respect to the rising edge of the clock input. Both positive and negative setup times are supported. If bit 7 is equal to 0, then the signal input setup time is positive with respect to the clock. If bit 7 is equal to 1, then the signal input setup time is negative with respect to the clock. Bit 6 through bit 4 define the setup time in nanoseconds (ns) and bits 3 through 0 define the signal input setup time in a tenth of a nanosecond. For example if:
Bit 7 is 0 + and bits 6:4 are 010 2 ns + and bits 3:0 are 0101 0.05 ns = 2.5 ns then the signal input setup time is
For example if:
Bit 7 is 1 - and bits 6:4 are 000 (0 ns) = and bits 3:0 are 0101 0.05 ns = -0.5ns then the signal input setup time is
B.2.35 Byte 35: Data Signal Input Hold Time
This byte describes the input hold time with respect to the rising edge of the clock input. Both positive and negative hold times are supported. If bit 7 is equal to 0, then the signal input hold time is positive with respect to the clock. If bit 7 is equal to 1, then the signal input hold time is negative with respect to the clock. Bit 6 through bit 4 define the hold time in nanoseconds (ns) and bits 3 through 0 define the signal input hold time in a tenth of a nanosecond.
B.2.36 Bytes 36 - 61: Superset Features (May be Used in the Future)
These bytes will be programmed with "zeroes" if not used.
Serial Presence Detect Technical Reference
B-39
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.37 Byte 62: Serial-Presence-Detect Revision
As the SPD definition is updated, it becomes necessary to identify the version of SPD that is being referred to. This TI specification follows JEDEC SPD specification revision 1. Table B-42 shows the definition for byte 62. Table B-42. Byte-62 Definition
SPD REVISION Initial release Rev 1 Rev 2 : :
BIT 7 0 0 0 : :
BIT 6 0 0 0 : :
BIT 5 0 0 0 : :
BIT 4 0 0 0 : :
BIT 3 0 0 0 : :
BIT 2 0 0 0 : :
BIT 1 0 0 1 : :
BIT 0 0 1 0 : :
B.2.38 Byte 63: Checksum for Bytes 0 - 62
The checksum calculation is as follows: 1. Convert binary information in byte locations 0 - 62 to decimal. 2. Add together (sum) all decimal values for byte locations 0 - 62. 3. Divide the sum by 256. 4. Convert the ramainder to binary (it will be < 256). 5. Store the single-byte result in address 63 as the checksum.
B-40
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Example B-1. Checksum for Bytes 0-62
SPD BYTE ADDRESS 0 1 2 3 . . 60 61 62 SERIAL PD 0010 0100 1111 1110 0000 0000 0000 0000 . . . . 0000 0000 0000 0000 0000 0000 ---- > ---- > ---- > ---- > . . ---- > ---- > ---- > + + + CONVERT TO DECIMAL 36 254 0 0 . . 0 0 0 ------ 290 (Sum of all decimal values) 290/256 (Divide by 256.) =1 With a remainder of 34 34 (Keep remainder.) 0010 0010 (Convert remainder to binary.) 63 0010 0010 <--- -- Store in byte location 63.
+ + +
B.2.39 Bytes 64-125: Manufacturer's Serial-Presence-Detect Format
See Appendix C.
B.2.40 Byte 126: Intel Specification Frequency
This byte, shown in Table B-43, defines the clock frequency of the Intel SDRAM DIMM. Table B-43. Byte-126 Definition
INTEL SPECIFICATION FREQUENCY 66 MHz 100 MHz HEX VALUE 66 64
Serial Presence Detect Technical Reference
B-41
Serial-Presence-Detect Format for Synchronous DRAM Modules
B.2.41 Byte 127: Intel Specification Details for 100 MHz Support
This byte defines the SDRAM component and clock interconnection details for the DIMMs as defined: Table B-44. Byte-127 Definition
BIT 7 CLK0 0/1 BIT 6 CLK1 0/1 BIT 5 CLK2 0/1 BIT 4 CLK3 0/1 BIT 3 Junction Temp 0/1 BIT 2 CAS latency = 3 0/1 BIT 1 CAS latency = 2 0/1 BIT 0 Intel "Concurrent AP" 0/1
bit 7 = 1: CLK0 is connected on the DIMM bit7 = 0: CLK0 is not connected on the DIMM bit 6 = 1: CLK1 is connected on the DIMM bit6 = 0: CLK1 is not connected on the DIMM bit 5 = 1: CLK2 is connected on the DIMM bit5 = 0: CLK2 is not connected on the DIMM bit 4 = 1: CLK3 is connected on the DIMM bit4 = 0: CLK3 is not connected on the DIMM bit 3 = 1: 100 C junction temp bit3 = 0: 90 C junction temp bit2 and bit 1 = CL3 and CL2 support as shown:
PERFORMANCE GRADE CAS Latency 3 CAS Latency 3 HEX VALUE (BITS 2 - 1) 04 06
bit 0 = 1: bit0 = 0: Example B-2.
It supports Intel defined concurrent auto-precharge It does not support Intel defined concurrent auto-precharge
Byte 127 with the following encoding will imply:
BIT 7 CLK0 1 BIT 6 CLK1 0 BIT 5 CLK2 1 BIT 4 CLK3 0 BIT 3 Junction Temp 0 BIT 2 CAS latency = 3 1 BIT 1 CAS latency = 2 1 BIT 0 Intel AP 1
This example defines a single-sided DIMM. CLK0 and CLK2 are connceted on the DIMM and there is a 90 C junction temp. The SDRAMs support CL = 2 and the Intel-defined concurrent auto-precharge.
B-42
SMMU001
Serial-Presence-Detect Format for Synchronous DRAM Modules
Example B-3. Byte 127 with the following encoding will imply:
BIT 7 CLK0 1 BIT 6 CLK1 1 BIT 5 CLK2 1 BIT 4 CLK3 1 BIT 3 Junction Temp 1 BIT 2 CAS latency = 3 1 BIT 1 CAS latency = 2 1 BIT 0 Intel AP 1
This example defines a double-sided DIMM. CLK0, CLK1, CLK2, and CLK3 are all connected on the DIMM and there is a 100 C junction temp. The SDRAMs support CL = 2 and the Intel-defined concurrent auto-precharge.
B.2.42 Bytes 128-255: System Integrator's SPD Format
See Appendix C.
Serial Presence Detect Technical Reference
B-43
B-44
SMMU001
Manufacturer's and System Integrator's Serial-Presence-Detect Format
Appendix C Manufacturer's and System Integrator's Serial-Presence-Detect Format
C.1 Bytes 64-71 : Manufacturer's JEDEC ID Code (see W.E.G.7.2 per JEP-106-E)
The manufacturer's JEDEC ID code for Texas Instruments is 97h. The JEDEC ID code is entered first, and the remainer of the assigned bytes are filled with 0s, as shown in Table C-1. Table C-1. Bytes 64-71 Definition
BIT 7 Byte 64 Byte 65 Byte 66 Byte 67 Byte 68 Byte 69 Byte 70 Byte 71 1 0 0 0 0 0 0 0 BIT 6 0 0 0 0 0 0 0 0 BIT 5 0 0 0 0 0 0 0 0 BIT 4 1 0 0 0 0 0 0 0 BIT 3 0 0 0 0 0 0 0 0 BIT 2 1 0 0 0 0 0 0 0 BIT 1 1 0 0 0 0 0 0 0 BIT 0 1 0 0 0 0 0 0 0
C.2
Byte 72: Manufacturing Location
This byte, shown in Table C-2, is defined by the manufacturer. Table C-2. Byte 72 Definition
MFG LOCATION SCI-SGP EEMS TBD
BIT 7 0 0 0
BIT 6 0 0 0
BIT 5 0 0 0
BIT 4 0 0 0
BIT 3 0 0 0
BIT 2 0 0 0
BIT 1 0 1 1
BIT 0 1 0 1
C.3
Bytes 73-90: Manufacturer's Part Number
The manufacturer's device part number must be coded in 8-bit ASCII. Unused spaces will be filled in with 20h (the hex number equivalent of "space"), as shown in Table C-3 and Table C-4. Example: For TM2SR64EPU-12A, bytes 73-90 are programmed as:
544D32535236344550552D3132412020202
Table C-3. Bytes 73-81 Definition
BYTE 73 ASCII HEX T 54 BYTE 74 M 4D BYTE 75 2 32 BYTE 76 S 53 BYTE 77 R 52 BYTE 78 6 36 BYTE 79 4 34 BYTE 80 E 45 BYTE 81 P 50
Serial Presence Detect Technical Reference
C-1
Manufacturer's and System Integrator's Serial-Presence-Detect Format
Table C-4. Bytes 82-90 Definition
BYTE 82 ASCII HEX U 55 BYTE 83 - 2D BYTE 84 1 31 BYTE 85 2 32 BYTE 86 A 41 20 20 20 20 BYTE 87 BYTE 88 BYTE 89 BYTE 90
C.4
Bytes 91-92: Revision Code
Byte 91, as shown in Table C-5, is for die (chip) revision code. Table C-5. Byte-91 Definition
REVISION A B C
BIT 7 0 0 0
BIT 6 0 0 0
BIT 5 0 0 0
BIT 4 0 0 0
BIT 3 0 0 0
BIT 2 0 0 0
BIT 1 0 1 1
BIT 0 1 0 1
Byte 92, as shown in Table C-6, is for board revision code. Table C-6. Byte-92 Definition
REVISION A B C BIT 7 0 0 0 BIT 6 0 0 0 BIT 5 0 0 0 BIT 4 0 0 0 BIT 3 0 0 0 BIT 2 0 0 0 BIT 1 0 1 1 BIT 0 1 0 1
C.5
Bytes 93-94: Manufacturing Date
Bytes 93 and 94 are for the manufacturing date. Byte 93, shown in Table C-7, is for the week. Table C-7. Byte-93 Definition
WEEK N/A 1 2 : : : :
BIT 7 0 0 0 : : : :
BIT 6 0 0 0 : : : :
BIT 5 0 0 0 : : : :
BIT 4 0 0 0 : : : :
BIT 3 0 0 0 : : : :
BIT 2 0 0 0 : : : :
BIT 1 0 0 1 : : : :
BIT 0 0 1 0 : : : :
Byte 94, shown in Table C-8, is for the year.
C-2
SMMU001
Manufacturer's and System Integrator's Serial-Presence-Detect Format
Table C-8. Byte-94 Definition
YEAR N/A 1901 1902 : 1996 1997 1998 : BIT 7 0 0 0 : 0 0 0 : BIT 6 0 0 0 : 1 1 1 : BIT 5 0 0 0 : 1 1 1 : BIT 4 0 0 0 : 0 0 0 : BIT 3 0 0 0 : 0 0 0 : BIT 2 0 0 0 : 0 0 0 : BIT 1 0 0 1 : 0 0 1 : BIT 0 0 1 0 : 0 1 0 :
C.6
Bytes 95-98: Assembly Serial Number
Each module has a unique number regardless of the module type. * Byte 95 is a tester number (SCI = 64, TIS= 1-31, EEMS=32-63). * Bytes 96-98 are a 24-bit serial number that starts at 0. The MSB of this serial number is bit 1 of Byte 96, and the LSB is bit 8 of Byte 98.
C.7
Bytes 99-125: Manufacturer's Specific Data (for Future Use)
These bytes are FF.
C.8
Bytes 128-255: System Integrator's Specific Data
These bytes are FF.
Serial Presence Detect Technical Reference
C-3
C-4
SMMU001
EEPROM Component Specifications
Appendix D
EEPROM Component Specifications
The serial presence detect (SPD) device is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains data such as module configuration, SDRAM organization, and timing parameters. Only the first 128 bytes are programmed by Texas Instruments; the remaining 128 bytes are available for customer use. Programming is performed through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD standard.
D.1
EEPROM Component Definition
Table D-1, Table D-2, Table D-3, and Table D-4 define components of the SPD EEPROM. various
Table D-1. EEPROM Component Absolute Maximum Ratings
PARAMETER All input or output Voltages with respect to ground Ambient Storage Temperature RANGE +4.6V to -0.3V -40 oC to +100 oC
Table D-2. EEPROM Component Operating Conditions
PARAMETER Ambient Operating Temperature Positive Power Supply RANGE 0 oC to +70 oC 3.0V to 3.6V
Table D-3. EEPROM Component A.C. and D.C. Characteristics
SYMBOL ICCA ISB ILI ILO VIL VIH VOL PARAMETER Active power supply current Standby current Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage IOL = 3 ma TEST CONDITIONS fSCL = 100 kHz VIN = GND or VCC VIN = GND or VCC VOUT = GND to VCC -0.3 VCC X 0.7 0.4 MIN MAX 5.0 100 10 10 VCC X 0.3 UNITS mA uA uA uA V V V
Serial Presence Detect Technical Reference
D-1
EEPROM Component Specifications
Table D-4. EEPROM Component A.C. Timing Parameters
SYMBOL fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH PARAMETER SCL clock frequency Noise suppression time constant at SCL, SDA inputs SCL low to SDA data out valid Time the bus must be free before a new transmission can start Start condition hold time Clock low time Clock high time Start condition setup time (for a repeated start condition) Data in hold time Data in setup time SDA and SCL rise time SDA and SCL fall time Stop condition setup time Data out hold time 6.7 300 0.3 6.7 4.5 6.7 4.5 6.7 0 500 1 300 MIN MAX 80 100 7.0 UNITS kHz ns us us us us us us us ns us ns us ns
tWR Write cycle time 15 ms NOTE: Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the write cycle, the EEPROM bus interface circuits are disabled, SDA remains high due to a pull-up resistor, and the EEPROM does not respond to its slave address.
D-2
SMMU001
EEPROM Component Specifications
D.2
EEPROM Component Illustration
The following drawings illustrate the EEPROM components.
tF t LOW
SCL
t HIGH
tR
t SU:STA
SDA IN
t HD:STA t SU:DAT
t SU:STO
t AA
SDA OUT
t DH
t BUF
Figure D-1. EEPROM Component A.C. Timing Parameters
SDA SCL
Data stable
Data change
Figure D-2. EEPROM Data Validity
Serial Presence Detect Technical Reference
D-3
EEPROM Component Specifications
SDA
SCL
START START = High to low transition of SDA while SCL is high STOP = Low to high transition of SDA while SCL is high
STOP
Figure D-3. EEPROM Start and Stop Conditions
SCL SDA
Output from transmitter
1
8
9
SDA
Output from receiver START ACKNOWLEDGE
ACKNOWLEDGE: Transmitter releases SDA after transmitting eight bits. During the ninth clock cycle, the receiver pulls SDA low to acknowledge receipt of the eight bits.
Figure D-4. EEPROM Acknowledge
D-4
SMMU001
EEPROM Component Specifications
SYSTEM MASTER:
SDA
S T A R T
Slave address (Write)
1010AAA0 210 A C K
Word address
Data
S T O P
EEPROM:
A C K
A C K
Figure D-5. EEPROM Byte Write Operation
SYSTEM MASTER:
SDA
S T A R T
Slave address (Write)
1010AAA0 210 A C K
Word address (n)
Data n
Data n+1
Data n+15 O
P
S T
EEPROM:
A C K
A C K
A C K
A C K
Figure D-6. EEPROM Page Write Operation
SYSTEM MASTER:
SDA
S T A R T
Slave address (Read)
1010AAA1 210 A C K
S T O P
EEPROM:
Data
Figure D-7. EEPROM Current Address Read Operation
Serial Presence Detect Technical Reference
D-5
EEPROM Component Specifications
SYSTEM MASTER:
SDA
S T A R T
Slave address (Write)
1 01 0AAA0 210 A C K
Word address n
S T A R T
Slave address (Read)
1010AAA1 210
S T O P
EEPROM:
A C K
A C K
Data n
Figure D-8. EEPROM Random Read Operation
SYSTEM MASTER:
SDA
S T A R T
Slave address (Read)
A C K
A C K
A C K
S T O P
1010AAA1 210 A C K
EEPROM:
Data n
Data n+1
Data n+x
Figure D-9. EEPROM Sequential Read Operation
D-6
SMMU001
EEPROM Component Specifications
D.3
Example of SPD
Table D-5 shows an example of serial presence detect. Table D-5. SDRAM DIMM Module TM2SR64EPU-12A
BYTE NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
FUNCTION Defines number of bytes written into serial memory at module mfg. Total number of bytes of SPD memory device Fundamental memory type SDRAM Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly... ... Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL=X (CL=3) SDRAM access from clock (CL=3) Module configuration type (nonparity, parity, error-correcting code [ECC]) Refresh rate/type SDRAM width, primary SDRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS number latency{ CS number latency Write latency SDRAM module attributes General SDRAM device attributes
VALUE 128 bytes 256 bytes SDRAM 11 9 1 bank 64 bits LVTTL tCK=12ns tAC=9ns Nonparity 15.6us/self-refresh x8 n/a 1 clk cycle 1,2,4,8 2 banks 2,3 0 0 Nonbuffered/ nonregistered Vcc tol. =(+10%)/(-5%), burst read, single-bit write, precharge all, autoprecharge
EEPROM CONTENTS 80h 08h 04h 0Bh 09h 01h 40h 00h 01h C0h 90h 0h 80h 08h 00h 01h 0Fh 02h 06h 01h 01h 00h 1Eh
Read latency = 1 is not supported.
Serial Presence Detect Technical Reference
D-7
EEPROM Component Specifications
Table D-5. SDRAM DIMM Module TM2SR64EPU-12A (Continued)
BYTE NUMBER 23 24 25 26 27 28 29 30 31 32-61 62 63 64-71 72 73-90 EEPROM CONTENTS F0h 90h 00h 00h 1Eh 18h 1Eh 3Ch 04h 00h 01h 07h 9700...00h 01h 544D3253523 6344550552D 31324120202 020 01h 01h 05h 61h MFG Data FFh FFh
FUNCTION Minimum clock cycle time at CL X-1 (CL=2) Maximum data access time from clock at CL X-1 (CL=2) Minimum clock cycle time at CL X-2 (CL=1){ Maximum data access time from clock at CL X-2 (CL=1){ Minimum row precharge time Minimum row-active-to-row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Module bank density Superset features (may be used in the future) SPD revision designator Checksum for bytes 0-62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number
VALUE tCK=15ns tAC=9ns - - tRP=30ns tRRD=24ns tRCD=30ns tRAS=60ns 16MB N/A 1 7 97h SCI-SGP TM2SR64EPU-12A
91 92 93 94 95-98 99-125 126-127 Read latency = 1 is not supported.
Die revision code PCB revision code Manufacturing week of the year Manufacturing year Assembly serial number Manufacturer-specific data Vender specific
Rev A Rev A Example: fifth week of the year 1997 Unique number N/A N/A
D-8
SMMU001

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