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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
D D D D D D D D D D D
Organization . . . 1 048 576 x 16 Bits x 4 Banks 2 097 152 x 8 Bits x 4 Banks 4 194 304 x 4 Bits x 4 Banks 3.3-V Power Supply ( 10% Tolerance) Four Banks for On-Chip Interleaving for x8/x16 (Gapless Access) Depending on Organizations High Bandwidth - Up to 125-MHz Data Rates Burst Length Programmable to 1, 2, 4, 8 Programmable Output Sequence - Serial or Interleave Chip-Select and Clock-Enable for Enhanced-System Interfacing Cycle-by-Cycle DQ Bus Mask Capability Only x16 SDRAM Configuration Supports Upper-/Lower-Byte Masking Control Programmable CAS Latency From Column Address Performance Ranges:
SYNCHRONOUS CLOCK CYLE TIME tCK3 '664xx4-8 '664xx4-8A '664xx4-10 8 ns 8 ns 10 ns tCK2 10 ns 15 ns 15 ns ACCESS TIME CLOCK TO OUTPUT tAC3 6 ns 6 ns 7.5 ns tAC2 6 ns 7.5 ns 7.5 ns REFRESH INTERVAL tREF 64 ms 64 ms 64 ms
D D D D D D D D D D D D
Pipeline Architecture (Single-Cycle Architecture) Single Write/Read Burst Self-Refresh Capability (Every 16 ms) Low-Noise, Low-Voltage Transistor-Transistor Logic (LVTTL) Interface Power-Down Mode Compatible With JEDEC Standards 16K RAS-Only Refresh (Total for All Banks) 4K Auto Refresh (Total for All Banks)/64 ms Automatic Precharge and Controlled Precharge Burst Interruptions Supported: - Read Interruption - Write Interruption - Precharge Interruption Support Clock-Suspend Operation (Hold Command) Intel PC100 Compliant (-8 and -8A parts)
description
The TMS664xx4 series are 67 108 864-bit synchronous dynamic random-access memory (SDRAM) devices which are organized as follow:
D D D
Four banks of 1 048 576 words with 16 bits per word Four banks of 2 097 152 words with 8 bits per word Four banks of 4 194 304 words with 4 bits per word
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface. The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed microprocessors and caches. The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP) (DGE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
TMS664xx4 (LVTTL) DGE PACKAGE (TOP VIEW)
4M x 16 8M x 8 16M x 4 VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML W CAS RAS CS A13, BS0 A12, BS1 A10, AP A0 A1 A2 A3 VCC VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC W CAS RAS CS A13, BS0 A12, BS1 A10, AP A0 A1 A2 A3 VCC VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC W CAS RAS CS A13, BS0 A12, BS1 A10, AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54-Pin Plastic TSOP-II (Pitch = 0.8 mm) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS BANKS 4 BANK-SELECT ADDRESS A13 - A12 x4 x8 x16 A10 ROW ADDR A0 - A13 A0 - A13 A0 - A13 COL ADDR A0 - A9 A0 - A8 A0 - A7
Auto Precharge
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
PIN NOMENCLATURE A[0:13] Address Inputs Four Banks Column A0 -A9 Column Addr (x4) A0 -A8 Column Addr (x8) A0 -A7 Column Addr (x16) A10 Auto Precharge A12 - A13 Bank-Select Row A0 - A11 Row Addrs A12 - A13 Bank-Select W RAS CAS CKE CLK CS DQ[0 : 3] DQ[0 : 7] DQ[0 :15] DQMU/DQML DQM NC VCC VCCQ VSS VSSQ Write Enable Row-Address Strobe Column-Address Strobe Clock-Enable System Clock Chip-Select SDRAM Data Input / Data Output (x4) SDRAM Data Input / Data Output (x8) SDRAM Data Input / Data Output (x16) Data / Output Mask Enables for x16 Data / Output Mask Enables for x8/x4 No External Connect Power Supply (3.3 V Typical) Power Supply for Output Drivers (3.3 V Typical) Ground Ground for Output Drivers
functional block diagram (four banks)
Array Bank 0 CLK CKE CS (DQM) DQMx RAS CAS W A0 - A13 14 AND Array Bank 1 Control Array Bank 2 DQ Buffer 16 8 4 DQ0 - DQ15 (x16) or DQ0 - DQ7 (x8) or DQ0 - DQ3 (x4)
Array Bank 3
Mode Register
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
device numbering conventions (SDRAM family nomenclature)
TMS 6 64 xx 4 -xx Prefix: TMS = Commercial / MOS Product Family: 6 = Synchronous Dynamic Random-Access Memory Density, Refresh, Interface: 64 = 64M 4K Auto-Refresh LVTTL Organization/Special Architecture: 41 = x 4 Pipeline 81 = x 8 Pipeline 16 = x 16 Pipeline Number of Banks: 4 = Four Banks Speed: 8 tCK3 8A tCK3 10 tCK3 = 8 ns = 8 ns = 10 ns
operation
All inputs to the '664xx4 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs (DQ0- DQ3 for x4, DQ0 - DQ7 for x8, and DQ0 - DQ15 for x16) are also referenced to the rising edge of CLK. The '664xx4 has four banks that are accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles refresh all banks alternately. Five basic commands or functions control most operations of the '664xx4:
D D D D D
Bank activate/row-address entry Column-address entry/write operation Column-address entry/read operation Bank deactivate Auto-refresh/self-refresh entry
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or gate) the CLK input. The device contains a mode register that must be programmed for proper operation. Table 1 through Table 3 show the various operations that are available on the '664xx4. These truth tables identify the command and/or operations and their respective mnemonics. Each truth table is followed by a legend that explains the abbreviated symbols. An access operation refers to any READ (READ-P) or WRT (WRT-P) command in progress at cycle n. Access operations include the cycle upon which the READ (READ-P) or WRT (WRT-P) command is entered and all subsequent cycles through the completion of the access burst.
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
operation (continued)
Automatic Mode Register Set MRS SLFR IDLE SLFR Exit Self Refresh
CKEPDE REFR Power Down CKE ACT Auto Refresh Automatic
CKE CLK Suspend CKE CKE(HOLD) Read DEAC / DCAB Row Active
Active Power Down
WRT CKE(HOLD) WRITE READ Read P Write- P Read-P Write- P Write CKE(HOLD Exit) CLK Suspend
CKE(HOLD Exit)
Read
Read-P
Read P CKE(HOLD Exit)
Automatic Precharge Automatic
Write P
CKE(HOLD Exit)
CKE(HOLD) CKE(HOLD) Power On CLK Suspend Automatic
CLK Suspend
Figure 1. State Diagram
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
operation (continued)
Table 1. Basic Command Truth Table
COMMAND Mode register set Bank deactivate (precharge) Deactivate all banks Bank activate/row-address entry STATE OF BANK(S) All Banks = deac X X SB = deac CS L L L L RAS L L L L CAS L H H H W L L L H A13 X BS X BS A12 X BS X BS A11 X X X V A10 X L H V A9 - A0 A9 = V, A8 = 0, A7 = 0, A6 - A0 = V X X V A0 - A7 = V, A8 - A9 = X, for x16 SB = actv L H L L BS BS X L A0 - A8 = V, A9 = X, for x8 A0 - A9 = V, for x4 A0 - A7 = V, A8 - A9 = X, for x16 SB = actv L H L L BS BS X H A0 - A8 = V, A9 = X, for x8 A0 - A9 = V, for x4 A0 - A7 = V, A8 - A9 = X, for x16 SB = actv L H L H BS BS X L A0 - A8 = V, A9 = X, for x8 A0 - A9 = V, for x4 A0 - A7 = V, A8 - A9 = X, for x16 SB = actv L H L H BS BS X H A0 - A8 = V, A9 = X, for x8 A0 - A9 = V, for x4 X X X READ-P READ WRT-P WRT MNEMONIC MRS DEAC DCAB ACTV
Column-address Column address entry / write operation
Column address entry / write Column-address operation with auto-deactivate
Column-address Column address entry/read operation
Column address entry/read Column-address operation with auto-deactivate
No operation Control-input inhibit / no operation Auto refresh
X X All banks= deac
L H L
H X L
H X L
H X H
X X X
X X X
X X X
X X X
NOOP DESL REFR
For execution of these commands on cycle n, CKE must satisfy requirements for one of the following: -- CKE (n - 1) must be high -- tCESP from power-down exit (PDE) -- tIS and nCLE from clock-suspend (HOLD) exit -- tCESP and tRC from self-refresh (SLFR) exit. DQMx (n) is a don't care Auto-refresh or self-refresh entry requires that all banks be deactivated or be in an idle state prior to the command entry. An REFR command turns on four rows (one from each bank; therefore, 4096 REFR commands fully refresh the memory). Legend: n = CLK cycle number actv = Activated L = Logic low deac = Deactivated BS = Logic: (A12 = 0, A13 = 0) select bank 0 (A12 = 1, A13 = 0) select bank 1 H = Logic high (A12 = 0, A13 = 1) select bank 2 (A12 = 1, A13 = 1) select bank 3 X = Don't care (either logic high or logic low) SB = Select bank by A12 - A13 at cycle n V = Valid
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SMOS695A - APRIL 1998 - REVISED JULY 1998
operation (continued)
Table 2. Clock-Enable (CKE) Command Truth Table
COMMAND Self-refresh entry Power-down entry at n + 1 Self refresh exit Self-refresh Power-down exit CLK suspend at n + 1 CLK suspend exit at n + 1 STATE OF BANK(S) All banks = deac All banks = no access operation All banks = self-refresh All banks = power down All banks = access operation All banks = access operation CKE (n - 1) H H L L L H L CKE (n) L L H H H L H CS (n) L X L H X X X RAS (n) L X H X X X X CAS (n) L X H X X X X W (n) H X H X X X X MNEMONIC SLFR PDE -- -- -- HOLD --
For execution of these commands, A0 - A13 (n) and DQMx (n) are don't care entries. On cycle n, the device executes the respective command (listed in Table 1). On cycle (n+1), the device enters the power-down mode. A bank is no longer in an access operation one cycle after the last data-out cycle of a READ (READ-P) operation, and two cycles after the last data-in cycle of a WRT (WRT-P) operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a WRT (WRT-P) operation. If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise, either the DESL or NOOP command must be applied before any other command. Legend: n = CLK cycle number L = Logic low H = Logic high X = Don't care (either logic high or logic low) deac = Deactivated
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
operation (continued)
Table 3. Data / Output Mask Enable (DQM) Command Truth Table
DQM (DQML/DQMU) (n) X X L H L H D0 - D3 (x4) D0 - D7 (x8) D0 - D15 (x16) (n) N/A N/A V M N/A N/A Q0 - Q3 (x4) Q0 - Q7 (x8) Q0 - Q15 (x16) (n+2) Hi-Z Hi-Z N/A N/A V Hi-Z
COMMAND
STATE OF BANK(S)
MNEMONIC
-- -- Data-in enable Data-in mask Data-out enable Data-out mask
Any bank = deac Any bank = actv ( no access operation ) Any bank = write Any bank = write Any bank = read Any bank = read
-- -- ENBL MASK ENBL MASK
For execution of these commands on cycle n, one of the following must be true: -- CKE (n - 1) must be high -- tCESP from power-down exit (PDE) -- nCLE from clock-suspend (HOLD) exit -- tCESP and tRC from self-refresh (SLFR) exit CS (n), RAS (n), CAS (n), W (n), and A0 - A13 (n) are don't care entries. DQM is used for x4/x8 (no byte control). DQM (n) operations correspond to D0 - D7 and Q0 - Q7 events. DQML/DQMU are used for x16 (for byte-control). DQML (n) operations correspond to D0 - D7 and Q0 - Q7 events, while DQMU (n) operations correspond to D8 - D15 and Q8 - Q15 events. A bank is no longer in an access operation one cycle after the last data-out cycle of a READ (READ-P) operation, and two cycles after the last data-in cycle of a WRT (WRT-P) operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a WRT (WRT-P) operation. Legend: n L H X V M N/A Hi-Z = CLK cycle number = Logic low = Logic high = Don't care (either logic high or logic low) = Valid = Masked input data = Not applicable = High impedance actv deac write read = Activated = Deactivated = Activated and accepting data in on cycle n = Activated and delivering data out on cycle n + 2
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SMOS695A - APRIL 1998 - REVISED JULY 1998
burst sequence
All data for the '664xx4 is written or read in a burst fashion, that is, a single starting address is entered into the device and then the '664xx4 internally accesses a sequence of locations based on that starting address. Some of the subsequent accesses after the first one can be at preceding, as well as succeeding, column addresses depending on the starting address entered. This sequence can be programmed to follow either a serial burst or an interleave burst (see Table 4 through Table 6). The length of the burst sequence can be user-programmed to be 1, 2, 4, or 8. After a read burst is completed (as determined by the programmed burst length), the outputs are in the high-impedance state until the next read access is initiated. Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0 DECIMAL START Serial Interleave 0 1 0 1 2ND 1 0 1 0 0 1 0 1 BINARY START 2ND 1 0 1 0
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1 - A0 DECIMAL START 0 Serial 1 2 3 0 Interleave 1 2 3 2ND 1 2 3 0 1 0 3 2 3RD 2 3 0 1 2 3 0 1 4TH 3 0 1 2 3 2 1 0 START 00 01 10 11 00 01 10 11 BINARY 2ND 01 10 11 00 01 00 11 10 3RD 10 11 00 01 10 11 00 01 4TH 11 00 01 10 11 10 01 00
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2 - A0 DECIMAL START 0 1 2 Serial 3 4 5 6 7 0 1 2 Interleave 3 4 5 6 7 2ND 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 3RD 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 4TH 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 5TH 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 6TH 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 7TH 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8TH 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 START 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 2ND 001 010 011 100 101 110 111 000 001 000 011 010 101 100 111 110 3RD 010 011 100 101 110 111 000 001 010 011 000 001 110 111 100 101 BINARY 4TH 011 100 101 110 111 000 001 010 011 010 001 000 111 110 101 100 5TH 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 6TH 101 110 111 000 001 010 011 100 101 100 111 110 001 000 011 010 7TH 110 111 000 001 010 011 100 101 110 111 100 101 010 011 000 001 8TH 111 000 001 010 011 100 101 110 111 110 101 100 011 010 001 000
latency
The beginning data-output cycle of a read burst can be programmed to occur two or three CLK cycles after the READ command (see Figure 2 on how to set the mode register.) This feature allows adjustment of the '664xx4 to operate in accordance with the system's capability to latch the data output from the '664xx4. The delay between the READ command and the beginning of the output burst is known as CAS latency (also known as read latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening gaps. Use of minimum CAS latencies is restricted, based on the particular maximum frequency rating of the '664xx4. Once the mode register has been set (see the section on setting the mode register), subsequent changes to the CAS latency are prohibited. There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same rising edge of CLK as the WRT command. The write latency is fixed and is not determined by the mode-register contents.
four-bank operation
The '664xx4 contains four independent banks that can be accessed individually or in an interleaved fashion. Each bank must be activated with a row address before it can be accessed. Each bank then must be deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry command (ACTV) is entered by holding RAS low, CAS high, W high, and A12 - A13 valid on the rising edge of CLK. A bank can be deactivated either automatically during a READ (READ-P) or a WRT (WRT-P) command, or by using the bank-deactivate (DEAC) command. All banks can be deactivated at once by using the DCAB command (see Table 1 for a description of the bank-deactivation, and Figure 25 and Figure 26 for examples of the operation).
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SMOS695A - APRIL 1998 - REVISED JULY 1998
four-bank row-access operation One of the features of the four-bank operation is access to information on random rows at a higher rate of operation than is possible with a standard DRAM. This is accomplished by activating one of the banks with a row address and, while the data stream is being accessed to/from that bank, activating one of the other banks with other row addresses. When the data stream to / from the first activated bank is complete, the data stream to / from the second activated bank can begin without interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next round of accesses or the entry of new row addresses for other banks which currently are deactivated. In this manner, operation can continue in an interleaved fashion. Figure 29A is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 8. Figure 29B is an example of four-bank, row-interleaving, read bursts with automatic deactivate with a CAS latency of 3 and a burst length of 4. four-bank column-access operation The availability of four banks allows the access of data from random starting columns between banks at a higher rate of operation. After activating each bank with a row address (ACTV command), A12 - A13 for the four-bank column-access operation can be used to alternate READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all specified timing requirements are met. Figure 30 is an example of four-bank, column-interleaving, read bursts with a CAS latency of 3 and a burst length of 2.
bank deactivation (precharge)
All banks can be deactivated simultaneously (placed in precharge) by using the DCAB command. A single bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB command except that A10 must be low and A12 - A13 select the bank to be precharged (see Table 1; Figure 27 and Figure 31 provide examples). A bank can also be deactivated automatically by using A10 during a READ or WRT command. If A10 is held high during the entry of a READ or WRT command, the accessed bank, selected by A12 - A13, is automatically deactivated upon completion of the access burst. If A10 is held low during READ- or WRT-command entry, that bank remains active following the burst. The READ and WRT commands with automatic deactivation are denoted as READ-P and WRT-P. See Figure 29A and Figure 29B for examples.
chip-select
CS (chip-select) can be used to select or deselect the '664xx4 for command entries, which might be required for multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). Using CS does not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W inputs to the '664xx4.
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TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A - APRIL 1998 - REVISED JULY 1998
data/output mask
Masking of individual data cycles within a burst sequence can be accomplished by using the MASK command (see Table 3). If DQM (or DQML/ DQMU of x16) is held high on the rising edge of CLK during a write burst, the incident data word (referenced to the same rising edge of CLK) on DQ0 - DQ7 [or (DQ0-DQ7)/( DQ8- DQ15) of x16] is ignored. If DQM (or DQML/DQMU of x16 ) is held high on the rising edge of CLK for a read burst, DQ0- DQ7 [or (DQ0-DQ7)/( DQ8- DQ15) of x16], referenced to the second rising edge of CLK, are in the high-impedance state. The application of DQM (DQML/DQMU) to data-output cycles (READ burst) involves a latency of two CLK cycles, but the application of DQM to data-in cycles (WRITE burst) has no latency. The MASK command (or its opposite, the ENBL command) is performed on a cycle-by-cycle basis, allowing the user to gate any individual data cycle or cycles within either a read-burst or a write-burst sequence. Figure 14, Figure 38 and Figure 39 show examples of data / output masking.
CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current state and no further inputs are accepted until CKE is returned high. This is known as a CLK-suspend operation and its execution is denoted as a HOLD command. The device resumes operation from the point at which it was placed in suspension, beginning with the second rising edge of CLK after CKE is returned high. See Figure 42 and Figure 43 for examples. If CKE is brought low when no READ (READ-P) or WRT (WRT-P) command is in progress, the device enters power-down mode. If all banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum. Power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. After power-down mode has been entered, no further inputs are accepted until CKE returns high. To ensure that data in the device remains valid during the power-down mode, the self-refresh command ( SLRF) must be executed concurrently with the power-down entry ( PDE) command. When exiting power-down mode, new commands can be entered on the first CLK edge after CKE returns high, provided that the setup time (tCESP) is satisfied. Table 2 shows the command configuration for a CLK-suspend/power-down operation; Figure 18 and Figure 19 show examples of the procedure.
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SMOS695A - APRIL 1998 - REVISED JULY 1998
setting the mode register
The '664xx4 contains a mode register that must be user-programmed with the CAS latency, the burst type, and the burst length. This is accomplished by executing an MRS command with the information entered on address lines A0 - A9. A logic 0 must be entered on A7 and A8, but A10 - A13 are "don't care" entries for the '664xx4. When A9 = 1, the write burst length is always 1. When A9 = 0, the write burst length is defined by A2 - A0. Figure 2 shows the valid combinations for a successful MRS command. Only valid addresses allow the mode register to be changed. If the addresses are not valid, the previous contents of the mode register remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word valid on A0 - A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when all banks are deactivated and may not be executed while a burst is active. See Figure 24 and Figure 35 for examples.
A13 A12 A11 A10 A9 A8 0 A7 0 0 = Serial 1 = Interleave (burst type) REGISTER BITS A6 A5 A4 REGISTER BITS BURST LENGTH A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 1 2 4 8 A6 A5 A4 A3 A2 A1 A0
Reserved
REGISTER BIT A9
WRITE BURST LENGTH
CAS LATENCY
0 1
A2 - A0 1
0 0
1 1
0 1
2 3
All other combinations are reserved. Refer to timing requirements for minimum valid read latencies based on maximum frequency rating. Once the mode register has been set, subsequent changes to the CAS latency is prohibited.
Figure 2. Mode-Register Programming
refresh
The '664xx4 must be refreshed at intervals not exceeding tREF (see timing requirements) or data cannot be retained. Refresh is accomplished by performing one of the following:
D D D
An ACTV command (RAS-only refresh) to every row in all banks 4096 auto-refresh (REFR) commands Putting the device in self-refresh mode
Regardless of the method used, refresh must be accomplished before tREF has expired. See Figure 34 for an example.
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auto refresh Before performing an auto refresh, all banks must be deactivated (placed in precharge). To enter a REFR command, RAS and CAS must be low and W must be high during the rising edge of CLK (see Table 1). The refresh address is generated internally such that after 4096 REFR commands, all banks of the '664xx4 are refreshed. The external address and bank-select A12 - A13 are ignored. The execution of a REFR command automatically deactivates all banks upon completion of the internal auto-refresh cycle. This allows consecutive REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not necessarily have to be consecutive, but all 4096 must be completed before tREF expires. self-refresh mode To enter self-refresh mode, all banks of the '664xx4 must be deactivated first and an SLFR command must be executed (see Table 2). The SLFR command is identical to the REFR command except that CKE is low. For proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK when RAS and CAS are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, refreshing signals are generated internally for all banks with all external signals (except CKE) being ignored. Data can be retained by the device automatically for an indefinite period when power is maintained (consumption is reduced to a minimum). To exit self-refresh mode, CKE must be brought high. New commands are issued after tRC has expired. If CLK is made inactive during self-refresh, it must be returned to an active and stable condition before CKE is brought high to exit self-refresh mode (see Figure 19). Prior to entering and upon exiting self-refresh mode, 4096 REFR commands are recommended before continuing with normal device operations. This ensures that the SDRAM is fully refreshed.
interrupted bursts
A read or write can be interrupted before the burst sequence is complete with no adverse effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7 and Table 8, provided that all timing requirements are met. The interruption of READ-P and WRT-P operations is not supported. Table 7. Read-Burst Interruption
INTERRUPTING COMMAND READ, READ-P EFFECT OR NOTE ON USE DURING READ BURST Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met and new output cycles begin (see Figure 3). The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQMx must be high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD-1), nCCD, and (nCCD+1), assuming there is any output on these cycles (see Figure 4). The DQ bus is in the high-impedance state when nHZP cycles are satisfied or upon completion of the read burst, whichever occurs first (see Figure 5 and Figure 22).
WRT, WRT-P
DEAC, DCAB
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interrupted bursts (continued)
nCCD = 2 CLK READ Command at Column Address C0 (see Note A) Interrupting READ Command at Column Address C1 (see Note A)
DQ
C0
C0 + 1
C1
C1 + 1
C1 + 2
First Output Cycle for New READ Command Begins Here a) INTERRUPTED ON EVEN CYCLES nCCD = 3 CLK READ Command at Column Address C0 (see Note A) Interrupting READ Command at Column Address C1 (see Note A)
DQ
C0
C0 + 1
C0 + 2
C1
C1 + 1
First Output Cycle for New READ Command Begins Here b) INTERRUPTED ON ODD CYCLES NOTE A: For this example, assume CAS latency = 2 and burst length > 2.
Figure 3. Read Burst Interrupted by Read Command
nCCD + 1 nCCD - 1 nCCD = 4 CLK READ Command at Column Address C0 (see Note A) Interrupting WRT Command at Column Address C1 (see Note A)
DQ
C0
C1
C1 + 1
C1 + 2
DQMx
See Note B
First Input Cycle for New WRT Command Begins Here
NOTES: A. For this example, read latency = 2 and burst length > 2. B. DQMx must be high to mask output of the read burst on cycles (nCCD-1), (nCCD), and (nCCD+1).
Figure 4. Read Burst Interrupted by Write Command
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interrupted bursts (continued)
nCCD = 2
CLK
READ Command at Column Address C0 (see Note A)
Interrupting DEAC/DCAB Command
nHZP3
DQ
C0
C0 + 1
NOTE A: For this example, assume CAS latency = 3 and burst length > 2.
Figure 5. Read Burst Interrupted by DEAC Command Table 8. Write-Burst Interruption
INTERRUPTING COMMAND READ, READ-P WRT, WRT-P EFFECT OR NOTE ON USE DURING WRITE BURST Data that was input on the previous cycle is written and no further data inputs are accepted (see Figure 6). The new WRT (WRT-P) command and data-in immediately supersede the write burst in progress (see Figure 7). The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to mask the DQ bus such that the write recovery specification (nWR ) is not violated by the interrupt (see Figure 8).
DEAC, DCAB
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interrupted bursts (continued)
nCCD = 2 CLK WRT Command (see Note A) READ Command (see Note A)
DQ
D
D a) INTERRUPTED ON EVEN CYCLES
Q
Q
nCCD = 1 CLK
WRT Command (see Note A)
READ Command (see Note A)
DQ
D b) INTERRUPTED ON ODD CYCLES
Q
Q
Q
NOTE A: For this example, assume CAS latency = 2, burst length > 2.
Figure 6. Write Burst Interrupted by Read Command
nCCD = 2
CLK WRT Command at Column Address C0 (see Note A) DQ C0 C0 + 1 Interrupting WRT-P Command
C1
C1 + 1
C1 + 2
C1 + 3
NOTE A: For this example, burst length > 2.
Figure 7. Write Burst Interrupted by Write Command
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interrupted bursts (continued)
nCCD = 2 CLK WRT Command (see Note A) DEAC or DCAB Command (see Note A)
DQ
D
D nWR
Ignored
DQMx NOTE A: For the purposes of this example, CAS latency = 2 and burst length > 2.
Figure 8. Write Burst Interrupted by DEAC/DCAB Command
power up
Device initialization should be performed after a power up to the full VCC level. After power is established, a 200-s interval is required (with no inputs other than CLK). After this interval, all banks of the device must be deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the device initialization. See Figure 24.
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absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Supply voltage range for output drivers, VCCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Voltage range on any input pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Voltage range on any output pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VCCQ VSS VSSQ VIH VIL Supply voltage Supply voltage for output drivers Supply voltage Supply voltage for output drivers High-level input voltage Low-level input voltage 2 - 0.3 0 3 3 NOM 3.3 3.3 0 0 VCC + 0.3 0.8 70 MAX 3.6 3.6 UNIT V V V V V V C
TA Operating ambient temperature VCCQ VCC 0.3 V
v
)
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electrical characteristics over recommended ranges of supply voltage and operating ambient temperature (unless otherwise noted) (see Note 2)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Operating g current Precharge standby current y in power-down mode Precharge standby current in non-power-down mode Active standby current in power-down mode Active standby current in non-power-down mode Burst current Auto-refresh current Self-refresh current IOH = - 2 mA IOL = 2 mA 0 V VI VCC + 0.3 V, All other pins = 0 V to VCC 0 V VO VCCQ Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA (see Notes 3, 4, and 5) TEST CONDITIONS - 8 (x8 / x4) MIN 2.4 0.4 10 10 CAS latency = 2 CAS latency = 3 115 125 1 1 MAX - 8 (x16) MIN 2.4 0.4 10 10 125 135 1 1 MAX - 8A (x8 / x4) MIN 2.4 0.4 10 10 95 125 1 1 MAX UNIT V V A A mA mA mA mA
ICC1
w
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
CKE VIL MAX, tCK = 15 ns (see Note 6) CKE and CLK (see Note 7)
v w v
v VIL MAX, tCK =
CKE VIH MIN, tCK = 15 ns (see Note 6) tCK =1 (see Note 7) CKE VIL MAX, tCK = 15 ns (see Notes 3 and 6) CKE and CLK VIL MAX, tCK = (see Notes 3 and 7) CKE VIH MIN, tCK = 15 ns (see Notes 3 and 6) (see Notes 3 and 7)
40 5 8 8 50 15 165 225 150 150 1
40 5 8 8 55 15 165 245 150 150 1
40 5 8 8 50 15 120 165 150 150 1
mA mA mA mA mA mA mA mA mA mA mA
v
w CKE w VIH MIN, CLK v VIL MAX, tCK =
Page burst, IOH/IOL = 0 mA All banks activated activated, (see Notes 8, 9, and 10) tRC tRC MIN (see Notes 4 and 7) CKE CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3
ICC5 ICC6
w
v VIL MAX
NOTES: 2. 3. 4. 5. 6. 7. 8. 9. 10.
All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. Only one bank is activated. tRC tRC MIN Control, DQ, and address inputs change state twice during tRC. Control, DQ, and address inputs change state once every 30 ns. Control, DQ, and address inputs do not change state (stable). 4-bank ping-pong, burst length = 4, nCCD = 4 cycles, data pattern 0011. Column address and bank address increment every 4 cycles. A tCK of 10 ns is used to obtain ICC4 for CL3 of the -8A speed grade.
w
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electrical characteristics over recommended ranges of supply voltage and operating ambient temperature (unless otherwise noted) (see Note 2) (continued)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Operating g current Precharge standby current y in power-down mode Precharge standby current in non-power-down mode Active standby current in power-down mode Active standby current in non-power-down mode Burst current Auto-refresh current Self-refresh current IOH = - 2 mA IOL = 2 mA 0 V VI VCC + 0.3 V, All other pins = 0 V to VCC 0 V VO VCCQ Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA (see Notes 3, 4, and 5) TEST CONDITIONS - 8A (x16) MIN 2.4 0.4 10 10 CAS latency = 2 CAS latency = 3 105 135 1 1 MAX - 10 (x8 / x4) MIN 2.4 0.4 10 10 95 105 1 1 MAX - 10 (x16) MIN 2.4 0.4 10 10 105 115 1 1 MAX UNIT V V A A mA mA mA mA
ICC1
w
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
CKE VIL MAX, tCK = 15 ns (see Note 6) CKE and CLK (see Note 7)
v w v
v VIL MAX, tCK =
CKE VIH MIN, tCK = 15 ns (see Note 6) tCK =1 (see Note 7) CKE VIL MAX, tCK = 15 ns (see Notes 3 and 6) CKE and CLK VIL MAX, tCK = (see Notes 3 and 7) CKE VIH MIN, tCK = 15 ns (see Notes 3 and 6) (see Notes 3 and 7)
40 5 8 8 55 15 140 165 150 150 1
40 5 8 8 55 15 120 175 150 150 2
40 5 8 8 60 15 140 200 150 150 2
mA mA mA mA mA mA mA mA mA mA mA
v
w CKE w VIH MIN, CLK v VIL MAX, tCK =
CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3
Page burst, IOH/IOL = 0 mA All banks activated, activated (see Notes 8, 9, and 10) tRC tRC MIN (see Notes 4 and 7) CKE
ICC5 ICC6
w
v VIL MAX
NOTES: 2. 3. 4. 5. 6. 7. 8. 9. 10.
All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. Only one bank is activated. tRC tRC MIN Control, DQ, and address inputs change state twice during tRC. Control, DQ, and address inputs change state once every 30 ns. Control, DQ, and address inputs do not change state (stable). 4-bank ping-pong, burst length = 4, nCCD = 4 cycles, data pattern 0011. Column address and bank address increment every 4 cycles. A tCK of 10 ns is used to obtain ICC4 for CL3 of the -8A speed grade.
w
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capacitance over recommended ranges of supply voltage and operating ambient temperature f = 1 MHz (see Note 11)
PARAMETER Ci(S) Ci(AC) Ci(E) Co Input capacitance, CLK input Input capacitance, address and control inputs: A0 - A13, CS, DQMx, RAS, CAS, W Input capacitance, CKE input Output capacitance 4 MIN 2.5 2.5 MAX 4 5 5 6.5 UNIT pF pF pF pF
NOTE 11: VCC = 3.3 0.3 V and bias on pins under test is 0 V.
ac timing requirements
'664xx4-8 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH2 tOH3 tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA Cycle time, CLK Cycle time, CLK Pulse duration, CLK high Pulse duration, CLK low Access time, CLK high to data out (see Note 12) Access time, CLK high to data out (see Note 12) Hold time, CLK high to data out with 50-pF load Hold time, CLK high to data out with 50-pF load CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3 3 3 1 8 2 1 8 48 68 20 20 16 16 100000 2 1 8 48 68 20 20 16 16 100000 CAS latency = 2 CAS latency = 3 10 8 3 3 6 6 3 3 1 8 2 1 10 50 80 30 30 20 20 100000 MAX '664xx4-8A MIN 15 8 3 3 7.5 6 3 3 2 10 MAX '664xx4-10 MIN 15 10 3 3 7.5 7.5 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Delay time, CLK high to DQ in low-impedance state (see Note 13) Delay time, CLK high to DQ in high-impedance state (see Note 14) Setup time, address, control, and data input Hold time, address, control, and data input Power down/self-refresh exit time (see Note 15) Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, REFR, or SLFR command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 16) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
See Parameter Measurement Information for load circuits (see Figure 9). All references are made to the rising transition of CLK, unless otherwise noted. NOTES: 12. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced from the rising transition of CLK that is CAS latency - one cycle after the READ command. An access time is measured at output reference level 1.5 V. 13. tLZ is measured from the rising transition of CLK that is CAS latency - one cycle after the READ command. 14. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 15. See Figure 18 and Figure 19. 16. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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ac timing requirements (continued)
'664xx4-8 MIN tAPR tAPW tT tREF nWR nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Transition time Refresh interval Delay time, final data in of WRT operation to DEAC or DCAB command Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT command to READ, READ-P, WRT, or WRT-P command Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB command to DQ in high-impedance state Delay time, DEAC or DCAB command to DQ in high-impedance state CAS latency = 2 CAS latency = 3 0 1 1 0 1 1 0 2 0 2 2 3 0 0 0 1 1 5 64 1 1 0 1 1 0 2 0 2 2 3 0 0 0 1 MAX '664xx4-8A MIN MAX '664xx4-10 MIN MAX UNIT ns ns 1 5 64 1 1 0 1 1 0 2 0 2 2 3 0 0 1 ns ms cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
tRP - (CL -1) * tCK tRP + 1 tCK 1 5 64
nWCD Delay time, WRT command to first data in See Parameter Measurement Information for load circuits (see Figure 9). All references are made to the rising transition of CLK, unless otherwise noted.
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PARAMETER MEASUREMENT INFORMATION general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint reference level of 1.5 V (INPUT = 2.8 V, 0 V) for LVTTL. For signal rise and fall times greater than 1 ns, the reference level should be changed to VIH MIN and VIL MAX instead of the midpoint level. All specifications referring to READ commands are valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
Output Under Test Z = 50
CL = 50 pF
Figure 9. ac Load Circuit
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PARAMETER MEASUREMENT INFORMATION
tCK tCH CLK
tCL tT tT tIS tIH
DQ0 - DQ15 (x16), DQ0 - DQ7 (x8), DQ0 - DQ3 (x4), A0 - A13, CS, RAS, CAS, W, DQMx, CKE tT tIS, tCESP tIH DQ0 - DQ15 (x16), DQ0 - DQ7 (x8), DQ0 - DQ3 (x4), A0 - A13, CS, RAS, CAS, W, DQMx, CKE
tT
Figure 10. Input-Attribute Parameters
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PARAMETER MEASUREMENT INFORMATION
CAS Latency
CLK ACTV Command READ Command tAC tLZ tHZ tOH2, tOH3
DQ
Figure 11. Output Parameters
ACTV ACTV DEAC, DCAB REFR ACTV SELF-REFRESH EXIT ACTV MRS READ, WRT DESL Command Disable CLK nCDD
tRAS tRCD tRP tRC tRC tRC tRRD tRSA nCCD (see Note A)
DEAC, DCAB READ, WRT ACTV, MRS, REFR, SLFR ACTV, MRS, REFR, SLFR ACTV, MRS, REFR, SLFR ACTV, MRS, REFR, SLFR ACTV (of a different bank) ACTV, REFR, SLFR, MRS STOP, READ, WRT, DEAC, DCAB
NOTE A: tRRD is specified for command execution in one bank to command execution in another bank.
Figure 12. Command-to-Command Parameters
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PARAMETER MEASUREMENT INFORMATION
nHZP3 CLK
DEAC / DCAB Command DQ (For CL = 3) Final Output of Burst nHZP2
tHZ
DQ (For CL = 2) Final Output of Burst NOTE A: For this example, assume CAS latency = 2, 3 and burst length > 1.
Figure 13. Final Data Output to DEAC or DCAB Command for CAS Latency = 2, 3
CAS Latency = 2 (see Note A) nDOD (for ENBL) CLK nWR
READ Command
nDOD (for MASK) tIS
WRT Command tIH
DEAC/DCAB Command
DQ ENBL Command
Q
D
Ignored MASK Command
DQMx
MASK Command
NOTE A: For this example, assume CAS latency = 2 and burst length = 2.
Figure 14. DQ Masking
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PARAMETER MEASUREMENT INFORMATION
CAS Latency = 2 (see Note A) tAPR CLK
READ-P Command
ACTV Command
DQ
Q
Q
NOTE A: For this example, assume CAS latency = 2 and burst length = 2.
Figure 15. Read Automatic-Deactivate (Autoprecharge)
tAPW
CLK WRT - P Command ACTV Command
DQ
D
D
NOTE A: For this example, the burst length = 2.
Figure 16. Write Automatic-Deactivate (Autoprecharge)
nCLE CLK tIH
nCLE
DQ
Q tIH
Q
Q
Q
(Assume Final Data Output of Burst)
tIS CKE
tIS
Figure 17. CLK-Suspend Operation (Assume Burst Length = 4)
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PARAMETER MEASUREMENT INFORMATION
CLK Last Data-In WRT (WRT-P) Operation CLK Is Don't Care, But Must Be Stable Before CKE High Last Data-out READ (READ-P) Operation CKE tIH tIS tCESP Exit Power-Down Mode If tCESP Is Satisfied (New Command)
Enter Power-down Mode
CLK Last Data-In WRT (WRT-P) Operation CLK Is Don't Care, But Must Be Stable Before CKE High Last Data-Out READ (READ-P) Operation CKE tIH tIS tCESP DESL or NOOP Command Only If tCESP Is Not Satisfied Exit Power-Down Mode (New Command)
Enter Power-Down Mode
Figure 18. Power-Down Operation
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PARAMETER MEASUREMENT INFORMATION
CLK
CLK Is Don't Care, But Must Be Stable Before CKE High SLFR Both Banks Command Deactivated tIS CKE tIH
Exit SLFR If tCESP Is Satisfied DESL or NOOP Only Until tRC Is Satisfied
ACTV, MRS, or REFR Command
tRC tCESP
CLK Exit SLFR
CLK Is Don't Care, But Must Be Stable Before CKE High SLFR Both Banks Command Deactivated tIS CKE tIH
tCESP Not Yet Satisfied
ACTV, MRS, or REFR Command
DESL or NOOP Only Until tRC Is Satisfied
tRC tCESP
NOTES: A. Assume both banks are deactivated before the execution of SLFR. B. Before/after self-refresh mode, 4K burst auto-refresh cycles are recommended to ensure that the SDRAM is fully refreshed.
Figure 19. Self-Refresh Entry/Exit
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PARAMETER MEASUREMENT INFORMATION
CLK DEAC/DCAB Command nHZP2 Q Q Q Q
Final Input of Write Burst (CL = 2) DQ Final Input of Write Burst (CL = 3) DQ D D D READ Command (CL = 3)
READ Command (CL = 2)
nHZP3
Q
Q
Q
Q
Q
NOTE A: Assume burst length = 8.
Figure 20. Write Burst Followed by DEAC/DCAB-Interrupted Read
nCWL CLK WRT Command
nWR
WRT Command
DEAC/DCAB Command
DQ NOTE A: For this example, assume burst length = 1.
D
D
Figure 21. Write Followed by Deactivate
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PARAMETER MEASUREMENT INFORMATION
nHZP3
CLK
READ Command
DEAC or DCAB Command tHZ
DQ
Q
Q
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 22. Read Followed by Deactivate
tAPR CLK
READ-P Command
Final Data Out
ACTV, MRS, REFR, or SLFR Command
DQ
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 23. Read With Auto-Deactivate
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DCAB Command CLK tCK 200 s
REFR #1 Command
REFR #8 Command
MRS New Command Command Can Start Entering Here
tRC tRSA
VCC VCCQ RAS
tIS
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PARAMETER MEASUREMENT INFORMATION
CAS
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tIH
W
A10
A11 - A13
A0 - A9 A9 = V A7, A8 = V A0 - A6 = V (see Note A)
Mode
DQ DQMx
Hi-Z
SMOS695A - APRIL 1998 - REVISED JULY 1998
CS
CKE Time Lapse NOTE A: Refer to the section titled "Setting the Mode Register". Time Lapse Time Lapse
Figure 24. Power-Up Sequence
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PARAMETER MEASUREMENT INFORMATION
ACTV_0 CLK tRCD READ_0 DEAC_0
DQ
a
b
c
d
DQMx
RAS
CAS
W
A13
A12
A11
R0
A10
R0
A0 - A9
R0
C0
CS
CKE BURST TYPE (D/Q) Q
BANK (0 - 3) 0
ROW ADDR R0 a C0
BURST CYCLE b C0 + 1 c C0 + 2 d C0 + 3
Column-address sequence depends on programmed burst type and starting address C0 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 25. Read Burst (CAS latency = 3, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_3 CLK tRCD nWR DQ a b c d e f g h WRT_3 DEAC_3
DQMx
RAS
CAS
W
A13
A12
A11
R0
A10
R0
A0 - A9
R0
C0
CS
CKE BURST TYPE (D/Q)
BANK (0 - 3)
ROW ADDR a C0 b c
BURST CYCLE d e f g h
D 3 R0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7 Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD and nWR for the '664xx4 at 125 MHz.
Figure 26. Write Burst (burst length = 8)
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PARAMETER MEASUREMENT INFORMATION
ACTV_1 CLK tRCD DQ a b c d WRT_1 READ_1 DEAC_1
DQMx
RAS
CAS
W
A13
A12
A11
R0
A10
R0
A0 - A9
R0
C0
C1
CS
CKE BURST TYPE (D/Q) D Q
BANK (0 - 3) 1 1
ROW ADDR R0 R0 a C0
BURST CYCLE b C0 + 1 c d
C1 C1 + 1 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 4). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 27. Write-Read Burst (CAS latency = 3, burst length = 2)
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ACTV_2 CLK tRCD DQ DQMx RAS CAS
READ_2
WRT-P_2
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
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W A13
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PARAMETER MEASUREMENT INFORMATION
A12 A11 A10 A0 - A9 CS CKE R0 R0 R0 C0 C1
BURST TYPE (D/Q) Q D
BANK (0 -3) 2 2
ROW ADDR R0 R0 a C0 b C0 + 1 c C0 + 2 d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6
BURST CYCLE h C0 + 7 C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7 i j k l m n o p
SMOS695A - APRIL 1998 - REVISED JULY 1998
C1 Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 28. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
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38 CLK DQ DQMx RAS CAS W A13
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ACTV_0
READ-P_0
ACTV_1
READ-P_1
ACTV_2
READ-P_2
ACTV_3
Template Release Date: 7-11-94
tRCD a b c
tRCD d e f g h i j k
tRCD l m n o p q r s
PARAMETER MEASUREMENT INFORMATION
A12 A11 A10 A0 - A9 CS CKE
BURST TYPE (D/Q) Q Q Q
R0 R0 R0 C0
R1 R1 R1 C1
R2 R2 R2 C2
R3 R3 R3
BANK (0 -3) 0 1 2
ROW ADDR R0 R1 R2 a C0 b C0 + 1 c C0 + 2 d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7 C1 i
BURST CYCLE j k l m n o p q r s ...
C1 + 1
C1 + 2
C1 + 3
C1 + 4
C1 + 5
C1 + 6
C1 + 7 C2 C2 + 1 C2 + 2 ...
Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 29. [A] Four-Bank Row-Interleaving Burst Length of 8 With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV_0 CLK tRCD DQ DQMx RAS
READ-P_0 ACTV_1
READ-P_1 ACTV_2
READ-P_2 ACTV_3
READ-P_3 ACTV_0
READ-P_0 ACTV_1
READ-P_1
tRCD a b c
tRCD d e f g
tRCD h i j k l
tRCD m n o
tRCD p q r s
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CAS W
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PARAMETER MEASUREMENT INFORMATION
A13 A12 A11 A10 A0 - A9 CS CKE R0 R0 R0 C0 R1 R1 R1 C1 R2 R2 R2 C2 R3 R3 R3 C3 R4 R4 R4 C4 R5 R5 R5 C5
BURST TYPE (D/Q) Q Q Q Q Q
BANK (0 -3) 0 1 2 3 0
ROW ADDR R0 R1 R2 R3 R4 a C0 b C0 + 1 c C0 + 2 d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 C2 e f g h i
BURST CYCLE j k l m n o p q r s ...
SMOS695A - APRIL 1998 - REVISED JULY 1998
C2 + 1
C2 + 2
C2 + 3 C3 C3 + 1 C3 + 2 C3 + 3 C4 C4 + 1 C4 + 2 ...
Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 29. [B] Four-Bank Row-Interleaving Burst Length of 4 With Automatic Deactivate (CAS latency = 3, burst length = 4) (Cont'd)
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PARAMETER MEASUREMENT INFORMATION
ACTV_0 CLK a c e ACTV_1 ACTV_2 ACTV_3 READ_0 READ_1 READ_2 READ_3 READ_0
DQ
b
d
f
DQMx
RAS
CAS
W
A13
A12 R0 R1 R2 R3
A11
A10
R0
R1
R2
R3
A0 - A9
R0
R1
R2
R3
C0
C1
C2
C3
C4
CS
CKE BURST TYPE (D/Q) Q Q Q Q BANK (0 -3) 0 1 2 3 ROW ADDR R0 R1 R2 R3 a C0 b C0 + 1 C1 C1 + 1 C2 C2 + 1 C3 C3 + 1 ... ... c d BURST CYCLE e f g h ... ...
... ... ... Column-address sequence depends on programmed burst type and starting addresses C0, C1, and C2 (see Table 4).
Figure 30. Four-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
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PARAMETER MEASUREMENT INFORMATION
READ_0 ACTV_2
ACTV_0 CLK tRCD DQ DQMx RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q BANK (0 - 3) 0 ROW ADDR R0 R0 R0 R0
DEAC_0
WRT_2
DEAC_2
a
b
c
d
e
f
g
h
R1 R1 C0 R1 C1
BURST CYCLE a C0 b C0 + 1 c C0 + 2 d C0 + 3 e f g h
D 2 R1 C1 C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 31. Read-Burst Bank 0, Write-Burst Bank 1 (CAS latency = 3, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_3 CLK tRRD nCWL DQ tRCD DQMx a b c d e f g ACTV_0 WRT-P_3 READ-P_0
RAS
CAS
W
A13
A12
A11
R0
R1
A10
R0
R1
A0 - A9
R0
R1
C0
C1
CS
CKE BURST TYPE (D/Q) D
BANK (0 -3) 3
ROW ADDR R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e f g h
Q 0 R1 C1 C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum nCWL,tRRD, and tRCD for the '664xx4 at 125 MHz.
Figure 32. Write-Burst Bank 3, Read-Burst Bank 0 With Automatic Deactivate (CAS latency = 3, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_1 CLK tRCD DQ a nDOD DQMx e b c d f g h READ_1 ACTV_0 WRT_0 DCAB
RAS
CAS
W
A13
A12
A11
R0
R1
A10
R0
R1
A0 - A9
R0
C0
R1
C1
CS
CKE BURST TYPE (D/Q) Q BANK (0 -3) 1 ROW ADDR R0 a C0 b C0 + 1 c C0 + 2 BURST CYCLE d C0 + 3 e f g h
D 0 R1 C1 C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 100 MHz.
Figure 33. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0, Deactivate All Banks) (CAS latency = 2, burst length = 4)
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REFR CLK tRC
REFR
ACTV_3
READ_3
DEAC_3
REFR
44 DQ DQMx RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE
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Template Release Date: 7-11-94
tRCD tRC a b c d e f g h
tRP
PARAMETER MEASUREMENT INFORMATION
R0 R0 R0 C0
BURST TYPE (D/Q) Q
BANK (0 -3) 3
ROW ADDR R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7
Column-address sequence depends on programmed burst type and starting address C0 (see Table 6). NOTE A: This example illustrates minimum tRC, tRCD, and tRP for the '664xx4 at 100 MHz.
Figure 34. Refresh Cycles (Refreshes Followed by Read Burst, Followed by Refresh) (CAS latency = 2, burst length = 8)
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PARAMETER MEASUREMENT INFORMATION
DCAB CLK tRSA DQ tRCD a b c d MRS ACTV_0 WRT-P_0
DQMx
RAS
CAS
W See Note A A13 See Note A A12 See Note A A11 See Note A A10 See Note A A0 - A9 R0 C0 R0 R0
CS
CKE BURST TYPE (D/Q) D BANK (0 -3) 0 ROW ADDR R0 a C0 BURST CYCLE b C0 + 1 c C0 + 2 d C0 + 3
Column-address sequence depends on programmed burst type and starting address C0 (see Table 5). NOTES: A. Refer to Figure 2 (for setting mode registers) B. This example illustrates minimum tRCD and tRSA for the '664xx4 at 125 MHz.
Figure 35. Mode-Register Programming (Deactivate All, Mode Program, Write Burst With Automatic Deactivate) (CAS latency = 3, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_3 CLK tRCD nCLE a b c d e f g h READ-P_3 HOLD ACTV_0 WRT-P_0
DQ DQMx RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE
R0 R0 R0 C0
R1 R1 R1 C1
BURST TYPE (D/Q) Q
BANK (0 -3) 3
ROW ADDR R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e f g h
D 0 R1 C1 C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTES: A. This example illustrates minimum tRCD and tAPW for the '664xx4 at 100 MHz. B. If entering the PDE command with violation of short tAPW, the device is still entering the power-down mode and then both banks are deactivated (still in power-down mode).
Figure 36. Use of CKE for Clock Gating (Hold) and Standby Mode (Read-Burst Bank 3 With Hold, Write-Burst Bank 0, Standby Mode) (CAS latency = 2, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
READ_0 ACTV_0 CLK tRCD nHZP3 DQ0 - DQ7 DQ8 - DQ15 DQMU DQML RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q D BANK (0 -3) 0 1 ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2 BURST CYCLE d C0 + 3 C1 e f g h R0 R0 R0 C0 R1 R1 R1 C1 a b c d e f g h nWR ACTV_1 DEAC_0 WRT_1 DEAC_1
C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD read burst, and a minimum nWR write burst for the '664xx4 at 125 MHz.
Figure 37. Read-Burst Bank 0, Write-Burst Bank 1 (With Lower Bytes Masked Out During the READ Cycles and Upper Bytes Masked Out During the WRITE Cycles) (Only for x16) (CAS latency = 3, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_1 CLK tRCD DQ0 - DQ7 DQML DQ8 - DQ15 DQMU RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q D BANK (0 -3) 1 0 ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2 BURST CYCLE d C0 + 3 C1 e f g h R0 R0 R0 C0 R1 R1 R1 C1 a b c d e f g h a b c d f nWR h READ_1 ACTV_0 WRT_0 DCAB
C1 + 1 C1 + 2 C1 + 3 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTE A: This example illustrates minimum tRCD and a minimum nWR write burst for the '664xx4 at 100 MHz.
Figure 38. Use of DQM for Output and Data-In Cycle Masking (Read-Burst Bank 1, Write-Burst Bank 0, Deactivate All Banks) [Only Masked Out the Lower Bytes (Random Bits)] for x16 (CAS latency = 2, burst length = 4)
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PARAMETER MEASUREMENT INFORMATION
ACTV_0 ACTV_2 ACTV_3 READ_2 ACT1 READ_3 READ_1 READ_0 READ_0 CLK tRCD DQ0 - DQ7 tRRD DQ8 - DQ15 Hi-Z a b c d e f h
DQMU
DQML
RAS
CAS
W
A13
A12
A11
R0
R2
R3
R1
A10
R0
R2
R3
R1
A0 - A9
R0
R2
C0
R3
C2
R1
C3
C1
C4
CS
CKE BURST TYPE (D/Q) Q Q Q Q BANK (0 -3) 0 2 3 1 ROW ADDR R0 R2 R3 R1 a C0 b C0 + 1 C2 C2 + 1 C3 C3 + 1 c BURST CYCLE d e f g h
C1 C1 + 1 Column-address sequence depends on programmed burst type and starting addresses C0, C1, C2, and C3 (see Table 4). NOTE A: This example illustrates minimum tRCD and minimum tRRD for the '664xx4 at 125 MHz.
Figure 39. Four-Bank Column-Interleaving Read Bursts (With Upper Bytes to be Masked) (Only for x16) (CAS latency = 3, burst length = 2)
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49
SMOS695A - APRIL 1998 - REVISED JULY 1998
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
ACTV_1 CLK tRCD DQ DQMx RAS CAS W A13
READ_1
WRT-P_1
50
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Template Release Date: 7-11-94
a
b
c
d
e
f
g
h
i
PARAMETER MEASUREMENT INFORMATION
A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q R0 R0 R0 C0 C1
BANK (0 -3) 1
ROW ADDR R0 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 e C0 + 4 f C0 + 5 g C0 + 6 h C0 + 7 i
D 1 R0 C1 Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 40. Read Burst -- Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A- APRIL 1998 - REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_0 CLK READ-P_0
tRCD
DQ n n+1 n+2 n+3 n+4 n+5 n+6 n+7
DQMx
RAS
CAS
W
A13
A12
A11
R0
A10
R0
A0 - A9
R0
C0
CS
CKE
BURST TYPE (D/Q) Q
BANK (0 - 3) 0
ROW ADDR R0 n C0 n+1 C0 + 1 n+2 C0 + 2
BURST CYCLE n+3 C0 + 3 n+4 C0 + 4 n+5 C0 + 5 n+6 C0 + 6 n+7 C0 + 7
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 6). NOTE A: This example illustrates minimum tRCD for the '664xx4 at 125 MHz.
Figure 41. Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8) (for x16)
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51
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A- APRIL 1998 - REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_1 CLK tRCD DQ DQMx See Note A RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q D 1 0 BANK (0 - 1) R0 R0 R0 R0 C0 R1 R1 R1 R1 C1 a b c d e f g h READ-P_1 HOLD ACTV_0 WRT-P_0
ROW ADDR R0 R1 a C0 b C0 + 1 c C0 + 2
BURST CYCLE d C0 + 3 C1 C1 + 1 C1 + 2 C1 + 3 e f g h
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTES: A. These rising clocks during output "c" with DQMx = Hi do not mask out the output "d" due to CKE inserted low to suspend those rising clocks at cycle DQMx = Hi. B. This example illustrates minimum tRCD for the '664xx4 at 100 MHz.
Figure 42. Use of CKE for Clock Gating (Hold/Suspend) and DQM = Hi Showed No Effect (CAS latency = 2, burst length = 4, two banks)
52
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A- APRIL 1998 - REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
ACTV_1 CLK DQ DQMx See Note A RAS CAS W A13 A12 A11 A10 A0 - A9 CS CKE BURST TYPE (D/Q) Q 1 BANK (0 - 1) R0 R0 R0 R0 C0 tRCD a b d READ-P_1 HOLD
c
ROW ADDR R0 a C0
BURST CYCLE b C0 + 1 c C0 + 2 d C0 + 3
Column-address sequence depends on programmed burst type and starting addresses C0 and C1 (see Table 5). NOTES: A. This example illustrates that the DQM mask is also delayed when a HOLD/Suspend is in progress. B. This example illustrates minimum tRCD for the '664xx4 at 100 MHz.
Figure 43. DQMx Mask Delay As the Hold/Suspend In Progress (CAS latency = 2, burst length = 4)
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
53
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A- APRIL 1998 - REVISED JULY 1998
device symbolization
TI TMS664xx4 DGE Package Code W B Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code -SS Speed Code (-8, -8A, -10)
54
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A- APRIL 1998 - REVISED JULY 1998
MECHANICAL DATA
DGE (R-PDSO-G54)
0.018 (0,45) 0.012 (0,30) 28
PLASTIC SMALL-OUTLINE PACKAGE
0.031 (0,80) 54
0.006 (0,16) M
0.471 (11,96) 0.455 (11,56) 0.404 (10,26) 0.396 (10,06)
1 0.879 (22,32) 0.871 (22,12)
27 0.006 (0,15) NOM
Gage Plane 0.010 (0,25) 0- 5 0.024 (0,60) 0.016 (0,40)
Seating Plane 0.047 (1,20) MAX 0.000 (0,00) MIN 0.004 (0,10)
4040070-6/C 12/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion.
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Copyright (c) 1998, Texas Instruments Incorporated

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