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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
HIGH OUTPUT RS-485 TRANSCEIVERS
FEATURES D Minimum Differential Output Voltage of 2.5 V D D D D D D D D
Into a 54- Load Open-Circuit, Short-Circuit, and Idle-Bus Failsafe Receiver 1/8th Unit-Load Option Available (Up to 256 Nodes on the Bus) Bus-Pin ESD Protection Exceeds 16 kV HBM Driver Output Slew Rate Control Options Electrically Compatible With ANSI TIA/EIA-485-A Standard Low-Current Standby Mode . . . 1 A Typical Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications Pin Compatible With Industry Standard SN75176
DESCRIPTION
The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.
D OR P PACKAGE (TOP VIEW)
APPLICATIONS D Data Transmission Over Long or Lossy Lines D D D D D D
or Electrically Noisy Environments Profibus Line Interface Industrial Process Control Networks Point-of-Sale (POS) Networks Electric Utility Metering Building Automation Digital Motor Control
DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL OUTPUT CURRENT
5 V O - Differential Output Voltage - V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 IOD - Differential Output Current - mA 60 Load Line TA = 25C DE at VCC D at VCC VCC = 5 V 30 Load Line
R RE DE D
1 2 3 4
8 7 6 5
VCC B A GND
LOGIC DIAGRAM (POSITIVE LOGIC) R RE 1 2
DE D
3 6 4 7 A B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002-2003, Texas Instruments Incorporated
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MARKED AS SIGNALING RATE UNIT LOAD DRIVER OUTPUT SLOPE CONTROL No Yes Yes No Yes -0C to 70C 0 C 70 C -40C to 85C 40 C 85 C TA PART NUMBER(2) PLASTIC DUAL-IN-LINE PACKAGE (PDIP) 65HVD05 65HVD06 65HVD07 75HVD05 75HVD06 SMALL OUTLINE IC (SOIC) PACKAGE VP05 VP06 VP07 VN05 VN06 VN07
40 Mbps 10 Mbps 1 Mbps 40 Mbps 10 Mbps
1/2 1/8 1/8 1/2 1/8
SN65HVD05D SN65HVD06D SN65HVD07D SN75HVD05D SN75HVD06D
SN65HVD05P SN65HVD06P SN65HVD07P SN75HVD05P SN75HVD06P
1 Mbps 1/8 Yes SN75HVD07D SN75HVD07P 75HVD07 (1) For the most current specification and package information, refer to our web site at www.ti.com. (2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
PACKAGE DISSIPATION RATINGS (SEE FIGURE 12 AND FIGURE 13)
PACKAGE D(2) D(3) P TA 25C POWER RATING 710 mW 1282 mW 1000 mW DERATING FACTOR(1) ABOVE TA = 25C 5.7 mW/C 10.3 mW/C 8.0 mW/C TA = 70C POWER RATING 455 mW 821 mW 640 mW TA = 85C POWER RATING 369 mW 667 mW 520 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3 (3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2) SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07 Supply voltage range, VCC Voltage range at A or B Input voltage range at D, DE, R or RE Voltage input range, transient pulse, A and B, through 100 (see Figure 11) Electrostatic discharge Human body model(3) Charged-device model(4) Continuous total power dissipation Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds A, B, and GND All pins All pins -0.3 V to 6 V -9 V to 14 V -0.5 V to VCC + 0.5 V -50 V to 50 V 16 kV 4 kV 1 kV See Dissipation Rating Table -65C to 150C 260C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VCC Voltage at any bus terminal (separately or common mode) VI or VIC High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID (see Figure 7) Driver High-level High level output current IOH current, Low-level Low level output current IOL current, Receiver Driver Receiver SN65HVD05 SN65HVD06 SN65HVD07 Operating free air temperature TA free-air temperature, SN75HVD05 SN75HVD06 SN75HVD07 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. 0 70 C C -40 40 85 C C D, DE, RE D, DE, RE -12 -100 -8 100 8 mA mA 4.5 -7(1) 2 0.8 12 NOM MAX UNIT 5.5 12 V V V V V
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1) PARAMETER VIK |VOD| |VOD| VOC(SS) VOC(SS) Input clamp voltage Differential out ut voltage output Change in magnitude of differential output voltage Steady-state common-mode output voltage Change in steady-state common-mode output voltage HVD05 VOC(PP) IOZ II IOS C(diff) Peak-to-peak commonPeak to peakcommon mode output voltage HVD06 HVD07 See receiver input currents -100 0 -7 V VO 12 V VID = 0.4 sin (4E6t) + 0.5 V, DE at 0 V RE at VCC, Receiver disabled and D & DE at VCC, No load driver enabled Receiver disabled and RE at VCC, D at VCC driver disabled DE at 0 V, No load (standby) RE at 0 V, D & DE at VCC, No load (1) All typical values are at 25C and with a 5-V supply. Receiver enabled and driver enabled -250 16 9 15 0 100 250 A mA pF mA A mA D DE See Figure 3 II = -18 mA No Load RL = 54 , See Figure 1 Vtest = -7 V to 12 V, See Figure 2 See Figure 1 and Figure 2 TEST CONDITIONS MIN TYP(1) -1.5 VCC 2.5 2.2 -0.2 2.2 See Figure 3 -0.1 600 500 900 mV 0.1 V 0.2 3.3 V V V MAX UNIT V
High-impedance output current Input current Short-circuit output current Differential output capacitance
ICC
Supply current
1
5
9
15
3
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
www.ti.com
DRIVER SWITCHING CHARACTERISTICS NIL
over operating free-air temperature range unless otherwise noted PARAMETER HVD05 tPLH Pro agation Propagation delay time, low to high level out ut low-to-high-level output HVD06 HVD07 HVD05 tPHL Pro agation Propagation delay time, high to low level out ut high-to-low-level output HVD06 HVD07 HVD05 tr Differential out ut signal rise time output HVD06 HVD07 HVD05 tf Differential out ut signal fall time output HVD06 HVD07 HVD05 tsk(p) sk( ) Pulse skew (|tPHL - tPLH|) HVD06 HVD07 HVD05 tsk(pp)(2) sk( ) Part to art Part-to-part skew HVD06 HVD07 HVD05 tPZH1 Pro agation Propagation delay time, high im edance to high level out ut high-impedance-to-high-level output HVD06 HVD07 HVD05 tPHZ Pro agation Propagation delay time, high level to high im edance out ut high-level-to-high-impedance output HVD06 HVD07 HVD05 tPZL1 Pro agation Propagation delay time, high im edance to low level out ut high-impedance-to-low-level output HVD06 HVD07 HVD05 tPLZ Pro agation Propagation delay time, low level to high im edance out ut low-level-to-high-impedance output HVD06 HVD07 tPZH2 Propagation delay time, standby-to-high-level output RL = 110 , RE at 3 V, See Figure 5 RL = 110 , RE at 3 V, See Figure 6 RE at 0 V, RL = 110 , See Figure 6 RE at 0 V, RL = 110 , See Figure 5 RL = 54 , CL = 50 pF, F, See Figure 4 2.7 18 150 2.7 18 150 TEST CONDITIONS MIN TYP(1) 6.5 27 250 6.5 27 250 3.6 28 300 3.6 28 300 MAX 11 40 400 11 40 400 6 55 450 6 55 450 2 2.5 10 3.5 14 100 25 45 250 25 60 250 15 45 200 14 90 550 6 s ns ns ns ns ns ns ns ns ns ns UNIT
tPZL2
Propagation delay time, standby-to-low-level output
6
s
(1) All typical values are at 25C and with a 5-V supply. (2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted PARAMETER VIT+ VIT- Vhys VIK VOH VOL IOZ Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage (VIT+ - VIT-) Enable-input clamp voltage High-level output voltage Low-level output voltage High-impedance-state output current II = -18 mA VID = 200 mV, VID = -200 mV, VO = 0 or VCC -1.5 IOH = -8 mA, IOL = 8 mA, RE at VCC VA or VB = 12 V VA or VB = 12 V, VA or VB = -7 V VA or VB = -7 V, VA or VB = 12 V VA or VB = 12 V, VA or VB = -7 V VA or VB = -7 V, See Figure 7 See Figure 7 -1 0.23 VCC = 0 V -0.4 VCC = 0 V VCC = 0 V -0.1 VCC = 0 V -0.05 -60 -60 -0.4 0.3 -0.13 -0.15 0.06 0.08 -0.05 -0.03 -26.4 -27.4 16 5 10 A A pF mA 0.1 0.13 mA 4 0.4 1 0.5 0.5 mA IO = -8 mA IO = 8 mA -0.2 35 TEST CONDITIONS MIN TYP(1) MAX -0.01 UNIT V V mV V V V A
HVD05 II Bus input current HVD06, HVD07 IIH IIL C(diff) High-level input current, RE Low-level input current, RE Differential input capacitance
Other in ut input at 0 V
Other in ut input at 0 V VIH = 2 V VIL = 0.8 V
VI = 0.4 sin (4E6t) + 0.5 V, DE at 0 V RE at 0 V, D & DE at 0 V, Receiver enabled and driver disabled No load RE at VCC, DE at 0 V, D at VCC, No load RE at 0 V, D & DE at VCC, No load Receiver disabled and driver disabled (standby)
ICC
Supply current
1
5
A
Receiver enabled and driver enabled
9
15
mA
(1) All typical values are at 25C and with a 5-V supply.
5
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
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RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted PARAMETER tPLH tPHL tPLH tPHL Propagation delay time, low-to-high-level output 1/2 UL Propagation delay time, high-to-low-level output 1/2 UL Propagation delay time low-to-high-level output 1/8 UL time, low to high level Propagation delay time high-to-low-level output 1/8 UL time, high to low level HVD05 HVD05 HVD06 HVD07 HVD06 HVD07 HVD05 tsk(p) sk( ) Pulse skew (|tPHL - tPLH|) HVD06 HVD07 HVD05 tsk( )(2) sk(pp)( ) tr tf tPZH1 tPZL1 tPHZ tPLZ tPZH2 tPZL2 Part to art Part-to-part skew Output signal rise time Output signal fall time Output enable time to high level Output enable time to low level Output disable time from high level Output disable time from low level Propagation delay time, standby-to-high-level output Propagation delay time, standby-to-low-level output CL = 15 pF, DE at 0, F, See Figure 10 CL = 15 pF, DE at 3 V V, See Figure 9 HVD06 HVD07 CL = 15 pF, F, See Figure 8 2 2 VID = -1.5 V to 1.5 V, CL = 15 pF, F, See Figure 8 TEST CONDITIONS MIN TYP(1) 14.6 14.6 55 55 55 55 MAX 25 25 70 70 70 70 2 4.5 4.5 6.5 14 14 3 3 10 10 15 15 6 6 s s ns ns ns ns ns ns UNIT ns ns
(1) All typical values are at 25C and with a 5-V supply. (2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
VCC II 0 or 3 V B VI VOB VOA IOB DE A IOA VOD 54 1% D 0 or 3 V B 375 1% VCC DE A VOD 60 1% + -7 V < V(test) _ < 12 V 375 1%
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
A VA VB VOC(PP) VOC(SS)
VCC DE Input D A
27 1%
B
27 1% B CL = 50 pF 20%
VOC
VOC
CL Includes Fixture and Instrumentation Capacitance Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
VCC DE D Input Generator VI 50 A B CL = 50 pF 20% VOD RL = 54 1% CL Includes Fixture and Instrumentation Capacitance VI tPLH VOD 0V 10% tr Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 tf 1.5 V tPHL 90% 90% 1.5 V 0V 2V 0V 10% -2 V 3V
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
A 3V D B DE Input Generator VI CL = 50 pF 20% RL = 110 1% 0.5 V tPZH(1 & 2) VOH VO 2.3 V tPHZ Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 0V 3V S1 VO VI 1.5 V 1.5 V 0V
50 CL Includes Fixture and Instrumentation Capacitance
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
7
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
www.ti.com
VCC RL = 110 1% S1 VO DE Input Generator VI 50 B CL = 50 pF 20% CL Includes Fixture and Instrumentation Capacitance VO 2.3 V VOL tPZL(1 & 2) tPLZ VCC 0.5 V VI 1.5 V 1.5 V 0V 3V
A 3V D
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA VA VIC VB VID IB A R B VO
IO
VA + VB 2
Figure 7. Receiver Voltage and Current Definitions
A Input Generator R VI 50 1.5 V 0V B RE VO CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance VI tPLH VO 1.5 V 10% tr tf 1.5 V tPHL 90% 90% 1.5 V 0V VOH 1.5 V 10% V OL 3V
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
A 0 V or 3 V Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Input Generator D B DE RE VI 50
3V
A VCC S1 B 1 k 1% CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance VO R
3V VI 1.5 V 1.5 V 0V tPZH(1) tPHZ VOH -0.5 V VO 1.5 V 0V tPZL(1) tPLZ VCC VO 1.5 V VOL +0.5 V D at 0 V S1 to A VOH D at 3 V S1 to B
VOL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
9
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
www.ti.com
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Input Generator
0V
DE RE
VI
50
VCC
A S1 B 1 k 1% CL = 15 pF 20% CL Includes Fixture and Instrumentation Capacitance VO R
A B
0 V or 1.5 V 1.5 V or 0 V
3V VI 1.5 V 0V tPZH(2) A at 1.5 V B at 0 V S1 to B VOH VO 1.5 V GND tPZL(2) A at 0 V B at 1.5 V S1 to A VCC VO 1.5 V VOL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V A 100 1% + _ DE 3 V or 0 V NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified. B RE R
Pulse Generator, 15 s Duration, 1% Duty Cycle tr, tf 100 ns
D
Figure 11. Test Circuit, Transient Over Voltage Test
10
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
FUNCTION TABLES
DRIVER INPUT D H L X Open X ENABLE DE H H L H Open OUTPUTS A H L Z H Z B L H Z L Z
RECEIVER DIFFERENTIAL INPUTS VID = VA - VB VID -0.2 V -0.2 V < VID < -0.01 V -0.01 V VID X Open Circuit Short Circuit X ENABLE RE L L L H L L Open OUTPUT R L ? H Z H H Z
H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
11
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs VCC 100 k 1 k Input 9V 9V Input 100 k 1 k DE Input VCC
A Input VCC 16 V 100 k Input 16 V R2 16 V R3 R1 Input 100 k 16 V
B Input VCC R1
R3
R2
A and B Outputs VCC 16 V VCC
R Output
5 Output 16 V
Output 9V
SN65HVD05 SN65HVD06 SN65HVD07
R1/R2 9 k 36 k 36 k
R3 45 k 180 k 180 k
12
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
TYPICAL CHARACTERISTICS
HVD05
HVD06
MAXIMUM RECOMMENDED STILL-AIR OPERATING TEMPERATURE vs SIGNALING RATE (D - PACKAGE)
MAXIMUM RECOMMENDED STILL-AIR OPERATING TEMPERATURE vs SIGNALING RATE (D - PACKAGE)
Maximum Recommended Still-Air Operating Temperature - T A ( C)
Maximum Recommended Still-Air Operating Temperature - T A ( C)
85
High K Board
25
Low K Board
1
10 Signaling Rate - Mbps
40
Figure 12
HVD05
RMS SUPPLY CURRENT vs SIGNALING RATE
120 110 I CC - RMS Supply Current - mA 100 90 80 70 60 50 40 30 0 5 10 15 20 25 30 35 40 Signaling Rate - Mbps 40 0 TA = 25C RE at VCC DE at VCC RL = 54 CL = 50 pF VCC = 5 V I CC - RMS Supply Current - mA 120
100
80
60
Figure 14
OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO OOOOOOOOOOOOO
85 High K Board 25 Low K Board 1 10 Signaling Rate - Mbps
OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO OOOOOOOOOOOO
Figure 13
HVD06
RMS SUPPLY CURRENT vs SIGNALING RATE
TA = 25C RE at VCC DE at VCC RL = 54 CL = 50 pF VCC = 5 V
2.5
5
7.5
10
Signaling Rate - Mbps
Figure 15
13
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
www.ti.com
HVD07
RMS SUPPLY CURRENT vs SIGNALING RATE
110 100 90 80 70 60 50 40 100 TA = 25C RE at VCC DE at VCC RL = 54 CL = 50 pF VCC = 5 V I I - Bus Input Current - A 250 200 150 100 50 0 -50 -100 -150 TA = 25C DE at 0 V VCC = 5 V
BUS INPUT CURRENT vs BUS INPUT VOLTAGE
I CC - RMS Supply Current - mA
HVD05
HVD06 HVD07
400 700 Signaling Rate - kbps
1000
-200 -7 -6-5 -4-3 -2-1 0 1 2 3 4 5 6 7 8 9 10 11 12 VI - Bus Input Voltage - V
Figure 16
DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
0 I OH - Driver High-Level Output Current - mA I OL- Driver Low-Level Output Current - mA -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - High-Level Output Voltage - V TA = 25C DE at VCC D at VCC VCC = 5 V 160 140 120 100 80 60 40 20 0 0 0.5 TA = 25C DE at VCC D at 0 V VCC = 5 V
Figure 17
DRIVER LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
1 1.5 2 2.5 3 3.5 4 4.5 VO - Low-Level Output Voltage - V
5
Figure 18
Figure 19
14
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SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
4 3.8 VOD - Differential Output Voltage - V 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -40 -15 0 85 10 35 60 TA - Free-Air Temperature - C 0 0.6 DE at VCC D at VCC VCC = 5 V RL = 54 70 60 I O - Driver Output Current - mA
DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE
TA = 25C DE at VCC D at VCC RL = 54
50 40
30 20
10
1.2 1.8 2.4 3 3.6 4.2 VCC - Supply Voltage - V
4.8
5.4
Figure 20
DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL OUTPUT CURRENT
5 4.5 VO - Differential Output Voltage - V 4 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 IOD - Differential Output Current - mA 60 Load Line TA = 25C DE at VCC D at VCC VCC = 5 V
Figure 21
30 Load Line
120
Figure 22
15
SN65HVD05, SN65HVD06, SN65HVD07 SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B - MAY 2002 - REVISED MAY 2003
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APPLICATION INFORMATION
RT
RT
Device HVD05 HVD06 HVD07
Number of Devices on Bus 64 256 256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible.
Figure 23. Typical Application Circuit
16
MECHANICAL DATA
MPDI001A - JANUARY 1995 - REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
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