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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B - NOVEMBER 2000 - REVISED FEBRUARY 2002
D Three Differential Transceivers in One
Package
SN65LBC170DB (marked as BL170) SN75LBC170DB (marked as BL170) (TOP VIEW)
D Signaling Rates Up to 30 Mbps D Low Power and High Speed D Designed for TIA/EIA-485, TIA/EIA-422, ISO D D D D D D D D
8482, and ANSI X3.277 (HVD SCSI Fast-20) Applications Common-Mode Bus Voltage Range -7 V to 12 V ESD Protection on Bus Terminals Exceeds 12 kV Driver Output Current up to 60 mA Thermal Shutdown Protection Driver Positive and Negative Current Limiting Power-Up, Power-Down Glitch-Free Operation Pin-Compatible With the SN75ALS170 Available in Shrink Small-Outline Package
1D 1DIR NC GND 2D 2DIR 3D 3DIR
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1B 1A NC VCC 2B 2A 3B 3A
SN65LBC170DW (marked as 65LBC170) SN75LBC170DW (marked as 75LBC170) (TOP VIEW)
description
The SN65LBC170 and SN75LBC170 are monolithic integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. Potential applications include serial or parallel data transmission, cabled peripheral buses with twin axial, ribbon, or twisted-pair cabling. These devices are suitable for FAST-20 SCSI and can transmit or receive data pulses as short as 25 ns, with skew less than 3 ns. These devices combine three 3-state differential line drivers and three differential input line receivers, all of which operate from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form three differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These ports feature a wide common-mode voltage range making the device suitable for party-line applications over long cable runs.
1D 1DIR NC GND NC 2D 2DIR NC 3D 3DIR
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
1B 1A NC NC VCC 2B 2A 3B 3A NC
NC - No internal connection
logic diagram
1DIR 1A 1B 1D
2DIR 2A 2B 2D
3DIR 3A 3B 3D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B - NOVEMBER 2000 - REVISED FEBRUARY 2002
description (continued)
The driver's active-high enable and the receiver's active-low enable are tied together internally and provide a direction input for each driver/receiver pair. The SN75LBC170 is characterized for operation over the temperature range of 0C to 70C. The SN65LBC170 is characterized for operation over the temperature range of -40C to 85C.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C Add R suffix for taped and reel PLASTIC SHRINK SMALL-OUTLINE (JEDEC MO-150) SN75LBC170DB SN65LBC170DB PLASTIC SMALL-OUTLINE (JEDEC MS-013) SN75LBC170DW SN65LBC170DW
Function Tables
EACH DRIVER INPUT D H L OPEN X X ENABLE DIR H H H L OPEN OUTPUTS B A H L L Z X L H H Z X EACH RECEIVER DIFFERENTIAL INPUT ENABLE OUTPUT (VA-VB) DIR D L H VID 0.2 V - 0.2 V < VID < 0.2 V VID - 0.2 V X OPEN L L H L ? L Z H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
DIR INPUTS A INPUT VCC 16 V Input 16 V 8V 100 k 4 k 100 k 18 k 1 k Input 16 V Input 100 k 4 k 4 k VCC 16 V 18 k 4 k B INPUT VCC
D I/O VCC VCC VCC
A AND B OUTPUT
4 k 18 k 40 100 k 8V 4 k
16 V Output 16 V
2
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B - NOVEMBER 2000 - REVISED FEBRUARY 2002
absolute maximum ratings
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Voltage range at any bus I/O terminal (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 15 V Voltage input range, A and B, (transient pulse through 100 , see Figure 12) . . . . . . . . . . . . . . -30 V to 30 V Voltage range at any D or DIR terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Electrostatic discharge: Human body model (A, B, GND) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV Charged-device model (all pins) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 3. Tested in accordance with JEDEC Standard 22, Test Method C101. POWER DISSIPATION RATING TABLE PACKAGE DB TA 25C POWER RATING 995 mW DERATING FACTOR} ABOVE TA = 25C 8.0 mW/C TA = 70C POWER RATING 635 mW TA = 85C POWER RATING 515 mW
DW 1480 mW 11.8 mW/C 950 mW 770 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC Voltage at any bus I/O terminal High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID Output current Operating free air temperature, TA free-air temperature A, B D, D DIR A with respect to B Driver Receiver SN75LBC170 SN65LBC170 4.75 -7 2 0 -12 -60 -8 0 -40 NOM 5 MAX 5.25 12 VCC 0.8 12 60 8 70 85 mA C UNIT V V V V
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SLLS459B - NOVEMBER 2000 - REVISED FEBRUARY 2002
DRIVER SECTION electrical characteristics over recommended operating conditions
PARAMETER VIK VO |VOD(SS)| VOD VOC(SS) VOC(SS) II IO Input clamp voltage D and DIR Open-circuit output voltage (single-ended) St d t t diff ti l t t lt Steady-state differential output voltage magnitude Change in differential output voltage magnitude, | VOD(H) | - |VOD(L) | Steady-state common-mode output voltage Change in steady-state common-mode output voltage (VOC(H) - VOC(L)) Input current TEST CONDITIONS II = 18 mA A or B, No load No load RL = 54 , See Figure 1 With common-mode loading, See Figure 2 MIN -1.5 0 3.8 1 1 -0.2 RL = 54 , CL = 50 pF See Figure 1 2 -0.2 D, DIR -100 2.4 4.3 1.6 1.6 TYP -0.7 VCC VCC 2.4 2.4 0.2 2.8 0.2 100 V A V MAX UNIT V V
V
Output current with power off VCC = 0 V, VO = -7 V to 12 V -700 900 A IOS Short-circuit output current VO = -7 V to 12 V, See Figure 7 -250 250 mA ICC Supply current (driver enabled) D at 0 V or VCC, DIR at VCC, No load 14 20 mA All typical values are at VCC = 5 V and TA = 25C. The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0C. System designers should take the possibly lower output signal into account in determining the maximum signal-transmission distance.
switching characteristics over recommended operating conditions
PARAMETER tPLH tPHL tr tf tsk(p) tsk(o) tsk(pp) tPLH tPHL tr tf tsk(p) tsk(o) tsk(pp) tPZH tPHZ Differential output propagation delay, low-to high Differential output propagation delay, high-to-low Differential output rise time Differential output fall time Pulse skew | (tPLH - tPHL) | Output skew Part-to-part skew Differential output propagation delay, low-to high Differential output propagation delay, high-to-low Differential output rise time Differential output fall time Pulse skew | (tPLH - tPHL) | Output skew Part-to-part skew Output enable time to high level Output disable time from high level See Figure 5 15 18 See Figure 4 4, (HVD SCSI double-terminated load) 3 3 3 3 7 7.5 7.5 7.5 RL = 54 , CL = 50 pF, See Figure 3 F, TEST CONDITIONS MIN 4 4 3 3 TYP 8.5 8.5 7.5 7.5 MAX 12 11 11 11 2 1.5 2 10 10 12 12 3 1.5 2.5 25 25 ns ns ns UNIT
tPZL Output enable time to low level 10 25 See Figure 6 ns tPLZ Output disable time from low level 17 25 Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits.
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RECEIVER SECTION electrical characteristics over recommended operating conditions
PARAMETER VIT+ VIT- Vhys VOH VOL II RI Positive-going differential input voltage threshold Negative-going differential input voltage threshold Hysteresis voltage (VIT+ - VIT-) High-level output voltage Low-level output voltage Line input current Input resistance VID = 200 mV, IOH = -8 mA, See Figure 8 VID = -200 mV, IOL = -8 mA, See Figure 8 Other input = 0 V A, B A, B, D, and DIR open VI = 12 V VI = -7 V 4 0 -0.7 12 16 See Figure 8 -0.2 40 4.7 0.2 VCC 0.4 0.9 mA k mA TEST CONDITIONS MIN TYP MAX 0.2 V mV V UNIT
ICC Supply current (receiver enabled) All typical values are at VCC = 5 V and TA = 25C.
switching characteristics over recommended operating conditions
PARAMETER tPLH tPHL tr tf tPZH tPHZ tPZL tPLZ tsk(p) tsk(o) Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output Receiver output rise time Receiver output fall time Receiver output enable time to high level Receiver output disable time from high level Receiver output enable time to low level Receiver output enable time to high level Pulse skew (| tPLH - tPHL |) Output skew See Figure 11 See Figure 10 29 See Figure 9 TEST CONDITIONS MIN 7 7 1.3 1.3 26 TYP MAX 16 16 3 3 40 40 40 40 2 1.5 ns ns ns UNIT ns ns ns ns
ns tsk(pp) Part-to-part skew 3 ns Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B - NOVEMBER 2000 - REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
IO II 0 V or 3 V IO VO VOD 50 pF 27 VOC 27
VO
Includes probe and jig capacitance
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Input VOD 60 VTEST = -7 V to 12 V VTEST
375
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V RL = 54 Signal Generator{ 50 Input CL = 50 pF} VOD tPLH Output 90% 90% 10% tr 10% tf tPHL VOD(H) 0V VOD(L) 1.5 V 1.5 V 0V
PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Includes probe and jig capacitance
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
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PARAMETER MEASUREMENT INFORMATION
5V S1 375 165 60 pF 3V Input 1.5 V 1.5 V 0V 75 Signal Generator{ 50 165 5V 375 60 pF tPLH VOD Output 90% 90% 10% tr 10% tf tPHL VOD(H) 0V VOD(L)
0V
S2 0V PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Includes probe and jig capacitance
Figure 4. Driver Switching Test Circuit and Waveforms, HVD SCSI-Loading (double terminated)
A S1 0 V or 3 V{ B Input Generator} CL = 50 pF Output RL = 110 tPZH Output 50 2.3 V tPHZ Input 3V 1.5 V 1.5 V 0V 0.5 V VOH 0V
3 V if testing A output, 0 V if testing B output PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 w Includes probe and jig capacitance
Figure 5. Driver Enable/Disable Test, High Output
5V A 0 V or 3 V{ B Input Generator CL = 50 pF S1 Output tPZL Output 2.3 V VOL 50 0.5 V tPLZ 5V RL = 110 Input 3V 1.5 V 1.5 V 0V
0 V if testing A output, 3 V if testing B output PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 w Includes probe and jig capacitance
Figure 6. Driver Enable/Disable Test, Low Output
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PARAMETER MEASUREMENT INFORMATION
IOS VO Voltage Source VID VO IO
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver DC Parameters
Generator{
50 A D VID B CL = 15 pF} VO IO
Input B Input A tPLH Output 1.5 V 10% tr 90% 90% 1.5 V
3V 0V tPHL VOH 1.5 V 10% V OL tf
Generator{
50
PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Includes probe and jig capacitance
Figure 9. Receiver Switching Test Circuit and Waveforms
VCC D B DIR Generator{ 1 k CL = 15 pF} tPZH 1.5 V tPHZ VOH VOH -0.5 V GND 3V DIR 1.5 V 1.5 V 0V
1.5 V
A
50
PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Includes probe and jig capacitance
Figure 10. Receiver Enable/Disable Test, High Output
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PARAMETER MEASUREMENT INFORMATION
A D B DIR 1 k CL = 15 pF} VCC DIR 3V 1.5 V 1.5 V 0V tPZL 1.5 V Generator{ 50 tPLZ VCC VOL + 0.5 V VOL
-1.5 V
PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Includes probe and jig capacitance
Figure 11. Receiver Enable/Disable Test, Low Output
100 Pulse Generator, 15-s Duration, 1% Duty Cycle
VTEST 0V 15 s 1.5 ms -VTEST
Figure 12. Test Circuit and Waveform, Transient Over Voltage Test
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TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT
4 VOD - Differential Output Voltage - V 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 IO - Output Current - mA 100 VCC = 4.75 V VCC = 5.25 V VCC = 5 V 2.5
DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
VOD - Differential Output Voltage - V
2 VCC = 5 V 1.5
VCC = 5.25 V
VCC = 4.75 V 1
0.5
0 -60
-40
-20 0 20 40 60 TA - Free-Air Temperature - C
80
100
Figure 13
DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE
12 11 Driver Propagation Delay - ns 160 I CC - Supply Current - mA 10 SCSI Load 9 8 7 6 5 4 -40 RS-485 Load 165
Figure 14
SUPPLY CURRENT vs SIGNALING RATE
All 3 Channels Driving RL = 54 , CL = 50 pF (Each Channel), Pseudorandom NRZ Data
155
150
145
140
-20 0 20 40 60 TA - Free-Air Temperature - C
80
135 0.1
1 10 Signaling Rate - Mbps
100
Figure 15
Figure 16
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TYPICAL CHARACTERISTICS
BUS INPUT CURRENT vs BUS INPUT VOLTAGE
800 600 VCC = 0 V Bus Input Current - A 400 200 0 -200 -400 -600 -10 VCC = 5 V t pd - Receiver Propagation Delay Time - ns 12 11 10 9 8 7 6 5 4 -40 tPHL tPLH
RECEIVER PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE
-5
0
5
10
15
-20
Bus Input Voltage - V
0 20 40 60 TA - Free-Air TemperatureC
80
Figure 17
Figure 18
SN65LBC170 (as Driver) Signal Generator
15 Meters, Cat. 5 Twisted-Pair Cable 100
SN65LBC170 (as Receiver)
15 pF
Figure 19. Circuit Diagram for Signaling Characteristics
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
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TYPICAL CHARACTERISTICS
Driver Input (5 V/div)
Driver Output (2 V/div)
Receiver Input (2 V/div) 25 ns Receiver Output (5 V/div)
Figure 20. Signal Waveforms at 30 Mbps
Driver Input (5 V/div)
Driver Output (2 V/div)
Receiver Input (2 V/div) 12.5 ns Receiver Output (5 V/div)
Figure 21. Eye Patterns, Pseudorandom Data at 30 Mbps
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TYPICAL CHARACTERISTICS
Driver Input (5 V/div)
Driver Output (2 V/div)
Receiver Input (2 V/div) 25 ns Receiver Output (5 V/div)
Figure 22. Signal Waveforms at 50 Mbps
Driver Input (5 V/div)
Driver Output (2 V/div)
Receiver Input (2 V/div) 12.5 ns Receiver Output (5 V/div)
Figure 23. Eye Patterns, Pseudorandom Data at 50 Mbps
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
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MECHANICAL DATA
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,15 NOM 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /D 09/00
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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SN65LBC170, SN75LBC170 TRIPLE DIFFERENTIAL TRANSCEIVERS
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MECHANICAL DATA
DW (R-PDSO-G**)
16 PINS SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000 / D 01/00
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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