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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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SCES644 - MARCH 2006
FEATURES
* * * * * * * Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages Low Static-Power Consumption: ICC = 0.9 A Max Low Dynamic-Power Consumption: Cpd = 4.3 pF Typ at 3.3 V Low Input Capacitance: Ci = 1.5 pF Typ Low Noise - Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V) Wide Operating VCC Range of 0.8 V to 3.6 V
DCT PACKAGE (TOP VIEW)
* * * * * *
*
Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 4.3 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) ESD Protection Exceeds 5000 V With Human-Body Model
*
DCU PACKAGE (TOP VIEW)
YEP OR YZP PACKAGE (BOTTOM VIEW)
CLK D Q GND
1 2 3 4
8 7 6 5
VCC PRE CLR Q
CLK D Q GND
1 2 3 4
8 7 6 5
VCC PRE CLR Q
GND Q D CLK
45 36 27 18
Q CLR PRE VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). ORDERING INFORMATION
TA PACKAGE (1) NanoStarTM - WCSP (DSBGA) 0.23-mm Large Bump - YEP -40C to 85C NanoFreeTM - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SSOP - DCT VSSOP - DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 3000 Reel of 3000 ORDERABLE PART NUMBER SN74AUP1G74YEPR _ _ _UP_ SN74AUP1G74YZPR SN74AUP1G74DCTR SN74AUP1G74DCUR U74_ _ _ UP_ TOP-SIDE MARKING (2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2006, Texas Instruments Incorporated
SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Static-Power Consumption (A) 100% 80% 60% 40% 20% 0%
Dynamic-Power Consumption (pF) 100% 80%
3.3-V Logic
60% 40% 20%
AUP
3.3-V LVC Logic
0%
AUP
Single, dual, and triple gates
Figure 1. AUP - The Lowest-Power Family
Switching Characteristics at 25 MHz 3.5 3 Voltage - V 2.5 2 1.5 1 0.5 0 -0.5 Input Output
0
5
10
15
20 25 30 Time - ns
35
40
45
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low. NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE
INPUTS PRE L X H H H CLR H L H H H CLK X X L D X X H L X OUTPUTS Q H L H L Q0 Q L H L H Q0
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
CLR CLK 6 1 C
C C
3 TG
Q
C
C C
C
5
Q
D
2
TG
TG
TG
C PRE 7
C
C
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO VO IIK IOK IO Supply voltage range Input voltage range (2) Voltage range applied to any output in the high-impedance or power-off state (2) Output voltage range in the high or low state (2) Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND DCT package JA Tstg (1) (2) (3) Package thermal impedance (3) Storage temperature range DCU package YEP/YZP package -65 VI < 0 VO < 0 -0.5 -0.5 -0.5 -0.5 MAX 4.6 4.6 4.6 VCC + 0.5 -50 -50 20 50 220 227 102 150 C C/W UNIT V V V V mA mA mA mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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Recommended Operating Conditions (1)
MIN VCC Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 0.8 V VIL Low-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VI VO Input voltage Output voltage VCC = 0.8 V VCC = 1.1 V IOH High-level output current VCC = 1.4 V VCC = 1.65 VCC = 2.3 V VCC = 3 V VCC = 0.8 V VCC = 1.1 V IOL Low-level output current VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3 V t/v TA (1) Input transition rise or fall rate Operating free-air temperature VCC = 0.8 V to 3.6 V -40 0 0 0.8 VCC 0.65 x VCC 1.6 2 0 0.35 x VCC 0.7 0.9 3.6 VCC -20 -1.1 -1.7 -1.9 -3.1 -4 20 1.1 1.7 1.9 3.1 4 200 85 ns/V C mA A mA V V A V V MAX 3.6 UNIT V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -20 A IOH = -1.1 mA IOH = -1.7 mA VOH IOH = -1.9 mA IOH = -2.3 mA IOH = -3.1 mA IOH = -2.7 mA IOH = -4 mA IOL = 20 A IOL = 1.1 mA IOL = 1.7 mA VOL IOL = 1.9 mA IOL = 2.3 mA IOL = 3.1 mA IOL = 2.7 mA IOL = 4 mA II Ioff Ioff ICC ICC Ci Co (1) A or B input VI = GND to 3.6 V VI or VO = 0 V to 3.6 V VI or VO = 0 V to 3.6 V VI = GND or (VCC to 3.6 V) VI = VCC - 0.6 V (1) VI = VCC or GND VO = GND One input at VCC - 0.6 V, other input at VCC or GND IO = 0 IO = 0 VCC 0.8 V to 3.6 V 1.1 V 1.4 V 1.65 V 2.3 V 3V 0.8 V to 3.6 V 1.1 V 1.4 V 1.65 V 2.3 V 3V 0 V to 3.6 V 0V 0 V to 0.2 V 0.8 V to 3.6 V 3.3 V 0V 3.6 V 0V 1.5 1.5 3 TA = 25C MIN VCC - 0.1 0.75 x VCC 1.11 1.32 2.05 1.9 2.72 2.6 0.1 0.3 x VCC 0.31 0.31 0.31 0.44 0.31 0.44 0.1 0.2 0.2 0.5 40 TYP MAX TA = -40C TO 85C MIN VCC - 0.1 0.7 x VCC 1.03 1.3 1.97 1.85 2.67 2.55 0.1 0.3 x VCC 0.37 0.35 0.33 0.45 0.33 0.45 0.5 0.6 0.6 0.9 50 A A A A A pF pF V V MAX UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER VCC 0.8 V 1.2 V 0.1 V fclock Clock frequency 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V CLK high or low 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V tw Pulse duration 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR low 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V Data high 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V tsu Setup time before CLK Data low 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR inactive 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V th Hold time, data after CLK 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0 0 0 0 0 0 ns 1 0.5 0.5 0.5 0.5 0.5 1 1.2 1 1 1 1 ns 3 1.3 1 1 0.5 0.5 4.5 2 2 2 2 2 3.5 2 2 2 2 2 ns TA = 25C TYP 21 40 50 60 90 90 MHz TA = -40C TO 85C MIN MAX UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V 1.2 V 0.1 V fmax 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V CLK 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V tpd Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR Q or Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TA = 25C TYP 60 80 125 150 180 190 31 10 6 5 3 3 28 9 6 5 3 3 26 9 6 5 3 3 20 12 9 6 5 2 1.5 1.3 1 1 20 13 10 7 5 19 11 9 6 4 2.4 1.6 1.3 1.1 1 19 11.8 9 6 4.6 ns 20 12 9 6 4 2.7 1.9 1.4 1.1 1 20.4 12.4 9.5 6.2 4.7 60 90 120 160 180 MHz MAX TA = -40C TO 85C MIN MAX UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V 1.2 V 0.1 V fmax 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V CLK 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V tpd Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR Q or Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TA = 25C TYP 46 65 95 110 170 180 33 10 7 6 4 3 30 10 7 5 4 3 29 10 7 5 4 3 21 13 10 7 5 2 2 2 1.5 1.5 21.4 13.8 10.8 7.4 5.8 20 12 9 6 5 3 2.2 1.8 1.3 1.1 20.3 12.8 9.9 6.7 5.2 ns 22 13 10 6 5 3.4 2.4 1.9 1.5 1.2 21.8 13.5 10.4 7 5.3 50 55 60 130 160 MHz MAX TA = -40C TO 85C MIN MAX UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V 1.2 V 0.1 V fmax 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V CLK 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V tpd Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR Q or Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TA = 25C TYP 41 75 95 100 150 200 35 12 8 6 4 4 32 11 7 6 4 3 31 11 7 6 4 4 23 14 11 7 6 2 2 2 2 1.5 22.9 14.9 11.7 8.1 6.4 21.8 13.5 10.4 7.1 5.4 3.7 2.6 2.2 1.7 1.4 21.8 14 10.9 7.5 5.8 ns 23.1 14.1 10.7 7 5.4 4.1 2.9 2.4 1.9 1.6 23.2 14.6 11.3 7.6 5.9 50 55 60 130 160 MHz MAX TA = -40C TO 85C MIN MAX UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V 1.2 V 0.1 V fmax 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V CLK 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V tpd Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 0.8 V 1.2 V 0.1 V PRE or CLR Q or Q 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TA = 25C TYP 21 50 60 75 100 100 32 14 10 8 6 5 40 13 9 7 5 5 38 13 9 8 6 5 26 17 13 9 7 3 3 3 3 2.5 27 17.4 14 10 8 26 16 13 9 7 5.5 4.1 3.5 2.7 2.4 25.9 16.8 13.2 9.2 7.2 ns 27 17 13 9 7 5.9 4.4 3.6 3 2.6 27 17.2 13.4 9.2 7.2 40 50 70 90 90 MHz MAX TA = -40C TO 85C MIN MAX UNIT
Operating Characteristics
TA = 25C
PARAMETER TEST CONDITIONS VCC 0.8 V 1.2 V 0.1 V Cpd Power dissipation capacitance f = 10 MHz 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V TYP 5.5 5.5 5.5 5.5 5.5 5.5 pF UNIT
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output Under Test CL (see Note A) 1 M
LOAD CIRCUIT VCC = 1.2 V 0.1 V 5, 10, 15, 30 pF VCC/2 VCC VCC = 1.5 V 0.1 V 5, 10, 15, 30 pF VCC/2 VCC VCC = 1.8 V 0.15 V 5, 10, 15, 30 pF VCC/2 VCC VCC = 2.5 V 0.2 V 5, 10, 15, 30 pF VCC/2 VCC VCC = 3.3 V 0.3 V 5, 10, 15, 30 pF VCC/2 VCC
VCC = 0.8 V CL VM VI 5, 10, 15, 30 pF VCC/2 VCC
tw VCC Input VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tsu th VCC Timing Input VCC/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 VCC/2 0V
CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SCES644 - MARCH 2006
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PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times)
2 x VCC From Output Under Test CL (see Note A) 5 k S1 GND 5 k TEST tPLZ/tPZL tPHZ/tPZH S1 2 x VCC GND
LOAD CIRCUIT
VCC = 0.8 V CL VM VI V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V
VCC = 1.2 V 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V
VCC = 1.5 V 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V
VCC = 1.8 V 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V
VCC = 2.5 V 0.2 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V
VCC = 3.3 V 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V
Output Control tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + V tPHZ VCC/2 VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B)
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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17-Apr-2006
PACKAGING INFORMATION
Orderable Device SN74AUP1G74DCUR SN74AUP1G74DCURG4
(1)
Status (1) ACTIVE ACTIVE
Package Type US8 US8
Package Drawing DCU DCU
Pins Package Eco Plan (2) Qty 8 8 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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