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SN75LVDT1422
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SLLS653 - JUNE 2005
14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER
FEATURES
* * * * * * * * * 10 MHz to 100 MHz Shift Clock Support 175 Mbytes/sec In TX/RX Modes Reduces Cable Size, Cost, and System EMI Bidirectional Data Communication Total Power < 360 mW Typ at 100-MHz Worst Case Pattern Power-Down Mode: < 500 W Typ No External Components Required for PLL Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard ESD Rating > 5 kV (HBM) * * * * * * Integrated Termination Resistor Supports Spread Spectrum Clocking 64-Pin TQFP Package (PAG)
APPLICATIONS
Flash Memory Cards Plain Paper Copiers Printers
DESCRIPTION
The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock. The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLK IN. The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT). The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows: Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state. The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2005, Texas Instruments Incorporated
SN75LVDT1422
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SLLS653 - JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM
TX ENABLE TA+ TA0-TA6 R/F TB0-TB6 IN 7 IN Parallel In to Serial Out 7 OUT TB- OUT TA-
TB+
>CLK TCLK+ CLK IN PLL TCLK- RA+ RA0-RA6 7 Serial In to Parallel Out RB0-RB6 7 OUT IN 100 W RB- OUT IN 100 W RA-
RB+
CLK< RCLK+ CLK OUT PLL 100 W RCLK- RX ENABLE
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PAG PACKAGE (TOP VIEW)
RA2 RA1 RA0 CLK OUT RX GND RX ENABLE RX LVDS VCC RA+ RA- RCLK+ RCLK- RB+ RB- RX LVDS GND RX VCC RA3 RA4 RA5 RA6 RX GND RX VCC RB0 RB1 RB2 RB3 RX VCC RB4 RB5 RB6 RX GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RX PLL GND RX PLL VCC TX ENABLE TX LVDS VCC TB- TB+ TCLK- TCLK+ TA- TA+ TX LVDS GND TX PLL GND TX PLL VCC R/F TX GND TB6 TB5 TB4
CLK IN TX GND TA0 TA1 TA2 TX VCC TA3 TA4 TA5 TA6 TX VCC TB0 TB1 TB2 TB3 TX VCC
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TERMINAL FUNCTIONS
TERMINAL NAME CLK IN CLK OUT R/F RA+, RA- RA[0:6] RB+, RB- RB[0:6] RCLK+, RCLK- RX ENABLE RX GND RX LVDS GND RX LVDS VCC RX PLL GND RX PLL VCC RX VCC TA+, TA- TA[0:6] TB+, TB- TB[0:6] TCLK+, TCLK- TX ENABLE TX GND TX LVDS GND TX LVDS VCC TX PLL GND TX PLL VCC TX VCC NO. 17 61 37 57, 56 62, 63, 64, 2, 3, 4, 5 53, 52 8, 9, 10, 11, 13, 14, 15 55, 54 59 6, 16, 60 51 58 50 49 1, 7, 12 41, 42 19, 20, 21, 23, 24, 25, 26 45, 46 28, 29, 30, 31, 33,34, 35 43, 44 48 18, 36 40 47 39 38 22, 27, 32 Power Supply LVDS Output LVTTL Input LVDS Output LVTTL Input LVDS Output LVTTL Input Power Supply TYPE LVTTL Input CMOS/LVTTL Clock input Input clock triggering edge select. High: Rising edge Low: Falling edge LVDS Data inputs DESCRIPTION
LVTTL Output LVTTL Clock output LVTTL Input LVDS Input
LVTTL Output Single-ended data outputs LVDS Input LVDS Data inputs
LVTTL Output Single-ended data outputs LVDS Input LVTTL Input LVDS Clock inputs Receiver enable: When asserted (low input), the receiver outputs go to a known low state. Ground pins for RX TTL outputs Ground pin for RX LVDS inputs Power supply pin for RX LVDS inputs Ground pin for PLL RX circuitry Power supply pin for PLL RX circuitry Power supply pins for RX TTL outputs LVDS Data outputs Single-ended data inputs LVDS Data outputs Single-ended data inputs LVDS Clock outputs Transmitter enable: When asserted (low input), the driver outputs are high-impedance. Ground pins for TX TTL inputs Ground pin for TX LVDS outputs Power supply pin for TX LVDS outputs Ground pin for PLL TX circuitry Power supply pin for PLL TX circuitry Power supply pins for TX TTL inputs
ORDERING INFORMATION (1)
PRODUCT SN75LVDT1422 (1) PACKAGE TQFP (PAG) ORDERING NUMBER SN75LVDT1422
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
Supply voltage range, VCC
(2)
(1)
UNIT -0.5 V to 4 V -0.3 V to VCC + 0.3 V Human Body Model (3) (All pins) Electrostatic discharge Continuous power dissipation Storage temperature range (1) (2) (3) (4) (5) Machine Model
(4)(All
Voltage range at any terminal pins)
5 kV 200 V 500 V See Dissipation Rating Table -65C to 125C
Charged-Device Model (5) (All pins)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals In accordance with JEDEC Standard 22, Test Method A114-A. In accordance with JEDEC Standard 22, Test Method A115. In accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATINGS
PACKAGE TQFP (PAG) TQFP (PAG) (1) (2) (3) CIRCUIT BOARD MODEL Low-K (2) High-K (3) TA 25C 813 mW 1076 mW DERATING FACTOR (1) ABOVE TA = 25C 8.13 mW/C 10.76 mW/C TA = 70C POWER RATING 448 mW 592 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-2. In accordance with the High-K thermal metric definitions of EIA/JESD51-6.
THERMAL CHARACTERISTICS
PARAMETER RJB RJC PD Junction-to-board thermal resistance Junction-to-case thermal resistance Device power dissipation Typical Maximum VCC = 3.3 V, TA = 25C, f = 100 MHz VCC= 3.6 V, TA = 70C , f = 100 MHz TEST CONDITIONS VALUE 69.5 39.2 357.4 455.8 UNIT C/ W mW
RECOMMENDED OPERATING CONDITIONS
MIN VCC VIH VIL |VID| VIC TA VN fc Supply voltage High-level input voltage Low-level input voltage Magnitude of differential input voltage Common-mode input voltage range, receiver Operating free-air temperature Supply noise voltage, VCC Clock frequency 3 2 GND 0.1 |VID|/2 -10 -50 10 NOM 3.3 MAX 3.6 VCC 0.8 0.6 2.4 - |VID|/2 70 50 100 UNIT V V V V V C mV MHz
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- VOH VOL VIK II II(OFF) RT Ci (1) Positive-going differential input threshold voltage Negative-going differential input threshold voltage High-level output voltage Low-level output voltage Input clamp voltage Input current with integrated termination Power-off input current Termination resistance Input capacitance All typical values are at VCC = 3.3 V, TA = 25C. IOH = -4 mA IOL = 4 mA II = -18 mA VI = 0 V or 2.4 V, VCC = 3.6 V VCC = 0 V, VI = 2.4 V VID = 100 mV, VIC = 0.05 V to 2.4 V -1.5 -45 -10 90 110 2 -0.8 45 10 132 -100 2.4 0.4 TEST CONDITIONS MIN TYP (1) MAX 100 UNIT mV mV V V V A A pF
TRANSMITTER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER |VOD| |VOD| VOC(SS) VOC(SS) VOC(PP) IIH IIL VIK IOS IO(OFF) Ci (1) Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage Change in steady-state common-mode output voltage between logic states Peak-to-peak common-mode output voltage High-level input current Low-level input current Input clamp voltage Short-circuit output current Power-off output current Input capacitance All typical values are at VCC = 3.3 V, TA = 25C. VIH = 2 V VIL = 0.8 V II = -18 mA VO+ or VO- = 0 V VOD = 0 V VCC = 0 V, VO = 2.4 V -10 -1.5 -24 -12 -10 3 -0.8 24 12 10 TEST CONDITIONS RL = 100 MIN 250 -35 1.125 -35 30 TYP (1) 365 MAX 450 35 1.375 35 80 20 10 UNIT mV mV V mV mV A A V mA A pF
TRANSMITTER SUPPLY CURRENT
PARAMETER TEST CONDITIONS f = 10 MHz f = 25 MHz ICC Supply current (worst case) See Figure 1 and Figure 2 f = 40 MHz f = 65 MHz f = 85 MHz f = 100 MHz (1) All typical values are at VCC = 3.3 V, TA = 25C. MIN TYP (1) 17 19 22 29 34 38 MAX 23 27 30 34 45 49 mA UNIT
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RECEIVER SUPPLY CURRENT
PARAMETER TEST CONDITIONS f = 10 MHz f = 25 MHz ICC Supply current (worst case) See Figure 1 and Figure 3 f = 40 MHz f = 65 MHz f = 85 MHz f = 100 MHz (1) All typical values are at VCC = 3.3 V, TA = 25C. MIN TYP (1) 19 27 35 49 60 69 MAX 35 42 45 69 81 90 mA UNIT
SUPPLY CURRENT (1)
PARAMETER ICC(DIS) (1) (2) Disable supply current TEST CONDITIONS TX/RX ENABLEs = GND MIN TYP (2) 150 MAX 800 UNIT A
CMOS inputs have to connect to ground. All typical values are at VCC = 3.3 V, TA = 25C.
TRANSMITTER INPUT TIMING REQUIREMENTS
PARAMETER tt(CLK) tc(CLK) twH(CLK) twL(CLK) tt(EN) (1) (2) Transition time, CLK IN Input clock period, CLK IN Pulse duration, clock high, CLK IN Pulse duration, clock low, CLK IN Transition time, TX ENABLE, TAx/TBx See Figure 6 TEST CONDITIONS See Figure 5 MIN 1.0 10 0.35T 0.35T 1.5 T 0.5T 0.5T TYP (1) MAX 6.0 (2) 100 0.65T 0.65T 6.0 UNIT ns ns ns ns ns
All typical values are at VCC = 3.3 V, TA = 25C. Regulate clock frequency lower than 50 MHz. tt(CLK)max = 1/f x 50% x 60%.
TRANSMITTER SWITCHING CHARACTERISTICS
PARAMETER tr tf t0 t1 t2 t3 t4 t5 t6 t0 t1 t2 t3 t4 t5 t6 (1) LVDS Rise time LVDS Fall time Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 All typical values are at VCC = 3.3 V, TA = 25C. f = 25 MHz, See Figure 12 f = 10 MHz, See Figure 12 TEST CONDITIONS See Figure 4 See Figure 4 -0.8 13.49 27.77 42.06 56.34 70.63 84.91 -0.45 5.26 10.98 16.69 22.41 28.12 33.84 MIN TYP (1) 0.38 0.38 0 14.29 28.57 42.86 57.14 71.43 85.71 0 5.71 11.43 17.14 22.86 28.57 34.29 MAX 0.7 0.7 0.8 15.09 29.37 43.66 57.94 72.23 86.51 0.45 6.16 11.83 17.54 23.26 28.97 34.69 ns ns UNIT ns ns
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TRANSMITTER SWITCHING CHARACTERISTICS (continued)
PARAMETER t0 t1 t2 t3 t4 t5 t6 t0 t1 t2 t3 t4 t5 t6 t0 t1 t2 t3 t4 t5 t6 t0 t1 t2 t3 t4 t5 t6 tsu th Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 Output pulse position for bit 0 Output pulse position for bit 1 Output pulse position for bit 2 Output pulse position for bit 3 Output pulse position for bit 4 Output pulse position for bit 5 Output pulse position for bit 6 TAx/TBx Setup time to CLK IN TAx/TBx Hold time to CLK IN f = 85 MHz or 100 MHz, See Figure 6 f = 10 MHz tpd(TCC) CLK IN to TCLK Propagation delay time See Figure 7 and Figure 8 (2) f = 25 MHz f = 85 MHz f = 100 MHz tjit(C-C) TCLK Clock cycle-to-cycle jitter f = 85 MHz or 100 MHz f = 10 MHz f = 25 MHz SSCG Spread Spectrum Clock support; Modulation frequency with a linear profile (3) f = 40 MHz f = 65 MHz f = 85 MHz f = 100 MHz ten(TPLL) Phase lock loop enable time tdis(T) (2) (3) Transmitter disable time See Figure 9 See Figure 11 10 100 ms ns 100 2.5%/-5% kHz f = 100 MHz, See Figure 12 f = 85 MHz, See Figure 12 f = 65 MHz, See Figure 12 f = 40 MHz, See Figure 12 TEST CONDITIONS MIN -0.25 3.32 6.89 10.46 14.04 17.61 21.18 -0.20 2.00 4.20 6.39 8.59 10.79 12.99 -0.15 1.53 3.21 4.89 6.57 8.25 9.93 -0.2 1.23 2.66 4.09 5.51 6.94 8.37 1 0.25 1.0 1.38 1.60 1.63 2.98 3.21 3.78 3.95 50 ps ns TYP (1) 0 3.57 7.14 10.71 14.29 17.86 21.43 0 2.20 4.40 6.59 8.79 10.99 13.19 0 1.68 3.36 5.04 6.72 8.40 10.08 0 1.43 2.86 4.29 5.71 7.14 8.57 MAX 0.25 3.82 7.39 10.96 14.54 18.11 21.68 0.20 2.40 4.60 6.79 8.99 11.19 13.39 0.15 1.83 3.51 5.19 6.87 8.55 10.23 0.2 1.63 3.06 4.49 5.91 7.34 8.77 ns ns ns ns ns UNIT
Measure from CLK IN rising edge or falling edge to immediately crossing point of differential TCLK, 50% duty cycle input clock is assumed. Care must be taken to ensure tsu and th are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking spread spectrum clock applied to CLK IN pin, and reflects the result on TCLK+ and TCLK- pins.
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RECEIVER SWITCHING CHARACTERISTICS
PARAMETER tr tf t0 t1 t2 t3 t4 t5 t6 t0 t1 t2 t3 t4 t5 t6 tSK tc twH twL tsu th twH twL tsu th tpd(RCC) tdis(R) (1) (2) CMOS/LVTTL Rise time CMOS/LVTTL Fall time Input strobe position for bit 0 Input strobe position for bit 1 Input strobe position for bit 2 Input strobe position for bit 3 Input strobe position for bit 4 Input strobe position for bit 5 Input strobe position for bit 6 Input strobe position for bit 0 Input strobe position for bit 1 Input strobe position for bit 2 Input strobe position for bit 3 Input strobe position for bit 4 Input strobe position for bit 5 Input strobe position for bit 6 RA/RB Skew margin (2) CLK OUT Typical period range CLK OUT Pulse duration, clock high CLK OUT Pulse duration, clock low Rax/RBx Setup time to CLK OUT Rax/RBx Hold time to CLK OUT CLK OUT Pulse duration, clock high CLK OUT Pulse duration, clock low Rax/RBx Setup time to CLK OUT Rax/RBx Hold time to CLK OUT RCLK to CLK OUT Propagation delay time Receiver disable time At TA = 25C, VCC = 3.3 V, See Figure 14 See Figure 15 See Figure 16 f = 100 MHz, See Figure 13 f = 85 MHz, See Figure 13 f = 85 MHz, See Figure 18 f = 100 MHz, See Figure 18 f = 100 MHz, See Figure 17 f = 85 MHz, See Figure 17 CLK OUT RA or RB CLK OUT RA or RB TEST CONDITIONS See Figure 3 See Figure 3 0.45 2.13 3.81 5.49 7.17 8.85 10.53 0.40 1.83 3.26 4.09 6.12 7.54 8.97 300 200 10 4.0 4.0 3.0 3.5 3.0 3.0 2.0 2.5 6 9 10 1 ns ms s 5.0 5.0 ns T 5 5 100 6.5 6.5 ns MIN TYP (1) 1.2 2.0 1.2 2.0 0.84 2.52 4.20 5.88 7.56 9.24 10.92 0.71 2.14 3.57 5.00 6.43 7.85 9.28 MAX 2.5 3.5 2.5 3.5 1.23 2.91 4.59 6.27 7.95 9.63 11.31 1.02 2.45 3.88 5.31 6.74 8.16 9.59 ps ns ns ns UNIT ns ns
ten(RPLL) Receiver phase lock loop enable time
All typical values are at VCC = 3.3 V, TA = 25C. Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
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PARAMETER MEASUREMENT INFORMATION
t CLK IN / CLK OUT
ODD TA/TB ODD RA/RB EVEN TA/TB EVEN RA/RB
Figure 1. Worst Case Test Pattern
TA/TB + 5 pF TA/TB - 100 W
Figure 2. LVDS Output Load
CMOS/TTL output 8 pF
80 %
80 %
20 % tr tf
20 %
Figure 3. Receiver CMOS/LVTTL Output Load and Transition Times
80% 20% tr tf
80% Differential 20%
Figure 4. Transmitter LVDS Transition Times
3V 80% 20% CLK IN tt(CLK) tt(CLK) 80% 20% 0V
Figure 5. Transmitter Input Clock Transition Time
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PARAMETER MEASUREMENT INFORMATION (continued)
tc(CLK) CLK IN 2V 2V VCC/2 0.8 V twH(CLK) tsu twL(CLK) th 2V
TA/TB [0:6]
VCC/2
Setup
Hold
VCC/2
Figure 6. Transmitter Setup/Hold and High/Low Times (Falling Edge Strobe)
tpd(TCC) TCLK-
TCLK+
CLK IN
VCC/2
Figure 7. Transmitter Clock In to Clock Out Propagation Delay Time with R/F at VCC
tpd(TCC) TCLK-
TCLK+
CLK IN
VCC/2
Figure 8. Transmitter Clock In to Clock Out Propagation Delay Time with R/F at GND
TX ENABLE
VCC/2 ten(TPLL)
CLK IN
TCLK +
Figure 9. Transmitter Phase Lock Loop Enable Time
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INDETERMINATE
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PARAMETER MEASUREMENT INFORMATION (continued)
TCLK+ Previous Cycle Current Cycle TA+ TA1-1 TA0-1 TA6 TA5 TA4 TA3 TA2 TA1 TA0
TB+
TB1-1
TB0-1
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Figure 10. 14 Parallel TTL Data Inputs Mapped to LVDS Outputs
TX ENABLE
Vcc/2
CLK IN
TCLK+
Figure 11. Transmitter Disable Time
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tdis(T)
HIGH-MPEDANCE
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PARAMETER MEASUREMENT INFORMATION (continued)
tCLK TCLK+ Previous Cycle Current Cycle TA+ TA1-1 TA0-1 TA6 TA5 TA4 TA3 TA2 TA1 TA0
TB+
TB1-1 t0 t1 t2 t3 t4 t5 t6
TB0-1
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Figure 12. Transmitter LVDS Output Pulse Position Measurement
tc 2V CLK OUT twH twL tsu 2V Setup th 2V Hold 2V 2V 0.8 V
RA/RB 0:6
Figure 13. Receiver Setup/Hold and High/Low Times
CLK OUT tpd(RCC) RCLK- RCLK+
VCC/2
Figure 14. Receiver Clock In to Clock Out Propagation Delay Time
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PARAMETER MEASUREMENT INFORMATION (continued)
RX ENABLE VCC/2 ten(RPLL)
RCLK+
CLK OUT
Figure 15. Receiver Phase Lock Loop Enable Time
RX ENABLE
RCLK+ tdis(R) CLK OUT
14

INDETERMINATE
2V
vcc/2
LOW
Figure 16. Receiver Disable Time
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PARAMETER MEASUREMENT INFORMATION (continued)
tc RCLK+ Previous Cycle RA+ Current Cycle
RB+
t0min t0max t1min t1max t2min t2max t3min t3max t4min t4max t5min t5max t6min t6max
Figure 17. Receiver LVDS Input Strobe Position
Ideal Strobe Position RA+ or RB+
RA- or RB- tSK min tn max
min
(1) (2) (3) (4) (5) (6)
C - Setup and hold time (internal data sampling window) defined by tSTPOS(receiver input strobe position) min and max tn- Transmitter output pulse position (min and max) tSK = Cable skew (type, length) + source clock jitter (cycle to cycle) (5) + ISI (inter-symbol interference) (6) Cable skew - typically 10 ps to 40 ps per foot, media dependent Cycle-to-cycle jitter is less than 150 ps at 85 MHz ISI is dependent on interconnect length; may be zero
Figure 18. Receiver LVDS Input Skew Margin

C tSTPOS
~1.4 V
~1 V tSK max min tn+1 max
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TYPICAL CHARACTERISTICS
RECEIVER AVERAGE SUPPLY CURRENT vs FREQUENCY
80 I CC - Transmitter Average Supply Current - mA ICC - Receiver Average Supply Current - mA 70 60 50 40 PRBS Pattern 30 20 10 0 10 20 30 40 50 60 70 f - Frequency - MHz 80 90 100 VCC = 3.3 V, TA = 255C, VIC = 1.2 V, VID = 0.4 V 45 40 35 30 25 20 15 10 5 0 10 PRBS Pattern VCC = 3.3 V, TA = 255C, VIC = 1.2 V, VID = 0.4 V Worst Case Pattern
TRANSMITTER AVERAGE SUPPLY CURRENT vs FREQUENCY
Worst Case Pattern
20
30
40 50 60 70 f - Frequency - MHz
80
90
100
Figure 19. TRANSMITTER CLOCK CYCLE-TO-CYCLE JITTER vs FREQUENCY
450 Cycle-To-Cycle Jitter - % of Unit Internal 400 350 300 250 200 150 100 50 0 10 20 30 40 50 60 70 80 90 100 f - Frequency - MHz VCC = 3.3 V, TA = 255C, VIH = 3.3 V, VIL = 0 V
Figure 20. TRANSMITTER CLOCK CYCLE-TO-CYCLE JITTER vs FREQUENCY
0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 10 20 30 40 50 60 70 f - Frequency - MHz 80 90 100 VCC = 3.3 V, TA = 255C, VIH = 3.3 V, VIL = 0 V
Cycle-To-Cycle Jitter - ps
Figure 21.
Figure 22.
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APPLICATION INFORMATION Power Source Sequence
There is no power-on sequence restriction to VCC, LVDS VCC, and PLL VCC. In most applications, it is recommended to apply the same power source with the separate power planes and decoupling bypass capacitor groups. Use inductors to connect the different power planes.
Transmitter/Receiver Clock/Data Sequencing
There is no special requirement to the sequence of the input clock/data and enable signals. The input clock/data can be inserted after the enable signal is active. It is not necessary to cycle the enable signal when the clock/data is stopped and reapplied, like with the case of changing video modes within a graphics controller. When TX ENABLE pin is pulled low, the LVDS outputs of a SN75LVDT1422 transmitter are high-impedance, the PLL is shut down, and the transmitter is reset. When RX ENABLE is pulled low, the single-ended outputs of a SN75LVDT1422 receiver are at low status, the PLL is shut down, and the receiver is reset.
Spread Spectrum Clock Support
The transmitter of the SN75LVDT1422 accepts spread spectrum clocking signal type inputs. The outputs accurately track spread spectrum clock/data inputs with modulation frequencies of up to 100 kHz (max) with either center spread of 2.5% or down spread -5% deviations.
Receiver Failsafe Feature
The receiver input failsafe bias circuitry ensures a stable output with known status while the receiver inputs are left floating. When the receiver enable pin is active and a valid clock signal appears at the clock input, all of the data outputs are high if the data inputs are floating or idle. When the receiver enable pin is active and the clock input is floating, the last valid state is maintained on the data channels if the inputs are floating or idle. When the receiver enable pin is inactive, both data and clock outputs are kept low without considering the input status. In an application with an unused data input, it is recommended to leave it open. Receiver Failsafe Summary
RX ENABLE High High Low DATA CHANNEL STATUS Floating/Idle Floating/Idle Don't Care CLOCK CHANNEL STATUS Valid clock signal Floating/Idle Don't Care FAILSAFE RESULT DATA High Last state Low CLOCK Clock Low Low
Transmitter Input, Receiver Output Pins
The single-ended I/O pins and control input pins are compatible with LVCMOS and LVTTL levels only. These pins are not 5-V tolerant.
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PACKAGE OPTION ADDENDUM
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12-Jul-2005
PACKAGING INFORMATION
Orderable Device SN75LVDT1422PAG SN75LVDT1422PAGR
(1)
Status (1) ACTIVE ACTIVE
Package Type TQFP TQFP
Package Drawing PAG PAG
Pins Package Eco Plan (2) Qty 64 64 96 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR
1500 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996
PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17
PLASTIC QUAD FLATPACK
0,08 M
49
32
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 16
1,20 MAX
0,08 4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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