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TSP50C0x/1x Family Speech Synthesizer Design Manual
SPSS011C October 1998
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This manual describes the TSP50C0x/1x family of speech synthesizing devices. When necessary, the differences between the family members are shown in separate and consecutive sections. The object of this user's guide is to provide the information needed to implement a speech synthesizer design using a TSP50C0x/1x device.
How to Use This Manual
This document contains the following chapters: Chapter 1 Introduction to the TSP50C0x/1x Family This chapter describes the TSP50C0x/1x family features, D/A options, pin assignments and descriptions, and gives a brief introduction to linear predictive coding. TSP50C0x/1x Family Architecture This chapter describes the architecture of the TSP50C0x/1x family with a separate section for the LCD driver, reference voltage and contrast adjustment, and clock options of the TSP50C12. TSP50C0x/1x Electrical Specifications This chapter provides the electrical specifications for the TSP50C0x/1x family. TSP50C0x/1x Assembler This chapter contains a detailed description of the TSP50C0x/1x assembler. TSP50C0x/1x Instruction Set This chapter provides the instruction set for the TSP50C0x/1x. TSP50C0x/1x Applications This chapter describes various hints and useful advice for designing applications for the TSP50C0x/1x.
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Chapter 2
Chapter 3
Chapter 4
Chapter 5 Chapter 6
Running Title--Attribute Reference
Chapter 7
Customer Information This chapter describes customer information including development cycles structure, speech development/production sequence, mechanical information, and ordering information. Script Preparation and Speech Development Tools This appendix describes script preparation and development tools for the TSP50C0x/1x. TSP50C0x/1x Sample Synthesis Program This appendix contains a sample synthesis program that counts numbers from one to five. External ROM Initialization This appendix contains a sample program to initialize external ROM. DTMF Program This appendix contains a sample program that generates a dual-tone multifrequency (DTMF) signal. Sample Music Program This appendix contains a sample program that produces Mozart's Minuet in G. TSP50P11 (OTP) Version This appendix contains advance information for the TSP50P11, which is a one-time-programmable (OTP) version of the TSP50C11.
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
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Notational Conventions
Notational Conventions
This document uses the following conventions.
-
Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter's. Here is a sample program listing:
0349 0059 0350 005A 005B 6B 60 FF SPEAK2 LUAA ANEC StopWord -Get word -End phase?
-
In syntax descriptions the following notational conventions are used in this guide:
J J
A reserved keyword (an instruction, command or directive) is shown in bold capital letters and should be entered as shown. An optional field is indicated by brackets and italics and describes the type of information that should be entered: [label] User-supplied contents are indicated by angle brackets and italics and describe the type of information that should be entered: A required blank is indicated by a caret (^).
J J -
The following syntax example demonstrates the notational conventions used in this guide. []^ABAAC^...[] A lower case h at the end of a numeric value indicates that the value is hexadecimal (e.g., 01FAh, 032Bh, and 0FFh). All addresses in this manual are in hexadecimal format unless otherwise noted. All other are numbers are in decimal format unless otherwise noted.
J J J J J J J J J J
Abbreviations: '04: TSP50C04 '06: TSP50C06 '10: TSP50C10 '11: TSP50C11 '12: TSP50C12 '13: TSP50C13 '14: TSP50C14 '19: TSP50C19 LSB, MSB: Least significant and most significant bits LSbyte, MSbyte: Least significant and most significant bytes
Read This First
v
Notational Conventions
-
Port A refers to pins PA0 -- PA7 operating together. Port B refers to pins PB0 and PB1 operating together. Individual bits of a register are indicated with the register abbreviation followed by a decimal point and the bit number (e.g., bit 5 of the A register is A.5 or bit 2 of the mode register is MR.2). *X is the contents of the location pointed to by the address stored in X register. A' indicates the old contents of the A register
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Information About Cautions
Information About Cautions
This book may contain cautions.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
The information in a caution is provided for your protection. Please read each caution carefully.
If You Need Assistance. . .
If you want to. . . Request more information about Texas Instruments Speech Synthesizer products Do this. . . Write to: Texas Instruments Incorporated Market Communications Manager, MS 8206 P.O. Box 655303 Dallas, Texas 75265-5303 Call the TI Literature Response Center: (800) 477-8924 Send your comments to: Texas Instruments Incorporated Technical Publications Manager, MS 8345 P.O. Box 655303 Dallas, Texas 75265-5303
Order Texas Instruments documentation Report mistakes in this document or any other TI documentation
Trademarks
IBM, PC, PC/XT, PC/AT are trademarks of IBM Corporation. TI is a trademark of Texas Instrument Incorporated.
Read This First
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Contents
Contents
1 Introduction to the TSP50C0x/1x Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.1 TSP50C0x/1x Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.2 TSP50C04/06/13/14/19 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.3 TSP50C10/11 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.4 TSP50C12 Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3 D/A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3.1 Two-Pin Push Pull (Option 1) - Accurate to 10 Bits (+ 1/ 2 LSB) . . . . . . . . . . . . 1-7 1.3.2 Single-Pin Single Ended (Option 2) - Accurate to Only 9 Bits (+ 1 LSB) . . . . . 1-9 1.3.3 Single-Pin Double Ended (Option 3) - Accurate to 10 Bits (+ 1/ 2 LSB) . . . . . 1-11 1.4 TSP50C10/11 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5 TSP50C12 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.6 TSP50C04/06/13/14/19 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 1-18 1.7 Introduction to LPC (Linear Predictive Coding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.7.1 The Vocal Tract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.7.2 The LPC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.7.3 LPC Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 TSP50C0x/1x Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 TSP50C0x/1x Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.2 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.3 Program Counter Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.1.4 TSP50C10/11 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.5 TSP50C12 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.1.6 TSP50C04/06/13/14/19 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . 2-7 2.1.7 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.1.8 A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.1.9 X Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.1.10 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.1.11 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.1.12 Integer Mode Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.1.13 Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.1.14 Timer Prescale Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.1.15 Pitch Register and Pitch-Period Counter (PPC) . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
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2
Contents
2.2
2.3 2.4
2.5 2.6 3
2.1.16 Speech Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.17 Parallel-to-Serial Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.18 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.19 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Synthesizer Mode 0 - OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Synthesizer Mode 1 - LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Synthesizer Mode 2 - PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Synthesizer Mode 3 - PCM and LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Use of RAM by the Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Frame-Length Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.7 Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSP50C12 LCD Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 TSP50C12 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 TSP50C12 LCD Drive Type A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 TSP50C12 LCD Drive Type B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSP50C12 LCD Reference Voltage and Contrast Adjustment . . . . . . . . . . . . . . . . . . . TSP50C12 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-12 2-13 2-13 2-15 2-17 2-17 2-17 2-17 2-17 2-18 2-18 2-19 2-20 2-22 2-22 2-24 2-26 2-28 2-29
TSP50C0x/1x Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Absolute Maximum Ratings Over Operating Free-Air TemperatureRange . . . . . . . . . 3-2 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4 TSP50C10/11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5 TSP50C12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.6 TSP50C04/06/13/14/19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 TSP50C0x/1x Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Description of Notation Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Invoking the Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Command-Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 BYTE Unlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 DATA Unlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 XREF Unlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 TEXT Unlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 WARNING Unlist Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 Complete XREF Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 Object Module Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Listing File Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Page-Eject Disable Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 Error-to-Screen Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.11 Instruction Count Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.12 Binary-Code File-Disable Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-4 4-4 4-5 4-5 4-5 4-5 4-5 4-5 4-5 4-6 4-6 4-6 4-6
4
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4.4
4.5
4.6 4.7 4.8
4.9
Assembler Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.1 Assembly Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.2 Assembly Binary Object File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.3 Assembly Tagged Object File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.4 Assembly Listing File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Source-Statement Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.5.1 Label Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.5.2 Command Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.5.3 Operand Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.4 Comment Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.5 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.6 Decimal Integer Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.7 Binary Integer Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.5.8 Hexadecimal Integer Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.5.9 Character Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.5.10 Assembly-Time Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Character Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.8.1 Arithmetic Operators in Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.8.2 Parentheses In Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.9.1 AORG Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.9.2 BYTE Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.9.3 COPY Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.9.4 DATA Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.9.5 EQU Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.9.6 END Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.9.7 IDT Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.9.8 LIST Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.9.9 NARROW Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.9.10 OPTION Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4.9.11 PAGE Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.9.12 RBYTE Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.9.13 RDATA Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.9.14 RTEXT Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.9.15 TEXT Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.9.16 TITL Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.9.17 UNL Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 4.9.18 WIDE Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
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TSP50C0x/1x Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Instruction Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 TSP50C0x/1x Assembly Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
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TSP50C0x/1x Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Synthesizer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1 Speech Coding and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2 RAM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.3 ROM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.2 Program Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.2 Phrase Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.3 Speech Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.4 Level-1- Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.5 Frame-Update Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.3 Synthesis Program Walk-Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.4 Arithmetic Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 6.5 Operation of the Multiply Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 6.6 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 6.7 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 6.7.1 Slave-Mode Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6.7.2 Slave-Mode Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 6.8 TSP60C18/81 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.8.1 External ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.8.2 TSP60C18/81 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.8.3 TSP60C18 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.8.4 TSP60C81 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.8.5 TSP60C18/81 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6.8.6 TSP60C18/81 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 6.8.7 Initialization of the TSP60C18/81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54 6.8.8 Direct-Address Initialization of the TSP60C18/81 . . . . . . . . . . . . . . . . . . . . . . . 6-55 6.8.9 8-Bit Indirect-Address Initialization of the TSP60C18/81 . . . . . . . . . . . . . . . . . 6-56 6.8.10 16-Bit Indirect-Address Initialization of the TSP60C18/81 . . . . . . . . . . . . . . . . 6-57 6.8.11 Placing the TSP60C18/81 in a Low-Power Standby Condition . . . . . . . . . . . . 6-58 6.9 Use of the GET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 6.9.1 GET From Internal ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 6.9.2 GET From External ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62 6.9.3 GET From Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63 6.10 Generating Tones Using PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 6.10.1 Operation of the TASYN Instruction in PCM Mode . . . . . . . . . . . . . . . . . . . . . . 6-66 6.10.2 Timing Considerations in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 6.10.3 DTMF Program Walk-Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 6.11 TSP50C19 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 6.11.1 Memory Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 6.11.2 Data Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 6.11.3 Preparing the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76 6.11.4 Program Location in ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77 Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
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7.4 7.5
Summary of Speech Development /Production Sequence . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3.1 N016 300-Mil Plastic Dual-In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3.2 DW020 Plastic Small-Outline Wide-Body (SOWB) Package . . . . . . . . . . . . . . . 7-6 7.3.3 FN068 68-Lead Plastic Leaded Chip Carrier (PLCC) Package . . . . . . . . . . . . . 7-8 7.3.4 TSP50C12 (PLCC) Reflow Soldering Precautions . . . . . . . . . . . . . . . . . . . . . . 7-10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 New Product Release Forms (TSP50C0x/1x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.5.1 New Product Release Form for TSP50C04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.5.2 New Product Release Form for TSP50C06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.5.3 New Product Release Form for TSP50C10A . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.5.3 New Product Release Form for TSP50C11A . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7.5.4 New Product Release Form for TSP50C12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.5.5 New Product Release Form for TSP50C13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7.5.6 New Product Release Form for TSP50C14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 7.5.7 New Product Release Form for TSP50C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 A-1 A-2 A-2 A-2 A-3 A-4 A-5
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Script Preparation and Speech Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Script Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.1 Speaker Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.2 Speech Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.3 LPC Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1.4 Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Speech Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B C D E F
TSP50C0x/1x Sample Synthesis Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 External ROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 DTMF Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Sample Music Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 TSP50P11 (OTP Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1 F.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 F.2 Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-3 F.3 Special Functions Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-5 F.4 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . F-6 F.5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7 F.6 TSP50P11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-8 F.7 Protection Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-9 F.8 Programming Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-11 F.9 Differences Between the TSP50P11 and the TSP50C11 . . . . . . . . . . . . . . . . . . . . . . . . F-13 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1
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Illustrations
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13. 1-14 1-15 1-16 1-17 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 3-5 6-1 6-2 6-3 6-4 6-5
xiv
TSP50C10/11 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 TSP50C12 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 TSP50C04/06/13/14/19 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 D/A Output Waveform for Two-Pin Push Pull (Option 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Four-Transistor Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Operational Amplifier Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Power Amplifier Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 D/A Output Waveform for Single Ended (Option 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 One-Transistor Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 D/A Output Waveform for Single-Pin Double Ended (Option 3) . . . . . . . . . . . . . . . . . . . . . 1-12 Operational Amplifier Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 TSP50C10/11 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Power-Up Initialization Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 TSP50C12 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 TSP50C04/06/13/14/19 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 LPC-12 Vocal Tract Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 TSP50C0x/1x System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TSP50C10/11 RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 TSP50C12 RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 TSP50C04/06/13/14/19 RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 RAM Map During Speech Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 TSP50C12 LCD Driver Type A Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 TSP50C12 LCD Driver Type B Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 TSP50C12 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 RC OSC Option Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Initialization Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Write Timing Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Read Timing Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 External Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Typical Input Leakage Current on INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 D6 Frame Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Speech Parameter Unpacking and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 ACAAC in Extended-Sign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 ACAAC in Integer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 Slave-Mode Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
Illustrations
6-6 6-7 6-8 6-9 6-10 6-11 7-1 7-2 7-3 7-4 A-1 A-2 A-3 A-4 A-5 A-6 F-1 F-2 F-3 F-4 F-5 F-6
Slave-Mode Read-Then-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 TSP60C18/81-to-TSP50C0x/1x Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Register Connections for GET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 Parallel-to-Serial Operation for GET 5 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 Operation of TASYN in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 Format of Data in A Register Before TASYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 TSP50C04/06/10/11/13/14/19 16-Pin N Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 TSP50C04/06/10/11/13/14/19 20-Pin DW Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 TSP50C12 68-Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 SDS5000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 EVM50C1X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 SEB50C1X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 SEB60CXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 ADP50C12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 FAB50C1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 TSP50P11 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 Simplified Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-4 Normal Programming Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-9 Programming with Protection Set Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-10 Initialization and Write Sequence Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-11 Programming and Read Sequence Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-12
Contents
xv
Tables
Tables
1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 4-2 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10
xvi
TSP50C10/11 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 TSP50C10/11 I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 TSP50C12 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 TSP50C04/06/13/14/19 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Reserved ROM Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 TSP50C19 ROM Block Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Interrupt-1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Interrupt-2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 TSP50C12 Display RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 D/A Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Initialization Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Write Timing Requirements (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Read Timing Requirements (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 External Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 TSP50C10/11 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 TSP50C12 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted) . . . . . 3-10 Switches and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Summary of Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 TSP50C0x/1x Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 TSP50C0x/1x Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 D6 Parameter Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Hardware-Fixed RAM Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Other RAM Locations Used in Sample Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 FLAGS Bit Descriptions for Sample Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 ROM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 TXA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 TSP60C18/81 Pin Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 TSP60C18/81 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 TSP60C18/81 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Indirect Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52
Tables
6-11 6-12 6-13 6-14 6-15 6-16 F-1 F-2 F-3 F-4 F-5 F-6 F-7
Mode Register Control of GET Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 Relative Weights of DAC Magnitude Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69 TSP50C14 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 TSP50C19 ROM Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-75 ASM50C1x Assembler Relative Address and Block Selected . . . . . . . . . . . . . . . . . . . . . . 6-76 TSP50P11 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 Special Testing Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7 TSP50P11 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted) . . . . . . . . . . . . . . . F-8 Timing Characteristics for Initialization and Write Sequences . . . . . . . . . . . . . . . . . . . . . . F-11 Timing Characteristics for Initialization and Write Sequences . . . . . . . . . . . . . . . . . . . . . . F-12 TSP50P11 Excitation Function Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-13
Contents
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xviii
Running Title--Attribute Reference
Chapter 1
Introduction to the TSP50C0x/1x Family
The TSP50C0x/1x family of speech synthesizers offer cost-effective solutions for high-volume applications. Each incorporates a built in microprocessor that allows music as well as speech capability. Texas Instruments offers five sizes of internal ROM for up to three minutes of speech. In addition, the devices can be interfaced to external speech memory.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 1.7
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 D/A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 TSP50C10/11 Pin Assignments and Descriptions . . . . . . . . . . . . . . . 1-13 TSP50C12 Pin Assignments and Description . . . . . . . . . . . . . . . . . . . 1-16 TSP50C04/06/13/14/19 Pin Assignments and Descriptions . . . . . . . 1-18 Introduction to LPC (Linear Predictive Coding) . . . . . . . . . . . . . . . . . 1-19
Chapter Title--Attribute Reference
1-1
Introduction
1.1 Introduction
The TSP50C0x/1x uses a revolutionary architecture to combine an 8-bit microprocessor, a speech synthesizer, ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same ALU (Arithmetic Logic Unit) for the synthesizer and the microprocessor, thus reducing chip area and cost and enabling the microprocessor to do a multiply operation in 1.6 s. Linear Predictive Coding (LPC) is used to synthesize high-quality speech at a low data rate. The TSP50C0x/1x is highly flexible and programmable, making it suitable for a wide variety of applications. Its low system cost opens up new applications for solid-state speech. They include:
-
Talking Clocks Toys Telephone Answering Machines Home Monitors Navigation Aids Laboratory Instruments Personal Computers Inspection Controls Inventory Controls Machine Controls Warehouse Systems Warning Systems Appliances Mailboxes Equipment for the Handicapped Learning Aids Computer-Aided Instruction Magazine and Direct-Mail Advertisements Point-of-Sale Displays
1-2
Description
1.2 Description
The TSP50C0x/1x can be divided into several functional blocks (Figure 1-1, Figure 1-2, Figure 1-3). The ALU and RAM are shared by the speech synthesizer and the microcomputer. The TSP50C0x/1x implements an LPC-12 speech synthesis algorithm using a 12-pole lattice filter. The internal microprocessor fetches speech data from the internal or external ROM (TSP60C18 or TSP60C81), decodes the speech data, and sends the decoded data to the synthesizer. The microprocessor also interpolates (smooths) the speech data between fetches. The output of the synthesizer can be used to drive transistor or integrated-circuit amplifiers. Some digital low-pass filtering is provided inside the TSP50C0x/1x. The general-purpose microprocessor in the TSP50C0x/1x is also capable of a variety of logical, arithmetic, and control functions. It can often be used for the nonsynthesis tasks of the customer's application as well.
Figure 1-1. TSP50C10/11 Functional Block Diagram
Microcomputer Port A Port B
I/O
ALU
Speech Synthesizer
Microprocessor
RAM PWM Output DA2 DA1
ROM
Timing Oscillator
OSC1 OSC2
Introduction to the TSP50C0x/1x Family
1-3
Description
Figure 1-2. TSP50C12 Functional Block Diagram
8 Common LCD Outputs 24-Segment LCD Outputs
Microcomputer Port A Port B
LCD Driver
I/O ALU
Speech Synthesizer
Microprocessor RAM PWM Output ROM Timing Oscillator DA2 DA1
OSC1 OSC2
Figure 1-3. TSP50C04/06/13/14/19 Functional Block Diagram
Microcomputer Port A Port B
I/O
ALU
Speech Synthesizer
Microprocessor
RAM PWM Output DA2 DA1
ROM
Timing Oscillator
1-4
Description
1.2.1
TSP50C0x/1x Family Features
Key features of the entire TSP50C0x/1x family are in the following list.
1.2.2
Programmable LPC-12 Speech Synthesizer 8-Bit Microprocessor With 61 Instructions 4-V to 6-V CMOS Technology for Low Power Dissipation 3 D/A Configurations - Mask Selectable 10-kHz or 8-kHz Speech Sample Rate 10 Software Controllable I/O Lines (9 I/O Lines With Two-Pin D/A Output) Internal Timer External Interrupt Single-Cycle Multiply Instruction Executes Up to 600,000 Instructions Per Second Built-in Interface to TSP60C18 or TSP60C81 Speech ROM Built-In Slave Mode to Act as Microprocessor Peripheral
TSP50C04/06/13/14/19 Additional Features
Key features of the TSP50C04/06/13/14/19 are in the following list.
-
Direct Speaker Drive Capability (32 speaker) Internal Clock Generator That Requires No External Components Two-Pin D/A Output and 10 Pins of I/O Simultaneously Possible Two D/A Configurations - Mask Selectable Optional Doubling of the D/A Output 16 Twelve-Bit Words and 48 Bytes of RAM Bytes of ROM:
J J J J J
TSP50C04 has 4K bytes of ROM. TSP50C06 has 6K bytes of ROM. TSP50C13 has 8K bytes of ROM. TSP50C14 has 16K bytes of ROM. TSP50C19 has 32K bytes of paged ROM.
1.2.3
TSP50C10/11 Additional Features
Key features of the TSP50C10/11 are in the following list.
-
Three D/A Configurations - Mask Selectable 16 Twelve-Bit Words and 112 Bytes of RAM Bytes of ROM:
J J
TSP50C10 has 8K bytes of ROM. TSP50C11 has 16K bytes of ROM.
Introduction to the TSP50C0x/1x Family
1-5
Description
1.2.4
TSP50C12 Additional Features
-
Key features of the TSP50C12 are in the following list. Direct LCD Drive Capability for an 8 x 24 (192-Segment) Display 1/8 Duty Cycle and 1/ 4 Bias Drive With On-Chip Voltage Reference Internal Contrast Adjustment 24 Bytes of Display RAM Limited Direct Speaker Drive Capability RC Oscillator Option 16K bytes of ROM 16 Twelve-bit Words and 112 Bytes of RAM
1-6
D/A Options
1.3 D/A Options
The TSP50C0x/1x offers three D/A (digital-to-analog) output options to match different applications. The DAC (digital-to-analog converter) is a pulse-width-modulated type with 9 bits or 10 bits of resolution and a 16-kHz or 20-kHz sampling rate. Each option has a range of 480 to - 480 segments per sample period, with two options having a resolution of 1/ 2 LSB and the third having a resolution of 1 LSB. The DAC produces samples at twice the rate that data is received from the LPC filter. For example, if the LPC filter is running at approximately 10 kHz, then the DAC is running at approximately 20 kHz. The TSP50C04/06/13/14/19 can be used with a normal-sized pulse width or with the PW2 option. The PW2 option causes the processor to produce a double-sized pulse width. This results in a higher volume output, which includes some risk of clipping the output.
1.3.1
Two-Pin Push Pull (Option 1) - Accurate to 10 Bits (1/2 LSB)
Option 1 works well with a very efficient and inexpensive four-transistor amplifier. It requires two pins, so the I/O pin B1 is used for the second pin, meaning that only 9 bits of I/O are available. When the DAC is idle, or the output value is 0, both pins are high. When the output value is positive, DA1 goes low with a duty cycle proportional to the output value, while DA2 stays high. When the output value is negative, DA2 goes low with a duty cycle proportional to the output value, while DA1 stays high. This option offers a resolution of 10 bits. Figure 1-4 shows examples of D/A output waveforms with different output values. Each pulse of the DAC is divided into 480 segments per sample period. For a positive output value x = 0 to 480, DA1 goes low for x segments while DA2 stays high. When the DAC is idle or the output value is 0, both DA1 and DA2 are high. For a negative value x = 0 to - 480, DA2 goes low for |x| segments while DA1 stays high. This option can be used with the TSP50C04/06/13/14/19 to directly drive a 32 speaker in applications where the anti-aliasing low-pass filter is not needed. When the device is placed in a low power state, this DAC option places both of the DAC lines high.
Introduction to the TSP50C0x/1x Family
1-7
D/A Options
Figure 1-4. D/A Output Waveform for Two-Pin Push Pull (Option 1)
480 - x High DA2 Low High DA1 Low x 240 479 240 1
0
1
2
0
1
2
0
1
2
0
1
2
Output Value = x where x = 0 to 480 (as shown x = 360)
Output Value = 240
Output Value = 479
Output Value = 480
High DA2 Low 480 + x High DA1 Low |x| 0 1 2 0 240 1 2 0 1 2 0 1 2 240
Output Value = x where x = 0 to - 480 (as shown x = -120)
Output Value = -240
Output Value = 0
Output Value = - 480
Figure 1-5, Figure 1-6, and Figure 1-7 show examples of circuits that can be used with this option.
Figure 1-5. Four-Transistor Amplifier Circuit
5V + 10 F 470 DA1 32- Speaker 470
DA2
470
10 F
470
1-8
D/A Options
Figure 1-6. Operational Amplifier Interface Circuit
10 k VDD 47 k - 47 k DA2 1 F 10 k VDD/ 2 2.5 V p-p +
1 F DA1
Figure 1-7. Power Amplifier Interface Circuit
VDD
R1 DA1 R1 DA2 R2 TSP50C0x/1x C1 R2 C1
6 - LM386 3+ 4 2
5
10 F
8- Speaker
OUTPUT
2 k 2N2222
VSS NOTES: R1 56 k 10% R2 = 2 k 10% C1 = 0.022 F 20% R2 and C1 set low-pass cutoff frequency: fc = 1/(2R2 x C1) For values given above, fc = 3.6 kHz Gain control can be added by connecting a 10-F capacitor in series with a 10-k pot. This series combination is connected between pins 1 and 8. When this is done, R1 should be increased to approximately 250 k.
1.3.2
Single-Pin Single Ended (Option 2) - Accurate to Only 9 Bits (1 LSB)
Option 2 is designed for use with a single-transistor amplifier, offering the lowest-cost solution and still retaining all 10 I/O pins. It has only 9 bits of resolution and the amplifier power consumption is higher than the four-transistor amplifier mentioned above. It is available on the TSP50C10,
Introduction to the TSP50C0x/1x Family
1-9
D/A Options
TSP50C11, and the TSP50C04/06/13/14/19. The duty cycle of the output is proportional to the output value. If the output value is 0, the duty cycle is 50%. As the output value increases from 0 to the maximum, the duty cycle goes from being high 50% of the time up to 100% high. As the value goes from 0 to the most negative value, the duty cycle decreases from 50% high to 0%. Each pulse of the DAC is divided into 480 segments per sample period. As shown in Figure 1-8, when the output value is x = - 480 to 480, DA1 goes low for |x/ 2-240| segments. When the output value is 0, DA1 goes low for 240 segments. When the devices are placed in a low-power state, this option places the DAC output pin into a low state. Note: Using Option 2 causes a click at the beginning and end of speech and (under certain conditions) during synthesis. Software is available to minimize these clicks.
Figure 1-8. D/A Output Waveform for Single Ended (Option 2)
|x/2 + 240| 300 240
High DA1 Low
|x/2-240| 180 240
0
1
2
0
1
2
0
1
2
0
1
2
Output Value = x Output Value = 120 where x = 480 to- 480 (as shown x = 240)
241
Output Value = 480
Output Value = 0
High DA1 Low
239
479
120
1
360
0
1
2
0
1
2
0
1
2
0
1
2
Output Value = - 480
Output Value = 2
Output Value = 478
Output Value = - 240
Figure 1-9 shows an example of a circuit that can be used with option 2.
1-10
Running Title--Attribute Reference
Figure 1-9. One-Transistor Amplifier Circuit
VDD 8- Speaker
+ 50 F
0.1-F Disc
DA1
500 2N3904 VSS
1.3.3
Single-Pin Double Ended (Option 3) - Accurate to 10 Bits (1/2 LSB)
Option 3 is provided for use with operational and power amplifiers. It offers both 10 bits of resolution and 10 I/O pins and is available on the TSP50C10, TSP50C11, and the TSP50C12. When the output value is zero, the D/A output is biased at approximately 1/ 2 VDD. When the output value is positive, the D/A output pulses to about 1/ 2 VDD - 1 V. The duty cycle is proportional to the output value. When the output value is negative, the D/A output pulses to 1/ 2 VDD +1 V with a duty cycle proportional to the output value. Figure 1-10 shows examples of D/A output waveforms with different output values. Each pulse of the DAC is divided into 480 segments per sample period. For a positive output value x = 0 to 480, DA1 goes low to 1/ 2 VDD -1 V for x segments. When the DAC is idle, or the output value is 0, DA1 goes to 1/ 2 VDD. For a negative value x = 0 to - 480, DA1 goes high to 1/ 2 VDD + 1 V for |x| segments. When the devices are placed in a low-power state, this option places the DAC output pin into a low state.
Chapter Title--Attribute Reference
1-11
D/A Options
Figure 1-10. D/A Output Waveform for Single-Pin Double Ended (Option 3)
1/2 VDD +1 V DA1 1/2 VDD 1/2 VDD -1 V 0 1
480 - x 240 1
x
240
479
2
0
1
2
0
1
2
0
1
2
Output Value = x where x = 0 to 480 (as shown x = 360)
|x|
Output Value = 240
Output Value = 479
Output Value = 480
240
1/2 VDD +1 V DA1 1/2 VDD 1/2 VDD -1 V 0 1 2 0 1 2 0 1 2 0 1 2
480 + x 240
Output Value = x where x = 0 to - 480 (as shown x = -360)
Output Value = -240
Output Value = 0
Output Value = - 480
Figure 1-11 shows an example of a circuit that can be used with option 3.
Figure 1-11. Operational Amplifier Interface Circuit
100 k VDD 47 k - + 2 V p-p
1 F DA1
10 k V DD 2
1-12
TSP50C10/11 Pin Assignments and Descriptions
1.4 TSP50C10/11 Pin Assignments and Descriptions
Figure 1-12 shows the pin assignments for the TSP50C10/11. Table 1-1 provides terminal functional descriptions. Table 1-2 shows the possible TSP50C10/11 I/O configurations. Figure 1-13 illustrates the recommended power-up initialization circuit. Note that the pullup resistor is required to be lower than 50 k. Figure 1-14 illustrates the recommended clock circuit. Refer to subsection 2.1.18, Input/Output Ports, for more information on I/O configuration.
Figure 1-12. TSP50C10/11 Pin Assignments
N PACKAGE (TOP VIEW) DW PACKAGE (TOP VIEW)
PA3 PA2 PA1 PA0 VSS INIT OSC1 OSC2
1 2 3 4 5 6 7 8
PA4 PA5 14 PA6 13 PA7 12 VDD
16 15 11 10
DA1 PB1/DA2 9 PB0
PA3 PA2 PA1 PA0 NC NC VSS INIT OSC1 OSC2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PA4 PA5 PA6 PA7 NC NC VDD DA1 PB1/ DA2 PB0
NC - No internal connection
Introduction to the TSP50C0x/1x Family
1-13
TSP50C10/11 Pin Assignments and Descriptions
Table 1-1. TSP50C10/11 Terminal Functions
Terminal Name DA1 DA2 INIT Terminal Number N Package 11 10 6 DW Package 13 12 8 I/O O O I Description D/A output. Three mask options are available. D/A output. Three mask options are available. Initialize input. When INIT goes low, the clock stops, the TSP50C10/11 goes into low-power mode, the program counter is set to zero, and the contents of the RAM are retained. An INIT pulse of 1 s is sufficient to reset the processor. Clock input. Crystal or ceramic resonator between OSC1 and OSC2, or signal into OSC1. 9.6 MHz for 10-kHz sampling rate or 7.68 MHz for 8-kHz sampling rate. Clock return 8-bit bidirectional I/O port
OSC1
7
9
I
OSC2 PA0 - PA7
8 1- 4, 13 -16 9 -10 12 5
10 1- 4, 17 -20 11, 12 14 7
- I/O
PB0 - PB1 VDD VSS
I/O - -
2-bit bidirectional I/O port 5-V supply voltage Ground terminal
The operation of this pin depends on the D/A option selected.
1-14
TSP50C10/11 Pin Assignments and Descriptions
Table 1-2. TSP50C10/11 I/O Configurations
16-Pin D Package Pin Number 4 3 2 1 16 15 14 13 9 10
With external interrupt
20-Pin DW Package Pin Number 4 3 2 1 20 19 18 17 11 12
Master 1-Pin D/A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 1-Pin D/A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1/ IRQ 2-Pin D/A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 DA2
Slave 1-Pin D/A D0 D1 D2 D3 D4 D5 D6 BUSY/D7 CE R/W
Master 1-Pin 1 Pi D/A TSP60C18 C0 C1 C2 C3 PA4 PA5 PA6 SRCK STR R/W
Figure 1-13. Power-Up Initialization Circuit
VDD Optional Reset Switch
47 k INIT 0.1 F
Figure 1-14. Oscillator Circuit
TSP50C0x/1x CLK 1 M
INIT
OSC1
OSC2
30 pF 9.6 -MHz or 7.68 -MHz Crystal or Ceramic Resonator
30 pF
Introduction to the TSP50C0x/1x Family
1-15
TSP50C12 Pin Assignments and Descriptions
1.5 TSP50C12 Pin Assignments and Descriptions
Figure 1-15 shows the pin assignments for the TSP50C12. Table 1-3 provides terminal functional descriptions. The I/O configurations in Table 1-2 also applies to the TSP50C12, but the pin numbers given are different. Figure 1-13 illustrates the recommended power-up initialization circuit, and Figure 1-14 illustrates the recommended clock circuit. The TSP50C12 is available only in die form. Refer to subsection 2.1.18, Input/Output Ports, for more information on I/O configuration.
Figure 1-15. TSP50C12 Pin Assignments
PLCC PACKAGE (TOP VIEW)
NC NC VSS DA1 VDD PB1/DA2 PBO OSC2 OSC1 VSS NC C8 C7 C6 C5 C4 C3 C2 C1 S1 S2 S3 S4 S5 VDD NC NC
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 87 6 5432
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
INIT S24 S23 S22 S21 NC NC NC NC S20 S19 S18 S17 S16 VC1 VLCD VC2 VX2 S15 S14 S13 S12 VSS NC
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC - No internal connection
1-16
NC S6 S7 S8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 S9 S10 S11 NC NC
TSP50C12 Pin Assignments and Descriptions
Table 1-3. TSP50C12 Terminal Functions
Terminal Name DA2 DA1 PB1 PB0 INIT Terminal Number 4 6 4 3 67 I/O O O I/O I/O I Description D/A output. D/A options 1 and 3 are available. D/A output. D/A options 1 and 3 are available. Bidirectional I/O pin Bidirectional I/O pin Initialize input. When INIT goes low, the clock stops, the TSP50C12 goes into low-power mode, the program counter is set to zero, and the contents of the RAM are retained. An INIT pulse of 1 s is sufficient to reset the processor. Clock input. Crystal or ceramic resonator between OSC1 and OSC2, or signal into OSC1. 9.6 MHz for 10-kHz sampling rate or 7.68 MHz for 8-kHz sampling rate. Clock return 8-bit bidirectional I/O port LCD common lines (rows) LCD segment lines (columns)
OSC1
1
I
OSC2 PA0 - PA7 C1 - C8 SEG1 - SEG24
2 31- 38 11 - 18 19 - 23, 28 - 30, 39 - 41, 46 - 49, 54 - 58, 63 - 66 53 51 50 52 5, 24 7, 45, 68
- I/O O O
VC1 VC2 VX2 VLCD VDD VSS
- - - - - - LCD supply voltage 5-V supply voltage Ground terminals Voltage doubler capacitor connection
The operation of this pin depends on the D/A option selected. Ceramic resonator requires two pins. RC oscillator requires one pin for timing and one buffered clock output for trim monitoring.
Introduction to the TSP50C0x/1x Family
1-17
TSP50C04/06/13/14/19 Pin Assignments and Descriptions
1.6 TSP50C04/06/13/14/19 Pin Assignments and Descriptions
Figure 1-16 shows the pin assignments for the TSP50C04/06/13/14/19. Table 1-4 provides terminal functional descriptions. The I/O configurations in Table 1-2 apply to the TSP50C04/06/13/14/19 with the exception of the pin numbering and the DA2 pin assignment. Figure 1-13 illustrates the recommended power-up initialization circuit for the TSP50C04/06/13/14/19. OSC1 should be tied to either VSS or VDD. Refer to subsection 2.1.18, Input/Output Ports, for more information on I/O configurations.
Figure 1-16. TSP50C04/06/13/14/19 Pin Assignments
N PACKAGE (TOP VIEW) DW PACKAGE (TOP VIEW)
PA3 PA2 PA1 PA0 VSS INIT OSC1 PB0
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PA4 PA5 PA6 PA7 DA2 DA1 VDD PB1
PA3 PA2 PA1 PA0 NC NC VSS INIT OSC1 PB0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PA4 PA5 PA6 PA7 NC NC DA2 DA1 VDD PB1
NC - No internal connection
Table 1-4. TSP50C04/06/13/14/19 Terminal Functions
Terminal Name DA1 DA2 INIT Terminal Number N Package 11 12 6 DW Package 13 14 8 I/O O O I Description D/A output. D/A options 1 and 2 are available. D/A output. D/A options 1 and 2 are available. Initialize input. When INIT goes low, the clock stops, the TSP50C04/06/13/14/19 goes into low-power mode, the program counter is set to zero, and the contents of the RAM are retained. An INIT pulse of 1 s is sufficient to reset the processor. OSC1 should be tied to VSS or VDD. 8-bit bidirectional I/O port 2-bit bidirectional I/O port 5-V supply voltage
OSC1 PA0 - PA7 PB0 - PB1 VDD
7 , 1- 4, 13 -16 8-9 10
9 , 1- 4, 17 -20 10 - 11 12
I I/O I/O -
5 7 - Ground terminal VSS Both DA1 and DA2 are driven with the same levels when option 2 is selected. 1-18
Introduction to LPC (Linear Predictive Coding)
1.7 Introduction to LPC (Linear Predictive Coding)
The LPC-12 system uses a mathematical model of the human vocal tract to enable efficient digital storage and re-creation of realistic speech. To understand LPC, it is essential to understand how the vocal tract works. This introduction, therefore, begins with a short description of the vocal tract, after which the LPC model and data compression techniques are addressed. A short discussion of the techniques and pitfalls of collecting, analyzing, and editing speech for LPC synthesis is included in Appendix A, Script Preparation and Speech Development Tools. For more information, contact your TI Field Sales Representative or Regional Technology Center.
1.7.1
The Vocal Tract
Speech is the result of the interaction of three elements in the vocal-tract air from the lungs, a restriction that converts the air flow to sound, and the vocal cavities that are positioned to resonate properly. Air from the lungs is expelled through the vocal tract when the muscles of the chest and diaphragm are compressed. Pressure is used as a volume control with higher pressure for louder speech. As air flows through the vocal tract, it makes little sound if there is no restriction. The vocal cords are one type of restriction. They can be tightened across the vocal tract to stop the flow of air. Pressure builds up behind them and forces them open. This happens over and over, generating a series of pulses. The tension on the vocal cords can be varied to change the frequency of the pulses. Many speech sounds, such as the |A| sound, are produced by this type of restriction, which is called voiced speech. A different type of restriction in the mouth causes a hissing sound called white noise. The |S| sound is a good example. White noise occurs when the tongue and some part of the mouth are in close contact or when the lips are pursed. This restriction causes high flow velocities then creating turbulence that, in turn, produces white noise, which is called unvoiced speech. The pulses from the vocal cords and the noise from the turbulence have fairly broad, flat spectral characteristics. In other words, they are noise, not speech. The shape of the oral cavity changes noise into recognizable speech. The positions of the tongue, the lips, and the jaws change the resonance of the vocal tract, shaping the raw noise of restricted airflow into understandable sounds.
Introduction to the TSP50C0x/1x Family
1-19
Introduction to LPC (Linear Predictive Coding)
1.7.2
The LPC Model
The LPC model incorporates elements analogous to each of the elements of the vocal tract previously described. It has an excitation function generator that models both types of restriction, a gain-multiplication stage to model the possible levels of pressure from the lungs, and a digital filter to model the resonance in the oral and nasal cavities. Figure 1-17 shows the LPC model in schematic form. The excitation function generator accepts coded pitch information as an input and can generate a series of pulses similar to vocal cord pulses. It can also generate white noise. The waveform is then multiplied by an energy factor that corresponds to the pressure from the lungs. Finally, the signal is passed through a digital filter that models the shape of the oral cavity. In the TSP50C0x/1x, this filter has twelve poles, so the synthesis is referred to as LPC-12.
Figure 1-17. LPC-12 Vocal Tract Model
Pitch
Periodic
LPC-12 Digital Filter
DAC
White Noise Energy K1 - K12 Filter Coefficients
1.7.3
LPC Data Compression
The data compression for LPC-12 takes advantage of other characteristics of speech. Speech changes fairly slowly, and the oral and nasal cavities tend to fall into certain areas of resonance more than others. The speech is analyzed in frames generally from 10 ms to 25 ms long. The inputs to the model are calculated as an average for the entire frame. The synthesizer smooths or interpolates the data during the frame so that there is not an abrupt transition at the end of each frame. Often speech changes even more slowly than the frame.
1-20
Introduction to LPC (Linear Predictive Coding)
The Texas Instruments LPC model allows for a repeat frame in which the only values changed are the pitch and the energy. The filter coefficients are kept constant from the previous frame. To take advantage of the recurrent nature of resonance in the oral cavity, all the coefficients are encoded with anywhere from seven to three bits for each coefficient. The coding table is designed so that more coverage is given to the coefficient values that occur frequently.
Introduction to the TSP50C0x/1x Family
1-21
1-22
Running Title--Attribute Reference
Chapter 2
TSP50C0x/1x Family Architecture
This chapter describes the architecture and function of the TSP50C0x/1x family of speech synthesizers including RAM, ROM, registers, flags, and the DAC.
Topic
2.1 2.2 2.3 2.4 2.5 2.6
Page
TSP50C0x/1x Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Speech Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 TSP50C12 LCD Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 2-22 TSP50C12 LCD Reference Voltage and Contrast Adjustment . . . . 2-28 TSP50C12 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Chapter Title--Attribute Reference
2-1
TSP50C0x/1x Functional Description
2.1 TSP50C0x/1x Functional Description
As shown in the block diagram in Figure 2-1, the major components of the TSP50C0x/1x are a speech synthesizer, an 8-bit microprocessor, an internal 4K-byte ROM (TSP50C04), 6K-byte ROM (TSP50C06), 8K-byte ROM (TSP50C10/13),16K-byte ROM (TSP50C11/12/14), 32K-byte ROM (TSP50C19), and input/output ports. When synthesis is disabled, instructions are fetched by the microprocessor from the ROM 600,000 (10-kHz speech sample rate) or 480,000 (8-kHz speech sample rate) times per second. These instructions control the actions of the TSP50C0x/1x. By placing different instruction patterns in the ROM, the TSP50C0x/1x can be programmed to accomplish a wide variety of tasks. To generate speech, the processor accesses speech data from either the internal ROM or an external source such as a TSP60C18 speech ROM, an EPROM, or a host processor. Once the data has been read, the processor must unpack and decode the individual speech parameters and store the results in a dedicated section of the RAM. The synthesizer shares access to the RAM and addresses the individual parameter locations as needed when generating speech. The instruction execution rate slows to 280,000 or 224,000 instruction cycles per second during synthesis because the synthesizer also shares the ALU (Arithmetic Logic Unit) and ROM data paths with the microprocessor. The microprocessor must perform interpolation during each frame as well as fetch the data for the next frame. The I/O consists of one 8-bit bidirectional port (port A) and one 2-bit bidirectional port (port B). Each bit can be software configured for input or output and for push pull or open drain (no pullup driver). There are two specialized I/O modes for specific functions. Slave mode configures the TSP50C0x/1x to act as a peripheral to a host microprocessor. External ROM mode allows the TSP50C0x/1x to interface with a TSP60C18 or TSP60C81 speech ROM.
2-2
TSP50C0x/1x Functional Description
Figure 2-1. TSP50C0x/1x System Block Diagram
Integer Flag ALU Integer Flag' Status Flag Status Flag'
A B Timer Prescale Mode P/S Buffer Random Number X
A' B'
P/ S Register X'
16 x 12-Bit RAM 48 x 8-Bit RAM (TSP50C04/06/13/14/19) 112 x 8-Bit RAM (TSP50C10/11/12) 24 x 8-Bit Display RAM (TSP50C12 Only) 14-Bit Data Bus 1 x 4-Bit Contrast Adjust (TSP50C12 Only) 4 x 8-Bit I/O 4 x 2-Bit I/O Program Counter Port A Port B
3-Level Stack Speech Address
4096-Byte ROM (TSP50C04) 6144-Byte ROM (TSP50C06) 8192-Byte ROM (TSP50C10/13) 16384-Byte ROM (TSP50C11/12/14) 32768-Byte ROM (TSP50C19) 384-Byte Excitation ROM
Pitch Counter
Pitch D/A Register Excitation Synthesizer Stack D/A Output
TSP50C0x/1x Family Architecture
2-3
TSP50C0x/1x Functional Description
2.1.1
Read-Only Memory (ROM)
The TSP50C04 has a 4K-byte ROM. The TSP50C06 has a 6K-byte ROM. The TSP50C10 and the TSP50C13 each have an 8K-byte ROM. The TSP50C11/12/14 each have a 16K-byte ROM. The TSP50C19 has a 32K-byte ROM. ROM can be used for program instructions and speech data as required by the application. Certain locations in the ROM, described in Table 2-1, are reserved for specific purposes.
Table 2-1. Reserved ROM Locations
Address 0000h 0010h - 001Fh 0FE0h - 0FFFh 17E0h - 17FFh 1FE0h-1FFFh 3FE0h - 3FFFh 5FFDh - 5FFFh 7FFDh - 7FFFh Function Execution start location after INIT rising edge Interrupt start locations (see Section 2.3, Interrupts) Texas Instruments test code (TSP50C04 only) Texas Instruments test code (TSP50C06 only) Texas Instruments test code (TSP50C10/13 only) Texas Instruments test code (TSP50C11/12/14/19 only) Texas Instruments test code (TSP50C19 only) Texas Instruments test code (TSP50C19 only)
The TSP50C19 has a paged ROM as shown in Table 2-2. The lower 8K-bytes of ROM are available at any time. The upper 8K-byte block of address space is switched between three separate ROM blocks depending upon the value loaded to the B2 and B3 output ports. See Section 6.11, TSP50C19 Programming, for more information.
Table 2-2. TSP50C19 ROM Block Addressing
ROM Address 0000h - 1FFFh 2000h - 3FFFh 2000h-3FFFh 2000h - 3FFFh Port B2 X O O 1 Port B3 X 0 1 0 ROM Block Block 1 Block 2 Block 3 Block 4 Listing Address Accessed 0000h - 1FFFh 2000h - 3FFFh 4000h - 5FFFh 6000h - 7FFFh
2-4
TSP50C0x/1x Functional Description
The ROM may be accessed in the following four ways:
2.1.2
The program counter is used to address processor instructions. The GET instruction can be used to transfer 1 to 8 bits from the ROM to the A register. The GET counter is initialized by the LUAPS instruction. The SAR (speech address register) points to the ROM location to be used. The LUAA instruction can be used to transfer a byte from the ROM into the A register. The value in the A register when LUAA is executed points to the ROM address to be used. The LUAB instruction can be used to transfer a byte from the ROM into the B register. The value in the A register when LUAB is executed points to the ROM address to be used.
Program Counter
The TSP50C0x/1x has a 14-bit program counter that points to the next instruction to be executed. After the instruction is executed, the program counter is normally incremented to point to the next instruction. The following instructions modify the program counter: BR BRA CALL branch branch to address in A register call subroutine
RETN return from subroutine RETI SBR return from interrupt short branch
2.1.3
Program Counter Stack
The program counter stack has three levels. When a subroutine is called or an interrupt occurs, the contents of the program counter are pushed onto the stack. When an RETN or an RETI is executed, the contents of the top stack location are popped into the program counter.
TSP50C0x/1x Family Architecture
2-5
TSP50C0x/1x Functional Description
2.1.4
TSP50C10/11 Random-Access Memory (RAM)
The TSP50C10/11 RAM has 128 locations (Figure 2-2). The first 16 RAM locations are used by the synthesizer and are 12 bits long. The remaining 112 locations are 8 bits long. When not synthesizing speech, the entire RAM may be used for algorithm data storage. The I/O control registers are also mapped into the RAM address space from 080h to 087h. For more information, see subsection 2.1.18, Input/Output Ports.
Figure 2-2. TSP50C10/11 RAM Map
11 10 9 8 7 6 5 4 3 2 1 0 Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
07Eh 07Fh 080h (I/O) 081h
086h 087h
2.1.5
TSP50C12 Random-Access Memory (RAM)
The TSP50C12 RAM has 16 12-bit synthesizer RAM locations and 112 8-bit general purpose RAM locations (Figure 2-3). The RAM also has 24 8-bit display RAM locations and one 4-bit contrast adjustment register. The I/O ports are mapped into RAM address space from 0F0h-0F7h.
2-6
TSP50C0x/1x Functional Description
Figure 2-3. TSP50C12 RAM Map
11 10 9 8 7 6 5 4 3 2 1 0 Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
07Eh 07Fh 080h (Display) 081h
096h 097h 098h (Contrast)
0F0h (I/O) 0F1h
0F6h 0F7h
2.1.6
TSP50C04/06/13/14/19 Random-Access Memory (RAM)
The TSP50C04/06/13/14/19 RAM has the same basic RAM layout as the TSP50C10/11 (see Figure 2-4) with one exception. The general-purpose RAM location range is from 010h to 03Fh.
TSP50C0x/1x Family Architecture
2-7
TSP50C0x/1x Functional Description
Figure 2-4. TSP50C04/06/13/14/19 RAM Map
11 10 9 8 7 6 5 4 3 2 1 0 Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
03Fh
080h (I/O) 081h
086h 087h
2.1.7
Arithmetic Logic Unit (ALU)
The ALU performs arithmetic and logic functions for the microprocessor and the synthesizer. The ALU is 14 bits in length, providing the resolution needed for speech synthesis. When 8-bit data are transferred to the ALU, they are right justified. The input to the upper 6 bits may be either zeros (integer mode) or equal to the MSB of the 8-bit data (extended-sign mode) depending on the arithmetic mode selected using the EXTSG and INTGR instructions. See the description of each instruction for specific information. All bit and comparison operations are performed on the lower 8 bits. The ALU is capable of doing an 8-bit by 14-bit multiply with a 14-bit scaled result in a single instruction cycle.
2.1.8
A Register
The A register, or accumulator, is the primary 14-bit register and is used for arithmetic and logical operations. Its contents can be transferred to RAM and
2-8
TSP50C0x/1x Functional Description
most of the other registers. It can be loaded from RAM, ROM, and most other registers. The contents are saved in a dedicated storage register during level-1 interrupts and restored by the RETI instruction.
A Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2.1.9
X Register
The X register is an 8-bit register used as a RAM index register. All RAM access instructions (except for the direct-addressing instructions TAMD, TMAD, and TMXD) use the X register to point to a specific RAM location. The X register can also be used as a general-purpose counter. The contents of the X register are saved during level-1 interrupts and restored by the RETI instruction. If a RAM location with an illegal address is loaded via the X register, the EVM board with the TSE chip accepts it, but a problem appears on the TSP chip.
X Register 7 6 5 4 3 2 1 0
2.1.10 B Register
The 14-bit B register is used for temporary storage. It is helpful for storing a RAM address because it can be exchanged with the X register using the XBX instruction. The B register can be added to, subtracted from, or exchanged with the A register, making it useful for data storage after calculations. The contents of the B register are saved during level-1 interrupts and restored by the RETI instruction.
B Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2.1.11 Status Flag
The status flag is set or cleared by various instructions depending on the result of the instruction. Refer to the individual description of instructions in Chapter 5, TSP50C0x/1x Instruction Set, to determine the effect an instruction
TSP50C0x/1x Family Architecture
2-9
TSP50C0x/1x Functional Description
has on the value of the status flag. The BR, SBR, and CALL instructions are conditional, modifying the program counter only when the status flag is set. The value of the status flag is unknown at power up. Therefore, if the first instruction after power up is one of these conditional instructions, the execution of the instruction cannot be predicted. The value of the status flag is saved during interrupts and restored by the RETI instruction.
Status Flag 0
2.1.12 Integer Mode Flag
The integer mode flag is set by the INTGR instruction and cleared by the EXTSG instruction. When the integer mode flag is set (integer mode), the upper bits of data less than 14 bits in length are zero filled when being transferred to, added to, or subtracted from the A and B registers. When the integer mode flag is cleared (extended-sign mode), the upper bits of data less than 14 bits in length are sign extended when being transferred to, added to, or subtracted from the A and B registers. The value of the integer mode flag is saved during interrupts and restored by the RETI instruction.
Integer Mode Flag 0
2.1.13 Timer Register
The 8-bit timer register is used for generating interrupts and for counting events. It decrements once each time the timer prescale register goes from 000h to 0FFh. It can be loaded using the TATM instruction and examined with the TTMA instruction. When it decrements from 000h to 0FFh, a level-2 interrupt request is generated. If interrupts are enabled and no interrupt is being processed already, an immediate interrupt occurs; if not, the interrupt request remains pending until interrupts are enabled. The timer continues to count whether or not it is reloaded.
Timer Register 7 6 5 4 3 2 1 0
Note: The timer does not decrement before it is initialized. However, on the EVM, the timer decrements after a STOP/RUN.
2-10
TSP50C0x/1x Functional Description
2.1.14 Timer Prescale Register
The 8-bit timer prescale register is a programmable divider between the processor clock and the timer register. When it decrements from 000h to 0FFh, the timer register is also decremented. The timer prescale register is then reloaded with the value in its preset latch, and the counting starts again. The timer prescale register clock comes from an internal clock. The internal clock runs at 1/16 the clock frequency of the chip; thus, the timer prescale register decrements once every instruction cycle when not in LPC mode. The TAPSC instruction loads the timer prescale register's preset latch. If the timer has not yet been initialized with the TATM instruction, the TAPSC instruction also loads the timer prescale register.
Timer Prescale Register 7 6 5 4 3 2 1 0
2.1.15 Pitch Register and Pitch-Period Counter (PPC)
Although the 14-bit pitch register and pitch-period counter are part of the synthesizer, they affect the microprocessor in many ways. The pitch-period counter controls the timing of the periodic impulse (excitation function) that simulates the vocal cords. On the TSP50C0x/1x, the pitch-period counter is also used to synchronize the interpolation of all speech parameters during each frame. This pitch-synchronous interpolation helps to minimize the inevitable noise from interpolation by making it occur at the lowest energy part of the speech and by making it a harmonic of the speech fundamental frequency. The pitch register is used when LPC speech is being synthesized. The following discussion presumes that the LPC mode is active. The pitch register is loaded with the TASYN instruction. When speech starts, the pitch-period counter is cleared. The pitch-period counter is decremented by 020h for each speech sample, with speech samples occurring at an 8-kHz or 10-kHz rate. When the pitch-period counter decrements past zero, the pitch register is added to it. When the pitch-period counter goes below 200h or when a pitch register is added to it with a result less than 200h, a level-1 interrupt occurs. This interrupt can be used to synchronize the interpolation algorithm. The excitation function is put out when the pitch-period counter is between 140h and 000h. For further information, see Chapter 6, TSP50C0x/1x Applications, of this book.
TSP50C0x/1x Family Architecture
2-11
TSP50C0x/1x Functional Description
Pitch Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0
For voiced or unvoiced frames, the LSB and the MSB of the A register must be zero when data is transferred from the A register to the pitch register with the TASYN instruction (see the following illustration). If this is not done, problems with the TSP50C0x/1x chip may occur that are not apparent when using the TSE50C1x chip.
13 12 11 10 9 0 8 A Register 765 4 3 2 1 0 0
13 12 11 10 9 0
Pitch Register 8765
4
3
2
1
0 0
For voiced frames, the pitch register must be loaded with a value no higher than 1FFEh. In addition, there are three recommendations for the minimum pitch-register value for voiced frames. First, it is required that the pitch-register value be 042h or higher. If this is not done, problems with the TSP chip may occur that are not apparent with the TSE chip. Second, it is strongly recommended that the pitch register be loaded with a value of 142h or higher. This permits the complete excitation pulse to be used in the LPC synthesis. Third, for best results with the recommended software algorithms, a pitch-register value of 202h or higher is recommended. The requirement that the pitch register value be less than or equal to 1FFEh and the recommendation of a value greater than or equal to 142h result in a pitch range of 39 Hz to 994 Hz when operating with a 10-kHz sample rate. For unvoiced frames, the pitch register is required to be loaded with a value between 042h and 3FEh. If this is not done, problems with the TSP chip may occur that are not apparent with the TSE chip.
2.1.16 Speech Address Register
The speech address register (SAR) is a 14-bit register that is used to point to data in internal ROM. The LUAPS instruction transfers the value in A to the speech address register and loads the parallel-to-serial register (see subsection 2.1.17, Parallel-to-Serial Register) with the internal ROM value pointed to by the SAR. The GET instruction can then be used to bring 1 to 8
2-12
TSP50C0x/1x Functional Description
bits at a time from the parallel-to-serial register into the accumulator. Whenever the parallel-to-serial register becomes empty, it is loaded with the internal ROM value pointed to by the SAR, and the SAR is incremented.
Speech Address Register 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2.1.17 Parallel-to-Serial Register
The 8-bit parallel-to-serial register is used primarily to unpack speech data. It can be loaded with 8 bits of data from internal ROM pointed to by the speech address register, internal RAM pointed to by the X register, or external TSP60C18 or TSP60C81 speech ROM pointed to by the SAR in the TSP60C18 or TSP60C81. The LUAPS instruction is used to initialize the parallel-to-serial register and zero its bit counter. GET instructions can then be used to transfer one to eight bits from the parallel-to-serial register to the accumulator. When the parallel-to-serial register is empty, it is automatically reloaded. When the GET is from RAM, however, the X register is not automatically incremented. The EXTROM and RAMROM bits in the mode register control the source for the parallel-to-serial register. See the speech address register description in subsection 2.1.16, Speech Address Register, for more information.
Parallel-to-Serial Register 7 6 5 4 3 2 1 0
2.1.18 Input/Output Ports
Ten bidirectional lines - 8-bit port A and 2-bit port B - are available for interfacing with external devices. Each bit is individually programmable as an input or an output under the control of the respective data-direction register. In addition, each output bit can be individually programmed using the pullup-enable register for one of two output modes - push pull or open drain (no pullup). Each input bit can be programmed by the same register for resistive pullup or high impedance. The four registers associated with each of the two I/O ports are memory mapped. Only two bits of the B port are available on the outside of the chip. The states of the upper six bits of port B are undetermined on the TSP50C04/06/10/11/12/13/14. The states of the upper four bits of port B are undetermined on the TSP50C19. Transfers from any of the I/O port registers to the A register leave the bits in the A register
TSP50C0x/1x Family Architecture
2-13
TSP50C0x/1x Functional Description
corresponding to the upper six bits of port B on the TSP50C04/06/10/11/12/13/14 and the upper four bits of the TSP50C19 undetermined. Details of the I/O registers are shown in Table 2-3. The TSP50C19 uses 4 bits for port B. Only two of the four are available on the outside of the chip. The remaining two are used as a page select for the ROM. See Section 6.11, TSP50C19 Programming, for more information.
Table 2-3. I/O Registers
(a) I/O register type and location
Location Register Data Input Register (DIR) Pullup Enable Register (PER) Data Direction Register (DDR) Data Output Register (DOR) Type Read Only Read/Write Read/Write Read/Write Port A 080h 081h 082h 083h Port B 084h 085h 086h 087h
For the TSP50C12, the register locations are F0 - F7.
(b) I/O register pin function and pin state
Desired Pin Function Input, High Impedance Input, Internal Pullup Output, Active Pullup Output, Active Pullup Output, Open Drain Output, Open Drain DOR X X 0 1 0 1 DDR 0 0 1 1 1 1 PER 0 1 0 0 1 1 Pin State High Impedance Passive Pullup 0 1 0 High Impedance
A read of the DDR, PER, and DOR registers indicates the last value written to them. A read of the DIR always indicates the actual level on I/O, which is true even when the DDR is set for output. This allows true bidirectional data flow without having to switch the port between input and output. To avoid high-current conditions, this should only be attempted on pins set for open drain with a 1 written to the data register.
2-14
TSP50C0x/1x Functional Description
Leaving a high-impedance I/O pin unconnected could cause power consumption to rise while the processor is in run mode. The power consumption is between VDD and VSS with no increase in current through the input. This should cause no problem with device functionality. When the part is in standby mode, unconnected high-impedance pins have no effect on either power consumption or device functionality. The I/O can also be put in slave mode making the TSP50C0x/1x usable as a peripheral to a host microprocessor. Port A can be connected to an 8-bit data bus and controlled by R/W (PB1) and strobe (PB0). A read (R/W high and strobe low) puts the port A output latch values out on port A. A write (R/W low and strobe low) latches the value on the data bus into the port A input latch. In addition, bit 7 of the A output latch (pin PA7) is cleared. This makes it possible to use PA7 as a write-handshake line. Any lines that are to be used on the data bus in this mode should be configured as inputs. In external ROM mode, the TSP50C0x/1x can be interfaced easily to a TSP60C18 or TSP60C81 speech ROM. PB0 is used as a chip enable strobe output to the TSP60C18 or TSP60C81, and PA7 is used as a clock. PA0 -- PA3 are used for address and data transfer, and one other bit must be used for read/write control of the TSP60C18 or TSP60C81. When the two-pin push-pull option is selected for the D/A output on the TSP50C10/11/12, PB1 is used for the second D/A pin, making it unavailable for I/O. In this case, no attempt should be made to use the PB1 interrupt. If the PCM and LPC mode register bits are both cleared, a high-to-low transition on PB1 causes a level-1 interrupt. This can be used to generate an interrupt with an external event.
2.1.19 Mode Register
The mode register (Table 2-4) is an 8-bit write-only register that controls the operating mode of the TSP50C0x/1x. When INIT goes low, all mode register bits are cleared. The mode register is not saved during a subroutine call or interrupt.
TSP50C0x/1x Family Architecture
2-15
TSP50C0x/1x Functional Description
Table 2-4. Mode Register
(a) Mode register bits
Mode Register Bits 7 UNV 6 MASTER 5 RAMROM 4 EXTROM 3 ENA2 2 PCM 1 LPC 0 ENA1
(b) Mode register bit descriptions
Bit Name ENA1 LPC Bit Low Disables level-1 interrupt Bit High Enables level-1 interrupt
Disables LPC processor - all instruction cycles Enables LPC processor - 53% of instruction used by the microprocessor. cycles dedicated to LPC synthesis when the PCM bit is low and 50% if the instruction cycles are dedicated to LPC synthesis when PCM is set high. Disables PCM mode. Level-1 interrupt is either Enables PCM mode. LPC high causes an interrupt PPC < 200h in LPC mode or pin PB1 otherwise. rate of fosc / 960 and microprocessor control of LPC excitation value. LPC low causes an interrupt rate of fosc / 480 and microprocessor control of D/A register.50% of the instruction cycles are dedicated to LPC synthesis when the PCM bit is set high. Disables level-2 interrupt Enables level-2 interrupt
PCM
ENA2 EXTROM
Disables operation of external ROM hardware Enables operation of external ROM hardware interface. interface.
RAMROM Enables data source for GET instructions to be Enables data source for GET instructions to be either internal or external ROM. internal RAM. MASTER Enables I/O master operation. All available I/O Enables I/O slave operation. Pin PB0 becomes pins are controlled by internal microprocessor. hardware chip enable strobe, and PB1 becomes R/W. Port A is controlled by PB0 and PB1. Enables pitch-controlled excitation sequence Enables random excitation sequence when in when in LPC mode (PCM low, voiced). LPC mode (PCM low, unvoiced).
UNV
2-16
Speech Synthesizer
2.2 Speech Synthesizer
The task of generating synthetic speech is divided between the programmable microprocessor and the dedicated speech synthesizer. The four speech synthesizer modes, which are set by the LPC and PCM bits in the mode register, are discussed in the following paragraphs.
2.2.1
Synthesizer Mode 0 - OFF
When the PCM and LPC bits are both cleared, the synthesizer is disabled. All instruction cycles are devoted to the microprocessor.The TASYN instruction transfers the A register to the pitch register, making it easy to load the pitch register before starting the LPC synthesizer. In this mode, the level-1 interrupt is triggered by a high-to-low transition on pin PB1.
2.2.2
Synthesizer Mode 1 - LPC
This is the normal speaking mode. The TASYN instruction loads the pitch register, and the level-1 interrupt is triggered by the pitch-period counter going below 200h. Fifty-three percent of the instruction cycles are used by the synthesizer. The microprocessor controls speech synthesis by unpacking and decoding parameters, by setting the update interval (frame rate), and by interpolating the parameters during the frame. The speech synthesizer acts as a 12-pole digital lattice filter, a pitch-controlled or white-noise excitation generator, a 2-pole digital low-pass filter, and a digital-to-analog converter. Speech parameter input is received from dedicated space in the microprocessor RAM, and speech samples are generated at 8 kHz or 10 kHz. Communication between the microprocessor and the speech synthesizer takes place via a shared memory space in the microprocessor RAM. Refer to Chapter 6, TSP50C0x/1x Applications, of this book for more information.
2.2.3
Synthesizer Mode 2 - PCM
This mode is used for tone and music generation or for very-high-bit-rate speech. The microprocessor uses all the instruction cycles, and the TASYN instruction transfers the A register directly to the D/A register. The level-1 interrupt occurs at a rate twice the speech sample rate (16 kHz or 20 kHz), giving access to the unfiltered D/A output.
2.2.4
Synthesizer Mode 3 - PCM and LPC
When both the PCM and LPC bits are set, the LPC synthesizer runs normally with its excitation function provided by software. The level-1 interrupt occurs
TSP50C0x/1x Family Architecture
2-17
Speech Synthesizer
at the speech sample rate, and the TASYN instruction transfers the A register to the excitation function input of the synthesizer. This mode is included for use with RELPS (Residual Encoded Linear Predictive Synthesis) and similar techniques. The synthesizer takes 50% of the instruction cycles in this mode.
2.2.5
Use of RAM by the Synthesizer
The synthesizer uses locations 001h to 00Fh in the RAM. When synthesis is taking place, the parameters for the synthesizer come directly from these RAM locations. The addresses are shown in Figure 2-5.
Figure 2-5. RAM Map During Speech Generation
Address 11 10 9 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 8 7 6 5 4 3 2 1 0 Comments Not Used For Synthesis Energy K12 (LPC-12 Values) K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 C1 (Low-Pass Filter) C2
2.2.6
Frame-Length Control
The frame length is controlled by the value put into the prescale register and the range over which the timer is allowed to vary. Typical synthesis and interpolation routines let the timer decrement through a range of fixed size, so the prescale value should be selected to give the proper frame duration based on the timer's range.
2-18
Speech Synthesizer
2.2.7
Digital-to-Analog Converter
The TSP50C0x/1x contains an internal digital-to-analog converter (DAC) connected to the output of the synthesizer. The DAC is available in three pulse-width-modulated forms for the TSP50C10/11 and two pulse-width-modulated forms for the TSP50C04/06/12/13/14/19. See Section 1.3, D/A Options, for more information. The DAC outputs samples at a rate given by fosc / 480. For a 9.6-MHz oscillator, this results in an output sample rate of 20 kHz. For a 7.68-MHz oscillator, this results in an output sample rate of 16 kHz. The DAC output rate is twice the speech sample rate, with a digital low-pass filter in all modes except PCM mode. When the device is initialized, the DAC is placed in an OFF state. This state is the same as a zero state for the two-pin and single-pin double-ended modes, but in the single-pin single-ended mode, the DAC goes to the maximum negative value. This fact must be taken into account to minimize clicks during speech. Once synthesis or PCM generation is turned off following speech or other sound output (return to mode 0), the DAC maintains whatever value was last loaded by the LPC filter or (in PCM mode) the TASYN instruction.
TSP50C0x/1x Family Architecture
2-19
Interrupts
2.3 Interrupts
The TSP50C0x/1x has two interrupts: interrupt-1 and interrupt-2. Both are enabled and disabled by bits in the mode register. Interrupt-1 is a synthesis interrupt and has a higher priority. It also has more hardware support. When an interrupt-1 occurs, the program counter is placed on the program counter stack, and the status flag, integer mode flag, A register, B register, and X register are all saved in dedicated storage registers. The mode register is not saved and restored during interrupts. Then the program counter is loaded with the interrupt start location and execution of the interrupt routine begins. When the interrupt routine returns, all these registers are restored, and the program counter is popped from the stack. Interrupt-1 is caused by 1 of 4 conditions depending on the state of the two mode-register bits PCM and LPC. These conditions, as well as the interrupt routine start address for each case, are shown in Table 2-5.
Table 2-5. Interrupt-1 Vectors
Address 0018h 001Ah 001Ch 001Eh PCM LPC 0 0 1 1 1 0 1 0 Interrupt Trigger Pitch-period counter less than 200h (see subsection 2.1.15) Pin PB1 goes from high to low (see subsection 2.1.18) fosc / 960 clock (see subsection 2.2.4) fosc / 480 clock (see subsection 2.2.3)
Interrupt-2 has a lower priority and cannot interrupt the interrupt-1 routine. It can be interrupted by interrupt-1. During a level-2 interrupt, the program counter, status bit, and integer mode flag are the only registers saved. The A register, X register, and B register must be saved by the program if they are used by both it and the routine being interrupted. The mode register is not saved. Interrupt-2 is always caused by a timer underflow - the timer going from 000h to 0FFh - but it starts at different addresses depending on the state of two mode-register bits. Table 2-6 shows the interrupt-2 vectors.
2-20
Interrupts
Table 2-6. Interrupt-2 Vectors
Address 0010h 0012h 0014h 0016h PCM 0 0 1 1 LPC 1 0 interru ts All level-2 interrupts caused by timer underflow 1 0 Interrupt Trigger
The interrupting conditions for interrupt-1 and interrupt-2 set interrupt-pending latches. If an interrupt is enabled (and in the interrupt-2 case, not overridden by an interrupt-1-pending condition), the interrupt is taken immediately. If, however, the interrupt is not enabled, the pending-interrupt latch causes an interrupt to occur as soon as the respective interrupt is enabled in the mode register. Interrupts are not taken in the middle of double-byte instructions, during branch or call instructions, or during the subroutine or interrupt returns (RETN or RETI). A single instruction software loop (instruction of BR, BRA, CALL, or SBR to itself) should be avoided since an interrupt is never taken. Consecutively executed branches or calls delay interrupts until after the execution of the instruction at the eventual destination of the string of branches (or calls). If consecutive branches (or calls) are avoided, the worst-case interrupt delay in the main level is four instruction cycles. The worst-case delay occurs when the interrupt occurs during the first execution cycle of a branch and the first instruction at the branch destination address is a double-cycle instruction. When the interrupt occurs, execution begins at the interrupt address. The state of the status bit is not known when the interrupt occurs, so a BR or CALL instruction should not be used for the first instruction. Two SBRs may be used, since one of them is always taken, or it may be possible to use some other instruction that sets the status bit, followed by an SBR. The mode register is not saved and restored during interrupts. Any changes made to the mode register during interrupts remains in effect after the return, including the enabling and disabling of interrupts. Note: If a level-1 interrupt is followed immediately by a RETI, the potential exists with some single byte instructions to corrupt the A register upon return. To avoid this problem, do not place a RETI immediately at the interrupt vector. Instead, precede the RETI with a CLA or some other instruction.
TSP50C0x/1x Family Architecture
2-21
TSP50C12 LCD Functional Description
2.4 TSP50C12 LCD Functional Description
The LCD functionality of the TSP50C12 is included without adding instructions to the instruction set. An additional 192 bits of RAM are added to serve as the display RAM. The display RAM is physically placed at RAM addresses 080h - 097h. As a result, port A's registers are mapped from 0F0h to 0F3h and port B's registers are mapped from 0F4h to 0F7h. This RAM mapping is consistent with the SE50C10 emulator device used in the extended RAM mode (pin controllable). When data is stored into the display RAM locations, it may immediately affect the voltage levels on the LCD segment outputs. Because the microprocessor access of RAM is time multiplexed with LCD access, there are no asynchronous ambiguities on segment outputs. If the display RAM update routines are slow, it may be necessary to buffer the display data in another area of RAM and then transfer it to the display RAM in a more time efficient block move. An LCD voltage reference generator is also included on the TSP50C12. This circuit eliminates the need for an external voltage reference generator.
2.4.1
TSP50C12 LCD Driver
The TSP50C12 can drive an 8 x 24 (192-segment) LCD display with 1/8 duty cycle. The driver function for the LCD is controlled by internal timing hardware. Display data for the LCD is stored in a dedicated section of RAM. This data is stored in pixel form with 24 consecutive 8-bit words. Table 2-7 shows the memory locations for each pixel.
2-22
TSP50C12 LCD Functional Description
Table 2-7. TSP50C12 Display RAM Map
Address 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h
NOTE:
MSB S24c1 S16c1 S8c1 S24c2 S16c2 S8c2 S24c3 S16c3 S8c3 S24c4 S16c4 S8c4 S24c5 S16c5 S8c5 S24c6 S16c6 S8c6 S24c7 S16c7 S8c7 S24c8 S16c8 S8c8 S23c1 S15c1 S7c1 S23c2 S15c2 S7c2 S23c3 S15c3 S7c3 S23c4 S15c4 S7c4 S23c5 S15c5 S7c5 S23c6 S15c6 S7c6 S23c7 S15c7 S7c7 S23c8 S15c8 S7c8 S22c1 S14c1 S6c1 S22c2 S14c2 S6c2 S22c3 S14c3 S6c3 S22c4 S14c4 S6c4 S22c5 S14c5 S6c5 S22c6 S14c6 S6c6 S22c7 S14c7 S6c7 S22c8 S14c8 S6c8 S21c1 S13c1 S5c1 S21c2 S13c2 S5c2 S21c3 S13c3 S5c3 S21c4 S13c4 S5c4 S21c5 S13c5 S5c5 S21c6 S13c6 S5c6 S21c7 S13c7 S5c7 S21c8 S13c8 S5c8 S20c1 S12c1 S4c1 S20c2 S12c2 S4c2 S20c3 S12c3 S4c3 S20c4 S12c4 S4c4 S20c5 S12c5 S4c5 S20c6 S12c6 S4c6 S20c7 S12c7 S4c7 S20c8 S12c8 S4c8 S19c1 S11c1 S3c1 S19c2 S11c2 S3c2 S19c3 S11c3 S3c3 S19c4 S11c4 S3c4 S19c5 S11c5 S3c5 S19c6 S11c6 S3c6 S19c7 S11c7 S3c7 S19c8 S11c8 S3c8 S18c1 S10c1 S2c1 S18c2 S10c2 S2c2 S18c3 S10c3 S2c3 S18c4 S10c4 S2c4 S18c5 S10c5 S2c5 S18c6 S10c6 S2c6 S18c7 S10c7 S2c7 S18c8 S10c8 S2c8
LSB S17c1 S9c1 S1c1 S17c2 S9c2 S1c2 S17c3 S9c3 S1c3 S17c4 S9c4 S1c4 S17c5 S9c5 S1c5 S17c6 S9c6 S1c6 S17c7 S9c7 S1c7 S17c8 S9c8 S1c8
S - Segment or pixel on a given row (common time) c - Row (common time)
TSP50C0x/1x Family Architecture
2-23
TSP50C12 LCD Functional Description
2.4.2
TSP50C12 LCD Drive Type A
The Type A drive method places limitations on the series resistance and pixel capacitance of the display. This drive type requires a more complex LCD display. The Type A option must be selected by the customer and given to TI before releasing the device for mask tooling. Figure 2-6 shows the timing waveforms for the LCD type A option.
2-24
TSP50C12 LCD Functional Description
Figure 2-6. TSP50C12 LCD Driver Type A Timing Diagram
Vr -Vr' Vc' Vr' -Vr 1 Frame Period Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr
c1
c2
c8
S1 (c1/c3/c8 on)
S2 (c1/c2/c6 on)
S3 (c1 - c8 on)
Differential Voltage Across Pixel S1c1 (Vcommon - Vsegment)
4V V 0V -V - 4V 2V V 0V -V -2V
S1c1 "on"
S1c2 "off"
TSP50C0x/1x Family Architecture
2-25
TSP50C12 LCD Functional Description
2.4.3
TSP50C12 LCD Drive Type B
The Type B drive method operates at a lower frequency, allowing the common signal to go high on the first frame and to go low on the next frame. This option is preferred for applications that have large capacitance pixel loads and high series trace resistances. This method also might be used if the microprocessor is operated at higher frequencies. The Type B option must be selected by the customer and given to TI before releasing the device for mask tooling. Figure 2-7 shows the timing waveforms for the LCD type B option.
2-26
TSP50C12 LCD Functional Description
Figure 2-7. TSP50C12 LCD Driver Type B Timing Diagram
Vr -Vr' Vc' Vr' -Vr
c1 1 Frame Period
c2
Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr Vr -Vr' Vc' Vr' -Vr
c8
S1 (c1/c3/c8 on)
S2 (c1/c2/c6 on)
S3 (c1 - c8 on)
Differential Voltage Across Pixel S1c1 (Vcommon - Vsegment)
4V V 0V -V - 4V 2V V 0V -V -2V
S1c1 "on"
S1c2 "off"
TSP50C0x/1x Family Architecture
2-27
TSP50C12 LCD Reference Voltage and Contrast Adjustment
2.5 TSP50C12 LCD Reference Voltage and Contrast Adjustment
The TSP50C12 contains an internal voltage-reference generator to regulate and adjust the LCD reference voltages. The voltage generator is comprised of a voltage doubler, a bandgap reference, a voltage regulator, and a final trim DAC. VLCD provides an isolated voltage supply for the voltage doubler. VLCD can be connected to VDD or, for example, can be connected to a 4.5-V tap of a 4-cell battery supply to improve the power efficiency of the circuit. An external capacitor should be connected between VC1 and VC2. An external capacitor should be connected between VX2 and VLCD. The bandgap provides a reference voltage for the voltage regulator. The voltage regulator has a nominal output of 4.9 V ( 200 mV). The reference voltage can be trimmed by writing to the DAC (memory-mapped to the lower four bits at RAM location 098h). The trim control ranges from - 8 steps (0000) to +7 steps (1111) from nominal with each step being approximately 100 mV. The value of this RAM location is not initialized and must be set by the initialization software routine. Figure 2-8 shows a diagram for the voltage doubler circuitry.
Figure 2-8. TSP50C12 Voltage Doubler
TSP50C12 VC1 Cpump 0.01 F VC2 VX2 Cstore 0.047 F VLCD 470 VDD
2-28
TSP50C12 Clock Options
2.6 TSP50C12 Clock Options
The RC oscillator requires a single external resistor between VDD and OSC1 with OSC2 left unconnected to set the operating frequency. The frequency shift, as VDD changes, is limited to 10% over the operating range of 4 V to 6.5 V. The center frequency as a function of resistance requires trimming. For applications requiring greater clock precision, a ceramic resonator option is also available. The RC oscillator/ceramic resonator selection must be made by the customer and given to TI before releasing the device for mask tooling.
Figure 2-9. RC OSC Option Circuit
OSC1 100 k OSC2
TSP50C0x/1x Family Architecture
2-29
2-30
Running Title--Attribute Reference
Chapter 3
TSP50C0x/1x Electrical Specifications
This chapter contains electrical and timing information for the TSP50C0x/1x family devices, organized according to device category.
Topic
3.1 3.2 3.3 3.4 3.5 3.6
Page
Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 TSP50C0x/1x Recommended Operating Conditions . . . . . . . . . . . . . . 3-3 TSP50C0x/1x Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 TSP50C10/11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 TSP50C12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TSP50C04/06/13/14/19 Electrical Characteristics . . . . . . . . . . . . . . . . 3-10
Chapter Title--Attribute Reference
3-1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 8 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Maximum Supply Current (IDD and ISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range (TSP50C04/06/10/11/12/13/14) . . . . . . . . . . . . . - 30C to 125C Storage temperature range (TSP50C19 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to ground.
Stresses beyond those listed here may cause permanent damage to the device. This is a stress rating only.
3-2
Recommended Operating Conditions
3.2 Recommended Operating Conditions
The following table contains recommended operating characteristics for the TSP50C0x/1x family.
Table 3-1. Recommended Operating Conditions
MIN VDD VIH Supply voltage High-level input voltage VDD = 4 V VDD = 5 V VDD = 6 V VDD = 4 V VIL Low-level input voltage VDD = 5 V VDD = 6 V Device functionality LCD reference spec (TSP50C12 only) 10-kHz speech sample rate 8-kHz speech sample rate External ROM mode interface to TSP60C18 speech ROMs TSP50C04/06/13/14/19 direct speaker drive using 2 pin push-pull DAC option fosc / 4 32 4 3 3.8 4.5 0 0 0 0 10 9.6 7.68 NOM MAX 6.5 4 5 6 0.8 1 1.3 70 40 C MHz MHz V V UNIT V
TA fosc fclock Rspeaker
Operating free air temperature free-air
Clock frequency ROM clock frequency Minimum speaker impedance
Unless otherwise noted, all voltages are with respect to VSS. Speech sample rate = fosc / 960.
TSP50C0x/1x Electrical Specifications
3-3
Timing Requirements
3.3 Timing Requirements
The following tables give timing requirements and the following figures give timing waveforms for the TSP50C0x/1x family.
Table 3-2. D/A Options Timing Requirements
MIN tr tf Rise time, PAx, PBx, D/A options 1, 2 Fall time, PAx, PBx, D/A options 1, 2 VDD = 4 V V, CL = 100 pF NOM 22 10 MAX Unit ns ns
Table 3-3. Initialization Timing Requirements
MIN tINIT tsu(INIT) INIT pulsed low while the TSP50C0x/1x has power applied Minimum delay VDD to INIT 1 2 MAX UNIT s s
Figure 3-1. Initialization Timing Diagram
INIT
tINIT
Table 3-4. Write Timing Requirements (Slave Mode)
MIN tsu(PB1) tsu(d) th(PB1) th(d) tw tr tf Setup time, PB1 low before PB0 goes low Setup time, data valid before PB0 goes high Hold time, PB1 low after PB0 goes high Hold time, data valid after PB0 goes high Pulse duration, PB0 low Rise time, PB0 Fall time, PB0 20 100 20 30 100 50 50 MAX UNIT ns ns ns ns ns ns ns
Figure 3-2. Write Timing Diagram (Slave Mode)
PB1 tsu(PB1) tw PB0 tf tr tsu(d) th(d) PA Data Valid th(PB1)
3-4
Timing Requirements
Table 3-5. Read Timing Requirements (Slave Mode)
MIN tsu(PB1) th(PB1) tdis tw tr tf td Setup time, PB1 before PB0 goes low Hold time, PB1 after PB0 goes high Output disable time, data valid after PB0 goes high Pulse duration, PB0 low Rise time, PB0 Fall time, PB0 Delay time for PB0 low to data valid 20 20 0 100 50 50 50 30 MAX UNIT ns ns ns ns ns ns ns
Figure 3-3. Read Timing Diagram (Slave Mode)
PB1 tsu(PB1) tw PB0 tf td PA Data Valid tr tdis th(PB1)
Table 3-6. External Interrupt Timing Requirements
MIN tw(PB1) (PB1) Pulse duration before PB1 goes low duration, fclock = 7.6 MHz fclock = 9.6 MHz 2 2.5 MAX UNIT s
Figure 3-4. External Interrupt Timing Diagram
tw(PB1) PB1
TSP50C0x/1x Electrical Specifications
3-5
TSP50C10/11 Electrical Characteristics
3.4 TSP50C10/11 Electrical Characteristics
Table 3-7 gives specifications and the Figure 3-5 gives the input leakage current that applies to the TSP50C10 and TSP50C11.
Table 3-7. TSP50C10/11 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted)
PARAMETER VT T+ VT T- Vh hys IIkg Istandby IDD Positive-going threshold voltage gg g (INIT) Negative-going threshold voltage g gg g (INIT) Hysteresis ( VT - VT ) (INIT) T+ T- Input leakage current (except for OSC1, INIT see Figure 3-5) Standby current (INIT low) Supply current D/A option 1, 2, or 3 VDD = 4 V, VDD = 5 V, IOH High-level output current g (PAx, PBx, D/A options 1, 2) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VDD = 4 V, VDD = 5 V, IOL Low-level output current (PAx, PBx, D/A options 1, 2) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, Pullup resistance VOH = 3.5 V VOH = 4.5 V VOH = 5.5 V VOH = 2.67 V VOH = 3.33 V VOH = 4 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.33 V VOL = 1.67 V VOL = 2 V -4 -5 -6 -8 -14 - 20 10 13 15 20 30 41 15 5 -6 -7.5 - 9.2 -13 - 20 - 29 17 20 25 32 52 71 30 60 k mA mA mA mA TEST CONDITIONS VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V MIN TYP 2.7 3.65 2.3 3.15 0.4 0.5 1 10 MAX UNIT V V V A A mA
Resistors selected with software and connected between pin and VDD
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited.
3-6
TSP50C10/11 Electrical Characteristics
Figure 3-5. Typical Input Leakage Current on INIT
Typical Input Leakage Current On Init Vs Input Voltage
30
Input Leakage Current (INIT) - A
25
20 VDD = 6.5 V 15 VDD = 3.9 V 10
5
0 0 1 1.5 2 2.5 3 VI - Input Voltage (INIT) - V 3.5 4
TSP50C0x/1x Electrical Specifications
3-7
TSP50C12 Electrical Characteristics
3.5 TSP50C12 Electrical Characteristics
Table 3-8 gives specifications that apply to the TSP50C12.
Table 3-8. TSP50C12 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted)
PARAMETER VT T+ VT T- Vh hys Positive-going threshold voltage gg g (INIT) Negative-going threshold voltage g gg g (INIT) Hysteresis ( VT - VT ) (INIT) T+ T- Vr -Vr ' LCD reference voltages Vc' Vr ' -Vr Vr LCD temperature coefficient DAC step IIkg Istandby IDD Input leakage current (except for OSC1, INIT see Figure 3-5) Standby current (INIT low) Supply current D/A option 1 or 3 VDD = 4 V, VDD = 5 V, IOH High-level output current g (PAx, PBx, D/A options 1) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VDD = 4 V, VDD = 5 V, IOL Low-level output current (PAx, PBx, D/A options 1) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VOH = 3.5 V VOH = 4.5 V VOH = 5.5 V VOH = 2.67 V VOH = 3.33 V VOH = 4 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.33 V VOL = 1.67 V VOL = 2 V -4 -5 -6 -8 -14 - 20 10 13 15 20 30 41 5 -6 -7.5 - 9.2 -13 - 20 - 29 17 20 25 32 52 71 mA mA mA mA TA = 0C to 40C DAC step control of Vr with respect to -Vr, VDD = 5 V, TA = 25C 74 TEST CONDITIONS VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V 4.7 3.717 DAC register = 1000, TA = 25C it 1000 25C, See Figures 2 - 5 and 2 - 6 2.734 1.751 0.767 MIN TYP 2.7 3.65 2.3 3.15 0.4 0.5 4.9 3.875 2.85 1.825 0.8 -2.5 100 124 1 10 5.1 4.033 2.966 1.899 0.833 mV/C mV A A mA V MAX UNIT V V V
This negative temperature coefficient is normally advantageous because it tracks the temperature variation of most LCD materials. Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited.
3-8
TSP50C12 Electrical Characteristics
Table 3-8. TSP50C12 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature(unless otherwise noted) (Continued)
PARAMETER Pullup resistance DAC buffer drive (D/A option 1) LCD frame rate TEST CONDITIONS Resistors selected with software and connected between pin and VDD 32- load connected across DA1 and DA2, VDD = 4.5 V fOSC = 9.6 MHz MIN 15 TYP 30 60 96 MAX 60 UNIT k mA Hz
TSP50C0x/1x Electrical Specifications
3-9
TSP50C04/06/13/14/19 Electrical Characteristics
3.6 TSP50C04/06/13/14/19 Electrical Characteristics
Table 3-9 gives specifications that apply to the TSP50C04, TSP50C06, TSP50C13, TSP50C14, and the TSP50C19.
Table 3-9. TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted)
PARAMETER VT T+ VT T- Vh hys IIkg Istandby IDD Positive-going Positive going threshold voltage (INIT) Negative-going Negative going threshold voltage (INIT) Hysteresis ( VT - VT ) (INIT) T+ T- Input leakage current (except for OSC1, INIT see Figure 3-5) Standby current (INIT low) Supply current DAC option 1 or 2 VDD = 4 V, VDD = 5 V, High-level output current (D / A g ( options 1, 2) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VDD = 4 V, VDD = 5 V, High-level High level output current (PAx, PBx) (PAx VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VOH = 3.5 V VOH = 4.5 V VOH = 5.5 V VOH = 2.67 V VOH = 3.33 V VOH = 4 V VOH = 3.5 V VOH = 4.5 V VOH = 5.5 V VOH = 2.67 V VOH = 3.33 V VOH = 4 V - 27 -34 -41 -54 -95 -136 -4 -5 -6 -8 -14 - 20 5 -41 -51 -63 -88 -136 -197 -6 -7.5 - 9.2 -13 - 20 - 29 mA mA mA mA TEST CONDITIONS VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V VDD = 4.5 V VDD = 6 V MIN TYP 2.7 3.65 2.3 3.15 0.4 0.5 1 10 MAX UNIT V V V A A mA
IOH
Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited.
3-10
TSP50C04/06/13/14/19 Electrical Characteristics
Table 3-9 TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (unless otherwise noted) (Continued)
PARAMETER TEST CONDITIONS VDD = 4 V, VDD = 5 V, Low-level output current (D / A options ( 1, 2) VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, VDD = 4 V, VDD = 5 V, Low-level Low level output current (PAx, PBx) (PAx VDD = 6 V, VDD = 4 V, VDD = 5 V, VDD = 6 V, Pullup resistance VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.33 V VOL = 1.67 V VOL = 2 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.33 V VOL = 1.67 V VOL = 2 V MIN 27 34 41 54 95 136 10 13 15 20 30 41 15 7.21 9.02 TYP 41 51 63 88 136 197 17 20 25 32 52 71 30 7.68 9.6 60 8.15 MHz 10.2 k mA mA mA mA MAX UNIT
IOL
Resistors selected with software and connected between pin and VDD 7.68-MHz target frequency, VDD = 5 V, TA = 25C 9.6-MHz target frequency, VDD = 5 V, TA = 25C
fosc
Oscillator frequency
The frequency of the internal clock has a temperature coefficient of approximately - 0.2 % / C and a VDD coefficient typical = 3%/V and a maximum =5.4% / V.
TSP50C0x/1x Electrical Specifications
3-11
3-12
Running Title--Attribute Reference
Chapter 4
TSP50C0x/1x Assembler
The TSP50C0x/1x assembler chapter describes how to invoke the assembler, assembler command-line options, source-statement format, assembler symbols and characters, and assembler directives.
Topic
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
Page
Description of Notation Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Invoking the Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Command-Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Assembler Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Source-Statement Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Character Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Chapter Title--Attribute Reference
4-1
Description of Notation Used
4.1 Description of Notation Used
The notation used in this document is as follows:
-
An optional field is indicated by brackets; for example, [LABEL] User-supplied contents are indicated by braces; for example, < num > A reserved keyword is shown in capital letters. A required blank is indicated by a caret (^).
The following syntax example demonstrates the notational conventions used in this guide. [< name >] ^ SBR ^ < number > ^ [< comment >]
4-2
Invoking the Assembler
4.2 Invoking the Assembler
The assembler is invoked by typing: ASM10 ^ [] ^ where:
-
-
Options represents a list of assembler options (see Section 4.3, Command-Line Options). Source is the name of the source file with the extension optional. If the extension is not given, then the default extension .asm is assumed. For example:
ASM10 -l PROGRAM
runs the assembler using the source file program.asm and generates the output object file program.bin. No list file is generated.
TSP50C0x/1x Assembler
4-3
Command-Line Options
4.3 Command-Line Options
Several options can be invoked from the command line (Table 4-1). They are invoked by listing their abbreviation prefixed by a minus sign. The following example:
ASM10 -Lo PROGRAM.ASM
assembles the program in file program.asm but does not generate either a listing file or an object file; however, any errors are written to the console. The available options are detailed in Table 4-1. See subsection 4.9.10, OPTION Directive, for information on invoking options from within the source code.
Table 4-1. Switches and Options
Character or Number B or b D or d I or i L or l O or o P or p R or r S or s T or t W or w X or x 9 Action Lists only the first data byte in BYTE or RBYTE Lists only the first data byte in DATA or RDATA Counts the number of times a valid instruction has been used Displays error messages without generating a list Disables object file output Prints listing without page breaks Produces a reduced cross-reference list Writes no errors on screen unless listing file is generated Lists only the first data byte in TEXT or RTEXT Suppresses the warning message Adds a cross-reference list at the end Generates object file in TI-990 tagged object format
4.3.1
BYTE Unlist Option
Placing a b or B in the command-line option field causes the assembler to list only the first opcode in a BYTE or RBYTE statement. Normally, if a BYTE or RBYTE statement has n arguments, they are listed in a column running down the page in the opcode column of the listing, taking n lines to completely list the resulting opcodes. If the BYTE unlist switch is set, then only the first line (which also contains the source line listing) is written to the listing file.
4-4
Command-Line Options
4.3.2
DATA Unlist Option
Placing a d or D in the command-line option field causes the assembler to list only the first opcode in a DATA or RDATA statement. Normally, if a DATA or RDATA statement has n arguments, they are listed in a column running down the page in the opcode column of the listing, taking n lines to completely list the resulting opcodes. If the DATA unlist switch is set, then only the first line (which also contains the source line listing) is written to the listing file.
4.3.3
XREF Unlist Option
Placing an x or X in the command-line option field causes the assembler to add a cross-reference listing at the end of the listing file.
4.3.4
TEXT Unlist Option
Placing a t or T in the command-line option field causes the assembler to list only the first opcode in a TEXT or RTEXT statement in the listing file. Normally, if a TEXT or RTEXT statement has as an argument a string containing n characters, the ASCII representation of these n characters is written in a column in the opcode column of the listing. If the TEXT unlist switch is set, only the first line (also containing the source line listing) is written to the list file.
4.3.5
WARNING Unlist Option
Placing a w or W in the command-line option field causes the assembler to suppress WARNING messages. Warnings are still counted and error messages are still generated.
4.3.6
Complete XREF Switch
Placing an r or R in the command-line option field causes the assembler to produce a reduced XREF listing if one is produced. Normally, all symbols (whether used or not) are listed in the XREF listing. The r option causes the assembler to omit from the XREF listing all symbols from the copy files that were never used.
4.3.7
Object Module Switch
Placing an o or O in the command-line option field causes the assembler to not generate any object output modules.
4.3.8
Listing File Switch
Placing an l or L in the command-line option field causes the assembler to not generate the listing file but to display any error messages to the screen.
TSP50C0x/1x Assembler
4-5
Command-Line Options
4.3.9
Page-Eject Disable Switch
Placing a p or P in the command-line option field causes the assembler to print the listing in a continual manner without division into separate pages. When desired, a form feed may still be forced using the PAGE command.
4.3.10 Error-to-Screen Switch
Placing an s or S in the command-line option field causes the assembler to not write errors to the screen unless no listing file is being generated.
4.3.11 Instruction Count Switch
Placing an i or I in the command-line option field causes the assembler to generate a table containing the number of times each valid instruction was used in the program.
4.3.12 Binary-Code File-Disable Switch
Placing a 9 in the command-line option field causes the assembler to generate the object module in tagged-object format in a file with a .mpo extension instead of the normal binary formatted object module in a file with a .bin extension.
4-6
Assembler Input and Output Files
4.4 Assembler Input and Output Files
The assembler takes as input a file containing the assembly source and produces as output a listing file and an object file in either binary format or tagged object format.
4.4.1
Assembly Source File
The assembly source file is specified in the command line. If the filename in the command line has an extension, then the file name is used as given. If no extension is specified, then the extension .asm is assumed. For example:
ASM10 PROGRAM.SRC
uses the file program.src as the assembly source file.
ASM10 PROGRAM
uses the file program.asm as the assembly source file.
4.4.2
Assembly Binary Object File
The assembly process produces an object file in binary format by default. The object output is placed in a file with the same file name as the assembly source except that the extension is .bin. If the binary file is not desired, it can be disabled either as a command-line option or with an OPTION statement. For example:
ASM10 PROGRAM.SRC
uses the file program.src as the assembly source file and the file program.bin as the binary object output file.
ASM10 -O PROGRAM.SRC
uses the file program.src as the assembly source file and produces no object output.
TSP50C0x/1x Assembler
4-7
Assembler Input and Output Files
4.4.3
Assembly Tagged Object File
If desired, the assembler can substitute an object file in tagged object format instead of the object file in binary format. If produced, the object output is placed in a file with the same file name as the assembly source except that the extension is .mpo. For example:
ASM10 -9 PROGRAM.SRC
uses the file program.src as the assembly source file and the file program.mpo as the tagged object output file. No binary-formatted object file is produced.
4.4.4
Assembly Listing File
The assembly process produces a listing file that contains the source instructions, the assembled code, and (optionally) a cross-reference table. The listing file is placed in a file with the same file name as the assembly source except that the extension is .lst. For example:
ASM10 PROGRAM.SRC
uses the file program.src as the assembly source file and the file program.lst as the assembly listing file.
4-8
Source-Statement Format
4.5 Source-Statement Format
An assembly-language source program consists of source statements contained in the assembly source file(s) that may contain assembler directives, machine instructions, or comments. Source statements may contain four ordered fields separated by one or more blanks. These fields (label, command, operand, and comment) are discussed in the following paragraphs. The source statement can be as long as 80 characters. If the form width is set to 80 characters (the default), the assembler truncates the source line at 60 characters. The user should ensure that nothing other than comments extend past column 60. Any source line starting with an asterisk (*) in the first character position is treated as a comment in its entirety. It is ignored by the assembler and has no effect on the assembly process. The syntax of the source statements is: [] ^ COMMAND ^ ^ [] A source statement may have an optional label that is defined by the user. One or more blanks separate the label from the COMMAND mnemonic. One or more blanks separate the mnemonic from the operand (if required by the command). One or more blanks separate the operand from the comment field. Comments are ignored by the assembler.
4.5.1
Label Field
The label field begins in character position one of the source line. If position one is a character other than a blank or an asterisk, the assembler assumes that the symbol is a label. If a label is omitted, then the first character position must be a blank. The label may contain up to ten characters consisting of alphabetic characters (a - z, A - Z), numbers (0 - 9), and some other characters (@,$,_ ). The first character should be an alphabetic character, and the remaining nine character positions can be any of the legal characters listed above.
4.5.2
Command Field
The command field begins after the blank that terminates the label field or in the first nonblank character past the first character position (which must be blank when the label is omitted). The command field is terminated by one or more blanks and may not extend past the sixtieth character position. The
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Source-Statement Format
command field may contain either an assembler mnemonic (e.g., TAX) or an assembler directive (e.g., OPTION). The assembler does not distinguish between capital and small letters in the command name; for example, TAX, Tax, and tAX are all identical names to the assembler.
4.5.3
Operand Field
The operand field begins following the blank that terminates the command field and may not extend past the sixtieth column position. The operand may contain one or more constants or expressions described in subsection 4.5.5, Constants, through subsection 4.5.10, Assembly-Time Constants. Terms in the operand field are separated by commas. The operand field is terminated by the first blank encountered.
4.5.4
Comment Field
The comment field begins after the blank that terminates the operand field or the blank that terminates the command field if no operand is required. The comment field may extend to the end of the source record and may contain any ASCII character including blanks.
4.5.5
Constants
The assembler recognizes the following five types of constants: Decimal integer constants Binary integer constants Hexadecimal integer constants Character constants Assembly-time constants
4.5.6
Decimal Integer Constants
A decimal integer constant is written as a string of decimal digits. The range of values of decimal integers is -32,768 to 65,535. Positive decimal integer constants greater than 32,767 are considered negative when interpreted as two's complement values. The following are valid decimal constants: 1000 -32768 25 Constant equal to 1000 or 03E8h Constant equal to -32768 or 8000h Constant equal to 25 or 0019h
4.5.7
Binary Integer Constants
A binary integer constant is written as a string of up to 16 binary digits (0/1) preceded by a question mark (?). If less than 16 digits are specified, the assembler right-justifies the given bits in the resulting constant.
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Source-Statement Format
The following are valid binary constants: ?0000000000010011 ?0111111111111111 ?11110 Constant equal to 19 or 0013h Constant equal to 32767 or 7FFFh Constant equal to 30 or 001Eh
4.5.8
Hexadecimal Integer Constants
A hexadecimal integer constant is written as a string of up to four hexadecimal digits preceded by a number sign (#) or a greater than sign (>). If less than four hexadecimal digits are specified, the assembler right-justifies the bits that are specified in the resulting constant. Hexadecimal digits include the decimal values 0 through 9 and the letters a (or A) through f (or F). The following are valid hexadecimal constants: #07F >#07f #307A Constant equal to 127 (or 007Fh) Constant equal to 127 (or 007Fh) Constant equal to 12410 (or 307Ah)
4.5.9
Character Constants
A character constant is written as a string of one or two alphabetic characters enclosed in single quotes. A single quote can be represented within the character constant by two successive quotes. If less than two characters are specified, the assembler right-justifies the given bits in the resulting constant. The characters are represented internally as 8-bit ASCII characters. A character constant consisting of only two single quotes (no character) is valid and is assigned the value 0000h. The following are valid character constants: 'AB' 'C' '"D' Constant equal to 4142h Constant equal to 0043h Constant equal to 2744h
4.5.10 Assembly-Time Constants
An assembly-time constant is a symbol given a value by an EQU directive (see subsection 4.9.5, EQU Directive). The value of the symbol is determined at assembly time and may be assigned values with expressions using any of the constant types.
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Symbols
4.6 Symbols
Symbols are used in the label field and the operand field. A symbol is a string of ten or fewer alphanumeric characters (a - z, A - Z, 0 - 9, and the characters @, _, and $). Uppercase and lowercase characters are not distinguished from one another; for example, A1 and a1 are treated identically by the assembler. No character may be blank. When more than ten characters are used in a symbol, the assembler prints all the characters but issues a warning message that the symbol has been truncated and uses only the first ten characters for processing. Symbols used in the label field become symbolic addresses. They are associated with locations in the program and must not be used in the label field of other statements. Mnemonic operation codes and assembler directives may also be used as valid user-defined symbols when placed in the label field. Symbols used in the operand field must be defined in the assembly, usually by appearing in the label field of a statement or in the operand field of an EQU directive. The following are examples of valid symbols:
START Start strt_1
Predefined Symbol $
The dollar sign ($) is a predefined symbol given the value of the current location within the program. It can be used in the operand field to indicate relative program offsets. For example:
BR $+6
results in a branch to an address six bytes beyond the current location.
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Character Strings
4.7 Character Strings
Several assembler directives require character strings in the operand field. A character string is written as a string of characters enclosed in single quotes. A quote may be represented in the string by two successive quotes. The maximum length of the string is defined for each directive that requires a character string. The characters are represented internally as 8-bit ASCII. The following are valid character strings:
'SAMPLE PROGRAM' 'Plan ''C'''
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Expressions
4.8 Expressions
Expressions are used in the operand fields of assembler instructions and directives. An expression is a constant or symbol, a series of constants or symbols, or a series of constants and symbols separated by arithmetic operators. Each constant or symbol may be preceded by a minus sign (unary minus) or a plus sign (unary plus). Unary minus is the same as taking the two's complement of the value. An expression must not contain embedded blanks. The valid range of values in an expression is - 32,768 to 65,535. The value of all terms of an expression must be known at assembly time.
4.8.1
Arithmetic Operators in Expressions
The following arithmetic operators may be used in an expression: ~ + - * / % & ++ && inversion addition subtraction multiplication division (remainder is truncated) modulo (remainder after division) bitwise AND bitwise OR bitwise EXCLUSIVE-OR
In evaluating an expression, the assembler first negates any constant or symbol preceded by a unary minus and then performs the arithmetic operations from left to right. The assembler does not assign arithmetic operation precedence to any operation other than unary plus or unary minus (so that the expression 4 + 5 * 2 is evaluated as 18, not 14).
4.8.2
Parentheses In Expressions
The assembler supports the use of parentheses in expressions to alter the order of evaluating the expression. Nesting parentheses within expressions is also supported. When parentheses are used, the portion of the expression within the innermost parentheses is evaluated first, and then the portion of the expression within the next innermost pair is evaluated. When evaluation of the portions of the expression within the parentheses has been completed, the evaluation is completed from left to right. Evaluation of portions of an expression within parentheses at the same nesting level is considered as simultaneous. Parenthetical expressions may not be nested more than eight deep.
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Assembler Directives
4.9 Assembler Directives
Assembler directives (Table 4-2) are instructions that modify the assembler operation. They are invoked by placing the directive mnemonic in the command field and any modifying operands in the operand field. The valid directives are described in the following paragraphs.
Table 4-2. Summary of Assembler Directives
Directives That Affect the Location Counter Mnemonic AORG Directive Absolute origin Syntax []^AORG^^[] Directives That Affect Assembler Output IDT LIST NARROW OPTION PAGE TITL UNL WIDE Program identifier Restart source listing 80-column form width Output options Page eject Page title Stop source listing 130-column form width []^IDT^''^[] []^LIST^[] []^NARROW^[] []^OPTION^

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