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Features
* * * * * * * * * * * * * *
Supply voltage up to 40 V RDSon typ. 0.5 @ 25C, max. 1 @ 150C Up to 1.5 A output current Three high-side and three low-side drivers usable as single outputs or half bridges Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors PWM capability for each output controlled by external PWM signal No crossover current Very low quiescent current Is < 10 A in stand-by mode over total temperature range Outputs short-circuit protected Selective overtemperature protection for each switch and overtemperature prewarning Undervoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power-supply fail Serial data interface, daisy chain capable, up to 2 MHz clock frequency SO16 power package
Description
T6819 / T6829 are fully protected driver interfaces designed in 0.8 m BCDMOS technology. It is used to control up to 6 different loads by a microcontroller i n a u t o m o t i v e a n d i n d u s t r i a l applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A. Each driver is free configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. The capability to control each output with an external PWM signal opens additional applications. Protection is guaranteed in terms of s h o r t - c i r c u i t c o n d i t i o n s , o v e r temperature and undervoltage. Various diagnosis functions and a very low quiescent current in stand-by mode opens a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection give added value and enhanced quality for demanding up-market applications.
Dual Triple DMOS Output Driver with Serial Input Control T6819 T6829
Ordering Information
Extended Type Number T6819-TBS T6819-TBQ T6829-TBS T6829-TBQ Package SO16 SO16 SO16 SO16 Remarks Power package, tubed Power package, taped and reeled Power package with heat slug, tubed Power package with heat slug, taped and reeled
Rev. A1, 12-Nov-01
Preliminary Information
1 (16)
Preliminary Information
Block Diagram
Figure 1.
OUT3H
4
OUT2H
14
OUT1H
13
Fault detect
Fault detect
Fault detect
Charge pump
12
6
DI
Vs
7
CLK
S I
O C S
O L D
P H 3
P L 3
P H 2
P L 2
P H 1
P L 1
H S 3
L S 3
H S 2
L S 2
H S 1
L S 1
S R R
5
Input register Output register
P S F I N H O V L n. u. n. u. n. n. u. u.
Serial interface
n. n. u. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1
Control logic
UV protection Power-on reset
11
CS
Vcc
10
DO
16 PWM 8
Fault detect Fault detect Fault detect
GND
Thermal protection
9
GND GND
1 3 15 2
OUT3L
OUT2L
OUT1L
2 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Pin Configuration
Figure 2.
GND OUT1L OUT3L OUT3H CS DI CLK PWM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OUT2L OUT2H OUT1H VS VCC DO GND
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND OUT1L OUT3L OUT3H CS DI CLK PWM GND DO VCC VS OUT1H OUT2H OUT2L GND Function T6819: Ground; reference potential; internal connection to Pin 9 and Pin 16; cooling tab T6829: Additional connection to heat slug Low-side driver output 1; Power-MOS open drain with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Low-side driver output 3; see Pin 2 High-side driver output 3; Power-MOS open source with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs which are selected for PWM mode by the serial data interface Ground; see Pin 1 Serial data output; 5-V CMOS logic-level tristate output for output (status) register data; sends 16-bit status information to the C (LSB is transferred first); output will remain tristated, unless device is selected by CS = low, therefore, several ICs can operate on one data-output line only. Logic supply voltage (5 V) Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply High-side driver output 3; see PIN 4 High-side driver output 2; see PIN 4 Low-side driver output 2; see Pin 2 Ground; see Pin 1
Preliminary Information
Rev. A1, 12-Nov-01
3 (16)
Preliminary Information
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data transfer
CS
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
PL1
7
PH1
8
PL2
9
PH2
10
PL3
11
PH3
12
OLD
13
OCS
14
SI
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVL
INH
PSF
Input Data Protocol
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 PL1 PH1 PL2 PH2 PL3 PH3 OLD OCS SI Function Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Output LS1 additionally controlled by PWM Input Output HS1 additionally controlled by PWM Input See PL1 See PH1 See PL1 See PH1 Open load detection (low = on) Overcurrent shutdown (high = overcurrent shutdown is active) Software inhibit; low = stand by, high = normal operation (data transfer is not affected by stand by function because the digital part is still powered)
4 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Output Data Protocol
Output (Status) Register TP
Bit 0
Function Temperature prewarning: high = warning Normal operation: high = output is on, low = output is off Open load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Normal operation: high = output is on, low = output is off Open load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Overload detected: set high, when at least one output is switched off by a short circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch. (open-load detection bit OLD = high) Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation Power-supply fail: undervoltage at Pin VS detected
1
Status LS1
2
Status HS1
3 4 5 6 7 8 9 10 11 12
Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u.
13
OVL
14 15
INH PSF
After power-on reset, the input register has the following status
Bit 15 SI Bit 14 Bit 13 Bit 12 PH3 Bit 11 PL3 Bit 10 PH2 Bit 9 PL2 Bit 8 PH1 Bit 7 PL1 Bit 6 HS3 Bit 5 LS3 Bit 4 HS2 Bit 3 LS2 Bit 2 HS1 Bit 1 LS1 Bit 0 SRR
2&6
2/'
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Power-Supply Fail
In case of undervoltage at Pin VS the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. An undervoltage condition is only detected if it occurs over the undervoltage detection delay time tdUV. After the undervoltage occurred the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR bit in the input register. f the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detec-
Open-Load Detection
Preliminary Information
Rev. A1, 12-Nov-01
5 (16)
Preliminary Information
tion current IHS1-3, ILS1-3). If the current through a high-side or low-side switch in ON-state does not reach the open-load detection threshold, the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output.
Overtemperature Protection
If the junction temperature at one ore more switches exceeds the thermal prewarning threshold TjPW set, the temperature prewarning bit (TP) in the output register is set. When temperature falls below the thermal prewarning threshold TjPW reset, the Bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low the state of TP appears at Pin DO. After the C has read this information CS is set high and the data transfer is interrupted without affecting the state of input and output registers.
If the junction temperature at a switch exceeds the thermal shutdown threshold Tj switch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additional the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold Tjswitch on and writing a high to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
Short-Circuit Protection
The output currents are limited by a current regulator. If the overcurrent shutdown bit (OCS) in the input register is set, the affected output is switched off after a short delay time (tdSd) when the current exceeds the overcurrent limitation and shutdown threshold. In this case the overload detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. To inhibit the T6819 / T6829 the INH bit in the input register must be set to zero. In this case all output stages are turned off but the serial interface stays active. The current consumption is reduced to less than 10 A out of V S and less than 20 A out of VCC. The output stages can be activated again by bit SI = 1.
Inhibit
6 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Absolute Maximum Ratings
All values refer to GND pins
Parameter Supply voltage Supply voltage t<0.5s; IS>-2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Reverse conducting current (tpulse = 150 s) Junction-temperature range Storage-temperature range Pin 12 Pin 12 Pin 11 Pins 5to 8 Pin 10 Pins 5to 8 Pin 10 Pins 2 to 4 and 13 to 15 Pins 2 to 4 and 13 to 15 towards Pin 3 Symbol VVS VVS VVCC VCS,VDI, VCLK, VPWM VDO ICS,IDI, ICLK, IPWM IDO IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L TJ TSTG Value -0.3 to 40 -1 -0.3 to 7 -0.3 to VVCC+0.3 -0.3 to VVCC+0.3 -10 to +10 -10 to +10 Internal limited, see output specification 17 -40 to 150 -55 to 150 A C C Unit V V V V V mA mA
Thermal Resistance
Parameter T6819 Junction - pin Junction - ambient T6829 Junction - pin Junction - ambient Measured to heat slug, GND Pins 1, 9, 16 RthJP RthJA 5 30 K/W K/W Measured to GND Pins 1, 9, 16 RthJP RthJA 30 65 K/W K/W Test Conditions Symbol Value Unit
Operating Range
Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency PWM input frequency Junction-temperature range Note: 1. Threshold for undervoltage detection Symbol VVS VVCC VCS,VDI, VCLK, VPWM fCLK fPWM Tj Value VUV 1) to 40 4.75 to 5.25 -0.3 to VVCC 2 1 -40 to 150 Unit V V V MHz kHz C
Preliminary Information
Rev. A1, 12-Nov-01
7 (16)
Preliminary Information
Noise and Surge Immunity
Parameter Conducted interferences Interference suppression ESD (Human Body Model) ESD (Machine Model) ISO 7637-1 VDE 0879 Part 3 ESD S 5.1 JEDEC A115A Test Conditions Value Level 4 1) Level 6 2 kV 200 V
Electrical Characteristics
7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No. 1 1.1 1.2 Parameters Current Consumption Quiescent current (VS ) Quiescent current (VCC) VVS < 16 V, SI = low 4.75 V < VVCC < 5.25 V, SI = low VVS < 16 V normal operating, one output stage on, no load 4.75 V < VVCC < 5.25 V, normal operating 12 11 IVS IVCC 1 60 5 100 A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.3
Supply current (VS)
12
IVS
6
10
mA
A
1.4 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply current (VCC)
11
IVCC
350
600
A
A
Undervoltage Detection, Power-On Reset Power-on reset threshold Power-on reset delay time Undervoltagedetection threshold Undervoltagedetection hysteresis Undervoltagedetection delay time Thermal Prewarning and Shutdown Thermal prewarning Thermal prewarning Thermal prewarning hysteresis Thermal shutdown Thermal shutdown Thermal shutdown hysteresis TjPW set TjPW reset TjPW Tj switch off Tj switch on Tj switch off 150 135 120 105 145 130 15 175 160 15 200 185 170 155 C C K C C K B B B B B B After switching on VCC VCC = 5 V VCC = 5 V 12 12 11 VVCC tdPor VUv VUv tdUV 10 3.4 30 5.5 0.6 40 3.9 95 4.4 160 7.0 V s V V s A A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Electrical Characteristics
7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No. 3.7 Parameters Ratio thermal shutdown / thermal prewarning Ratio thermal shutdown / thermal prewarning Output Specification (OUT1-OUT3) On resistance On resistance Source output leakage current Sink output leakage current High-side switch reverse diode forward voltage Low-side switch reverse diode forward voltage Source overcurrent limitation and shutdown threshold Sink overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Source open load detection current Sink open load detection current Source output switch on delay 1) Sink output switch on delay 1) Source output switch off delay 1) Sink output switch off delay 1) Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off VVS = 13 V, RLoad=30 VVS = 13 V, RLoad =30 VVS =13V, RLoad = 30 VVS =13V, RLoad = 30 4, 13, 14 2, 3, 15 IOut = 1.5 A IOut = -1.5 A VOut1-3 = 0 V, output stages off VOut1-3 = VVS, output stages off IOut = 1.5 A 2, 3, 15 4, 13, 14 4, 13, 14 2, 3, 15 4, 13, 14 2, 3, 15 4, 13, 14 2, 3, 15 RDS On L RDS On H IOut1-3 IOut1-3 VOut1-3 -VVS -5 5 1 1 W W A A A A A A Test Conditions Pin Symbol Tj switch off / TjPW set Tj switch on / TjPW reset Min. 1.05 Typ. 1.2 Max. Unit Type* B
3.8 4 4.1 4.2 4.3 4.4
1.05
1.2
B
4.5
1.3
V
A
4.6
IOut = -1.5 A
VOut1-3
1.3
V
A
4.7
IOut1-3
-2.5
-2
-1.5
A
A
4.8
IOut1-3 tdSd IOut1-3
1.5
2
2.5
A
A
4.9
10
40
s
A
4.10
-4
-2
mA
A
4.11
IOut1-3 tdon tdon tdoff tdoff
2
4
mA
A
4.12 4.13 4.14 4.15
5 15 5 1
15 25 15 2
s s s s
A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Preliminary Information
Rev. A1, 12-Nov-01
9 (16)
Preliminary Information
Electrical Characteristics
7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins.
No. 4.16 5 5.1 5.2 5.3 5.4 5.5 5.6 6 6.1 6.2 Parameters Dead time between corresponding highand low-side switches Input voltage low evel threshold Input voltage highlevel threshold Hysteresis of input voltage Pull-down current Pins DI, CLK, PWM Pull-up current Pin CS Hysteresis of input voltage Serial Interface - Logic Output DO Output-voltage low level Output-voltage high level Leakage current (tristate) Inhibit Input - Timing Stand-by setup time Stand-by setup time tINHSethl tINHSetlh 100 100 s s A A IOL = 2mA IOL = -2mA VCS= VCC 0V < VDO < VVCC Pin 10 Pin 10 Pin 10 VDOL VDOH VVCC0.7V -10 10 0.4 V V A A VDI, VCLK, VPWM = VCC VCS = 0 V Test Conditions VVS=13V, RLoad = 30 Pin Symbol tdon -tdoff Min. 1 Typ. Max. Unit s Type* A
Logic Inputs DI, CLK, CS, PWM 5-8 5-8 5-7 6, 7,8 5 8 VIL VIH VI IPD IPU VI 50 10 -50 50 0.3 x VVCC 0.7 x VVCC 500 60 -10 700 V V mV A A mV A A A A A A
6.3 7 7.1 8.2 Note:
IDO
A
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. Device not in stand-by for t >1ms
10 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Serial Interface - Timing
Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No. 1 2 10 4 8 9 5 6 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Preliminary Information
Rev. A1, 12-Nov-01
11 (16)
Preliminary Information
Figure 4. Serial interface timing with chart number
1
2
CS
DO
9
CS
4
7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Application Circuit
Figure 5.
Vcc
U5021M Watchdog
Trigger
OUT3H 4
M
OUT2H 14
M
OUT1H 13 Charge pump
Reset
Fault detect
Fault detect
Fault detect
Vs
12
BYT41D
Vs
6 DI
V Batt
13 V
7 S I O C S O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R Control Input register 5 Output register Serial interface logic Power-on reset n. n. u. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1 UV protection 11 Vcc
CLK
CS
10 DO 16 PWM 8
Fault detect Fault detect Fault detect
GND
Thermal protection
9
GND
1 3 OUT3L OUT2L 15 OUT1L 2
GND
Vcc
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOutzx (see Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins.
Preliminary Information
Rev. A1, 12-Nov-01
+
C
P S F
I N H
O V L
n. u.
n. u.
+
Vcc
5V
13 (16)
Preliminary Information
Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
8
14 (16)
T6819 / T6829
Rev. A1, 12-Nov-01
T6819 / T6829
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
Preliminary Information
Rev. A1, 12-Nov-01
15 (16)
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(c) Atmel Germany GmbH 2001. Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel Germany GmbH's Terms and Conditions. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH's products are not authorized for use as critical components in life support devices or systems. Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com
Rev. A1, 12-Nov-01

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