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DATA SHEET
TDA8354Q Full bridge current driven vertical deflection output circuit in LVDMOS
Product specification Supersedes data of 1998 Sep 03 File under Integrated Circuits, IC02 2001 Jul 11
Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
FEATURES * Few external components required * High efficiency fully DC-coupled vertical output bridge circuit * Vertical flyback switch with short fall and rise times * Built-in guard circuit * Thermal protection circuit * Improved EMC performance due to differential inputs * A guard signal in zoom mode. GENERAL DESCRIPTION
TDA8354Q
The TDA8354Q is a power circuit for use in 90 and 110 colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of the absence of second breakdown.
QUICK REFERENCE DATA SYMBOL DC supply VP Vflb Iq(av) IVflb(av) Io(p-p) Ii(diff)(p-p) Io(Vflb) Tstg Tamb Tvj supply voltage flyback supply voltage average quiescent supply current average flyback supply current during scan during scan 7.5 - - - - t 1.5 ms - -55 -25 - 12 10 - - 500 - - - - 18 68 15 10 V V mA mA 2 x VP 45 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Vertical circuit output current (peak-to-peak value) input current (peak-to-peak value) at pin 11 or 12 3.2 600 1.6 +150 +85 150 A A A C C C
Flyback switch peak output current
Thermal data (in accordance with IEC 60747-1) storage temperature ambient temperature virtual junction temperature
ORDERING INFORMATION TYPE NUMBER TDA8354Q PACKAGE NAME DBS13P DESCRIPTION plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) VERSION SOT141-6
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
BLOCK DIAGRAM
TDA8354Q
handbook, full pagewidth
Vo(guard) VP(B) 1 GUARD CIRCUIT 4
VP(A) 10
Vflb 7
M1
D2
M2 Ii(diff) Ii(bias) Ii(diff) Ii(pos) 12 D3 9 M3 COMPENSATION 13 CIRCUIT 2
Vo(A) Ii(comp) Vi(M)
INPUT/ FEEDBACK
3 M4 Ii(neg) 11 5
Vi(con)
Ii(diff) Ii(bias) Ii(diff)
Vo(B)
M5
TDA8354Q
6 GNDB 8 GNDA
MGL461
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PINNING SYMBOL Vo(guard) Vi(M) Vi(con) VP(B) Vo(B) GNDB Vflb GNDA Vo(A) VP(A) Ii(neg) Ii(pos) Ii(comp) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION guard output voltage input measuring resistor input conversion resistor supply voltage B output voltage B ground B flyback supply voltage ground A output voltage A supply voltage A input power stage (negative); includes Ii(sb) signal bias input power stage (positive); includes Ii(sb) signal bias input for damping resistor compensation current FUNCTIONAL DESCRIPTION Vertical output stage
TDA8354Q
The vertical driver circuit has a bridge configuration, with the deflection coil connected between the complimentary driven output amplifiers. The differential input circuit is current driven, and is specially designed for direct connection to driver circuits delivering a differential current signal. However, it is also suitable for single-ended input signals. The current to voltage conversion is done by the external resistor (Rcon) connected between the output of the input conversion stage and output stage B. This voltage is compared with the output current through the deflection coil, measured as a voltage across RM, which provides internal feedback information. The relationship between the differential input current and the output current is defined by: 2 x Ii(diff) x Rcon = Icoil x RM The output current is determined by the value of Rcon and should measure 0.5 to 3.2 A (peak-to-peak value). The allowable input current range is 50 to 800 A for each input. Flyback supply
handbook, halfpage
Vo(guard) Vi(M) Vi(con) VP(B) Vo(B) GNDB Vflb GNDA Vo(A)
1 2 3 4 5 6
TDA8354Q
7 8 9
The flyback voltage is determined by an additional supply voltage Vflb. The principle of operating with two supply voltages (class G) makes it possible to optimize the supply voltage VP for the scan voltage and optimize the second supply voltage Vflb for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage Vflb is almost totally available as flyback voltage across the coil, because of the absence of a coupling capacitor (which is not necessary as a result of the bridge configuration). The very short rise and fall times of the flyback switch are >400 V/s. Protection The output circuit has protection circuits for: * Too high die temperature * Overvoltage of output stage A.
VP(A) 10 Ii(neg) 11 Ii(pos) 12 Ii(comp) 13
MGL462
The die has been glued to the metal block of the package. If the metal block is not insulated from the heat sink, the heat sink may only be connected directly to pin 6 and pin 8.
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
Guard circuit A guard circuit with output signal Vo(guard) is provided. The guard circuit generates an active HIGH level during the flyback period. The guard circuit is also activated for one or more of the following conditions: * When the thermal protection is activated (Tj 170 C) * During short circuit of the output pins (pins 5 and 9) to VP or ground * During open coil * During open loop * During short circuit of the input pins to VP or ground. An active HIGH level of the guard signal is also generated for the following conditions: * No drive signal * Short circuit of the coil. However, for these events, the signal is generated via an internal timer circuit. The guard signal set via this timer has a delay of 120 ms. The delay time is given by the lowest applicable field frequency. The guard signal can be used to blank the picture tube screen and signal a fault condition. The guard signal can also be used as a vertical synchronisation input pulse for an On Screen Display (OSD) microcontroller. Damping resistor compensation
TDA8354Q
For HF loop stability, a damping resistor is connected across the deflection coil. There is a large difference in current in the damping resistor Rp during scan and flyback. The resistor current is summed to the current in the deflection coil via the measuring resistor RM, which results in a too low current in the deflection coil at the start of the scan. To reach a short settling time, the difference in the current during scan and flyback in the damping resistor can be compensated by external means. For this purpose, a resistor (Rcomp) of about 1 M can be connected between the output of output stage A (pin 9) and pin 13 (Icomp). For a more accurate calculation of Rcomp, we have: ( V flb - V loss - V P ) x R p x R con R comp = -----------------------------------------------------------------------------( V flb - V loss - I L x R L ) x R M
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL DC supplies VP Vflb Io(p-p) Vo(A) Vo(B) I1,2,3,11,12,13 supply voltage flyback supply voltage - - - note 1 - - PARAMETER CONDITIONS
TDA8354Q
MIN.
MAX.
UNIT
18 68
V V
Vertical circuit output current (peak-to-peak value) output voltage output voltage current in or out of pins 1 to 3 and 11 to 13 3.2 68 VP +20 VP 1.6 +150 +85 150 A V V mA V
-20 -0.5 t 1.5 ms - -55 -25 note 2 - - - - -
V1,2,3,11,12,13 peak voltage on pins 1 to 3 and 11 to 13 Flyback switch Io(Vflb) Tstg Tamb Tvj tsc Ii/o VESD peak output current
A C C C hr mA mA V
Thermal data (in accordance with IEC 60747-1) storage temperature operating ambient temperature virtual junction temperature
Miscellaneous short-circuiting time current into any pin current out of any pin electrostatic handling machine model electrostatic handling human body model Notes 1. When the pin voltage exceeds 70 V, the device functions asa power Zener diode, and limits the voltage. 2. Internally limited by thermal protection; switching point 170 C. 3. Up to VP = 18 V. 4. Latch-up test at Tj(max). 5. Machine model: equivalent to discharging a 200 pF capacitor through a 0 series resistor. 6. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-c) Rth(j-a) PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient in free air CONDITIONS VALUE 4 40 UNIT K/W K/W note 3 1.5 x VP (ABSmax); note 4 note 5 note 6 1 +200 - 300
-1.5 x VP (ABSmax); note 4 -200
2000 V
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
TDA8354Q
CHARACTERISTICS VP = 12 V; Vflb = 45 V; fi = 50 Hz; Ii(bias) = 330 A; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL DC supplies VP Vflb Iq(av) Iq IVflb(av) Vloss operating supply voltage flyback supply voltage average quiescent supply current quiescent supply current average flyback supply current during scan no signal; no load during scan Io = +1.6 A; note 1 Io = -1.6 A; note 1 Io = +1.1 A; note 1 Io = -1.1 A; note 1 7.5 - - - - - - - - 10 60 - - - - - 18 68 15 80 10 V V mA mA mA 2 x VP - PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Output stages A and B total voltage loss from pin 10 to 9 and from pin 5 to 6 total voltage loss from pin 4 to 5 and from pin 9 to 8 total voltage loss from pin 10 to 9 and from pin 5 to 6 total voltage loss from pin 4 to 5 and from pin 9 to 8 LE linearity error adjacent blocks not adjacent blocks Vo Voffset output voltage swing (flyback) Vo(A) - Vo(B) offset voltage across RM Io = 3.2 A (p-p); note 2 Io = 3.2 A (p-p); note 2 Ii(diff) = 0.3 mA; Io = -1.6 A Ii(diff) = 0 Ii(bias) = 500 A Ii(bias) = 100 A Voffset(T) Vo(A), Vo(B) Gv(ol) fres Gi GcT PSRR Input stage Ii(sb) Ii(diff)(p-p) Vi(diff) Vi(cm) signal bias current differential mode input current (peak-to-peak value) pin 11 or 12 differential mode input voltage common mode input voltage note 7 Ii(diff) = 500 A Ii(bias) = 330 A - - - 0.95 330 500 0.75 1.15 500 600 - 1.35 A A V V offset voltage as a function of temperature DC output voltage open-loop voltage gain V9 to 5/V3 to 5 frequency response (-3 dB) current gain (Io/Ii(diff)) current gain drift as a function of temperature power supply rejection ratio note 6 Ii(diff) = 0 Ii(diff) = 0; note 3 notes 4 and 5 note 4 open loop - - - - - - - - - 80 - - - VP/2 60 0 1 8000 - 90 15 13 40 - - - - - 10-4 - /K dB mV mV V/K V dB dB kHz - - - 0.5 0.5 46 2 3 - % % V 6.0 4.8 4.2 3.4 V V V V
V3 to 5/V2 to 5 voltage ratio V3 to 5/V2 to 5
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
SYMBOL Flyback switch Iflb Vloss output peak current voltage loss (Vflb - Vo(A)) Io = 1.6 A Io = 1.1 A Guard circuit Io(guard) output current not active; Vo(guard) = 0 V Io(guard) = 100 A maximum leakage current = 10 A - - - t < 1.5 ms - PARAMETER CONDITIONS MIN.
TDA8354Q
TYP. - 8 7.5 - - 6 -
MAX. UNIT 1.6 9 8.5
A V V A mA V V
10 2.5 7 18
active; Vo(guard) = 4.5 V 1 Vo(guard) output voltage on pin 1 allowable voltage on pin 1 Notes 1. At Tj = 125 C, the temperature coefficient of the Vloss has a positive sign. 5 -
2. The linearity error is measured for a linear input signal without S correction and is based on the `on screen' measurement principle. This method is defined as follows. The output signal is divided into 22 successive equal time parts. The 1st and 22nd parts are ignored. The remaining 20 parts form 10 successive blocks k, where a block consists of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10, where Vk and Vk + 1 are the measured voltages of two successive blocks. Vmin, Vmax and Vav are the minimum, maximum and average voltages respectively. The linearity errors are defined as: V max - V min Vk - Vk + 1 LE = ------------------------- x 100% (adjacent blocks) and LE = ----------------------------- x 100% (non-adjacent blocks). V av V av 3. Vo(A) + Vo(B) = VP. At the start of the scan, this equation is one diode voltage less. 4. The V value within formulae relates to voltages at or between relative pin numbers, i.e. V9 to 5/V3 to 5 = voltage value across pins 9 and 5, divided by voltage value across pins 3 and 5. 5. V2 to 5 AC short circuited. 6. At Vripple = 500 mVeff at VP; measured across RM; fripple = 50 Hz to 1 kHz. 7. Ii(abs)(max) = 800 A and Ii(abs)(min) = 50 A per pin.
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
INTERNAL CIRCUITS Table 1 PIN 1 Equivalent pin circuits SYMBOL Vo(guard)
1 300
TDA8354Q
EQUIVALENT CIRCUIT
MGL472
2
Vi(M)
2
300
MGL465
3
Vi(con)
300
3
MGL466
4 5 6
VP(B) Vo(B) GNDB
4
5
6
MGL467
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PIN 7 8 9 10 Vflb GNDA Vo(A) VP(A)
9
TDA8354Q
SYMBOL
EQUIVALENT CIRCUIT
10
8 7
MGL471
11
Ii(neg)
300
11
MGL470
12
Ii(pos)
300
12
MGL469
13
Ii(comp)
300
13
MGL468
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
TEST AND APPLICATION INFORMATION
TDA8354Q
handbook, full pagewidth
VP Rguard Vo(guard) 1 GUARD CIRCUIT VP(B) 4 VP(A) 10 Vflb 7 C3 C4 Vflb
Ii(diff) Ii(bias) Ii(diff) Ii(bias) Ii(pos) 12
M1
D2
M2 D3 9 Vo(A) Rcomp COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M) Rp RL
M3 Ii(diff) Ii(diff) INPUT/ FEEDBACK
Rs RM
3 11 Ii(neg) Ii(bias) Ii(diff) Ii(bias) Ii(diff) M4
Vi(con)
Rcon
5 Vo(B)
M5
TDA8354Q
6 GNDB 8 GNDA
MGL463
RM = 0.5 ; Rcon = 1.2 k; RL = 3.2 ; Rp = 300 ; Rcomp = 650 k; R(guard) = 5 k; Rs = 2.2 k; C3 = C4 = 100 nF.
Fig.3 Test diagram.
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
TDA8354Q
handbook, full pagewidth
VP Rguard Vo(guard) 1 GUARD CIRCUIT VP(B) 4 VP(A) 10 Vflb 7 C3 C1 C4 C2 Vflb
M1
D2
Ii(diff) Ii(bias) Ii(diff) Ii(pos) C6 M3 DEFLECTION PROCESSOR 12 D3
M2 9 Vo(A) Rcomp COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M) Rp coil C*filter R*filter Rs RM
INPUT/ FEEDBACK
Ii(neg) C7
3 11 M4
Vi(con)
Rcon
5 Vo(B)
Ii(diff) Ii(bias) Ii(diff)
M5
TDA8354Q
6 GNDB 8 GNDA
MGL464
Coil: AT6216/42; VP = 12.1 V at fv = 50 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; VP = 12.8 V at fv = 100 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; Io(p-p) = 2.33 A (peak-to-peak value); Ii(bias) = 330 A; Ii(diff)(12-11) = 485 A (peak value); Vflb = 45 V; tflb = 0.6 ms.
RM = 0.5 ; Rcon = 1.2 k; Rp = 300 ; Rcomp = 650 k; R(guard) = 5 k; Rs = 2.2 k.
C1 = 47 F; 100 V; C2 = 220 F; 25 V; C3 = C4 = 100 nF; C6 = C7 = 10 nF; Cfilter = 47 nF*; Rfilter = 1.5 *. * Values depend on coil impedance.
Fig.4 Application diagram.
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
TDA8354Q
SOT141-6
non-concave x D Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c vM
1 Z e e1 bp wM
13 m e2
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT141-6 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A 17.0 15.5 A2 4.6 4.4 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 3.4 e1 1.7 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.25 x 0.03 Z (1) 2.00 1.45
ISSUE DATE 97-12-16 99-12-17
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA8354Q
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. suitable suitable(1) WAVE
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Philips Semiconductors
Product specification
Full bridge current driven vertical deflection output circuit in LVDMOS
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA8354Q
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
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SCA 72
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Printed in The Netherlands
753504/02/pp16
Date of release: 2001
Jul 11
Document order number:
9397 750 08034

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