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Preliminary Data Sheet TLE 6230 GP
Smart Octal Low-Side Switch
Features Product Summary * Short Circuit Protection VS Supply voltage * Overtemperature Protection Drain source clamping voltage VDS(AZ)max * Overvoltage Protection RON(max) * 16 bit Serial Data Input and Diagnos- On resistance (TJ = 25 C) tic Output (2 bit/ch. acc. SPI protocol) Output current (all outp.ON equal) ID(NOM) * Direct Parallel Control of Four Chan(individually) nels for PWM Applications (total max. all channels) * Parallel Inputs High or Low Active Programmable * General Fault Flag * Low Quiescent Current * Compatible with 3V Micro Controllers * Electostatic Discharge (ESD) Protection Application * C Compatible Power Switch for 12 V Applications * Switch for Automotive and Industrial System * Solenoids, Relays and Resistive Loads * Robotic Controls
4.5 - 5.5 V 55 V 1 500 mA 1 A 4 A
P-DSO 36-10
Ordering Code: Q67006-A9329 C702
General description Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and eight open drain DMOS output stages. The TLE 6230 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via an SPI Interface. Additionally four channels can be controlled direct in parallel for PWM applications. Therefore the TLE 6230 GP is particularly suitable for engine management and powertrain systems. Block Diagram
PRG
GND VS
RESET
VS
FAULT
VBB IN1 IN2 IN3 IN4
as Ch. 1
LOGIC
Protection Functions
as Ch. 1
Output Stage
as Ch. 1
OUT1
16 SCLK SI 8
1
4 8
OUT8
CS
SO
Serial Interface SPI
Output Control Buffer
GND
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Preliminary Data Sheet TLE 6230 GP
Detailed Block Diagram
RESET FAULT
VS
Channel 1
Normal function
GND VS
SCB/Overload Open load short to ground
PRG
IN1
& Output Stage
OUT1
IN2 IN3 IN4
& & &
Channel 2 Channel 3 Channel 4 Channel 5
OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
SO SI SCLK
SPI Interface 16 bit
Channel 6 Channel 7 Channel 8
CS
GND
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Preliminary Data Sheet TLE 6230 GP
Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol GND NC NC OUT1 OUT2 IN1 IN2 VS
RESET CS
Pin Configuration (Top view) Function Ground not connected not connected Power Output Channel 1 Power Output Channel 2 Input Channel 1 Input Channel 2 Supply Voltage Reset Chip Select Program (inputs high or low-active) Input Channel 3 Input Channel 4 Power Output Channel 3 Power Output Channel 4 not connected not connected Ground Ground not connected not connected Power Output Channel 5 Power Output Channel 6 not connected not connected General Fault Flag Serial Data Output Serial Clock Serial Data Input not connected not connected Power Output Channel 7 Power Output Channel 8 not connected not connected Ground
GND NC NC OUT1 OUT2 IN1 IN2 VS
RESET CS
PRG IN3 IN4 OUT3 OUT4 NC NC GND GND NC NC OUT5 OUT6 NC NC
FAULT
PRG IN3 IN4 OUT3 OUT4 NC NC GND
1* 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Power SO 36
36 GND 35 NC 34 NC 33 OUT8 32 OUT7 31 NC 30 NC 29 SI 28 SCLK 27 SO 26 FAULT 25 NC 24 NC 23 OUT6 22 OUT5 21 NC 20 NC 19 GND
SO SCLK SI NC NC OUT7 OUT8 NC NC GND
Heat Slug internally connected to ground pins
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Preliminary Data Sheet TLE 6230 GP Maximum Ratings for Tj = - 40C to 150C
Parameter Supply Voltage Continuous Drain Source Voltage (OUT1...OUT8) Input Voltage, All Inputs and Data Lines Load Dump Protection VLoad Dump = UP+US; UP=13.5 V With Automotive Relay Load RL = 70 RI1)=2 ; td=400ms; IN = low or high With RL= 24 RI=2 ; td=400ms; IN = high or low Operating Temperature Range Storage Temperature Range Output Current per Channel Output per Channel @ TA = 25C (All 8 Channels ON; Mounted on PCB ) 3) Output Clamping Energy ID = 0.5 A Power Dissipation (mounted on PCB) @ TA = 25C Electrostatic Discharge Voltage (Human Body Model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 DIN Humidity Category, DIN 40 040 IEC Climatic Category, DIN IEC 68-1 Thermal Resistance junction - case junction - ambient @ min. footprint junction - ambient @ 2.25 cm2 cooling area with heat pipes Symbol Values VS -0.3 ... +7 VDS 40 VIN - 0.3 ... + 7 2) VLoad Dump 80 52 Unit V V V V
Tj Tstg ID(lim) ID EAS Ptot VESD
- 40 ... + 150 - 55 ... + 150 self limited 500 50 3.3 2000
C A mA mJ W V
---
E 40/150/56 5 50 38
--K/W
RthJC RthJA
Minimum footprint PCB with heat pipes, 2 backside 2.25 cm cooling area
1) 2)
RI=internal resistance of the load dump test pulse generator LD200 VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839. 3) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 C the output current has to be calculated using RthJA according mounting conditions.
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Preliminary Data Sheet TLE 6230 GP Electrical Characteristics
Parameter and Conditions VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C (unless otherwise specified) 1. Power Supply Supply Voltage Supply Current (outputs ON) Supply Current (outputs OFF) 2. Power Outputs ON Resistance VS = 5 V; ID = 500 mA Output Clamping Voltage Current Limit Output Leakage Current Turn-On Time Turn-Off Time 3. Digital Inputs Input Low Voltage Input High Voltage Input Voltage Hysteresis Input Pull Down/Up Current (IN1 ... IN4) PRG, Reset Pull Up Current Input Pull Down Current (SI, SCLK) Input Pull Up Current ( CS ) 4. Digital Outputs (SO, FAULT ) SO High State Output Voltage SO Low State Output Voltage Output Tri-state Leakage Current CS FAULT Output Low Voltage 5. Diagnostic Functions Open Load Detection Voltage Output Pull Down Current Fault Delay Time Short to Ground Detection Voltage Short to Ground Detection Current Current Limitation; Overload Threshold Current Overtemperature Shutdown Threshold Hysteresis Symbol Values min typ Unit max
VS IS(ON) IS(OFF) TJ = 25C TJ = 150C
Output OFF
4.5 ----40 1 ----
-1 1 ---1.5 -8 6
5.5 2 2 1 1.8 55 2 10 12 10
V mA mA V A A s s
RDS(ON) VDS(AZ) ID(lim)
VReset = L ID = 0.5 A, resistive load ID = 0.5 A, resistive load
ID(lkg) tON tOFF VINL VINH VINHys IIN(1..4) IIN(PRG,Res) IIN(SI,SCLK) IIN(CS)
- 0.3 2.0 50 20 20 10 10
--100 50 50 20 20
1.0 --100 100 50 50 -0.4 10 0.4 -150 200 --150 2 200 --
V V mV A A A A V V A V V A s V A A C K
ISOH = 1 mA ISOL = 1.6 mA = H, 0 VSO VS IFAULT = 1.6 mA
VSOH VSOL ISOlkg VFAULTL VDS(OL) IPD(OL) td(fault) VDS(SHG) ISHG ID(lim) 1...8 Tth(sd) Thys
VS -1V ---10 --50 50 --50 1 170 --0 -3 90 100 2 -100 1.5 -10
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Preliminary Data Sheet TLE 6230 GP Electrical Characteristics cont.
Parameter and Conditions Symbol Values min typ max Unit
VS = 4.5 to 5.5 V ; Tj = - 40 C to + 150 C (unless otherwise specified)
6. SPI-Timing Serial Clock Frequency Serial Clock Period (1/fclk) Serial Clock High Time Serial Clock Low Time Enable Lead Time (falling edge of CS to rising edge of CLK)
fSCK
DC 200 50 50 250 250 ------250 250 --
-------25 25 ------50
5 -------50 50 50 50 ----
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tp(SCK) tSCKH tSCKL tlead
Enable Lag Time (falling edge of CLK to rising edge of CS ) tlag Data Setup Time (required time SI to falling of CLK) Data Hold Time (falling edge of CLK to SI) SO Rise Time (CL=200 pF) SO Fall Time (CL=200 pF) SI, CS , SCLK Rise Time (SPI inputs) SI, CS , SCLK Fall Time (SPI inputs) Enable Time Disable Time Data Valid Time
tSU tH trso tfso trSI tfSI tEN tDIS tvalid
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Preliminary Data Sheet TLE 6230 GP
Functional Description
The TLE 6230 GP is an octal-low-side power switch which provides a serial peripheral interface (SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage by an active zener clamp. The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO).
Circuit Description
Output Stage Control Each output is independently controlled by an output latch and a common reset line, which disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A logic high input data bit turns the respective output channel ON, a logic low data bit turns it OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial data input bits to the output buffer. Special conditions for Channel 1 to 4: In addition to the serial control of the outputs it is possible to control channel 1 to channel 4 directly in parallel for PWM applications. These inputs are high or low active (programmable via PRG pin) and ANDed with the SPI control bit. The table shows the AND-operation of the parallel input pin (here active high) and the corresponding SPI bit. For an application where the parallel input is always "ON", it is possible to switch the channel OFF via the SPI bit, e.g. for diagnosis in OFF-state. SPI Priority for OFF-state IN 1 - 4 0 0 1 1 SPI-Bit 0 - 3 0 1 0 1 OUT 1 - 4 OFF OFF OFF ON
Operation with parallel inputs: Set SPI bits to logic high. Operation via SPI: Connect parallel inputs to logic high (if programmed to active high).
PRG = High (VS): Parallel inputs Channel 1 to 4 are high active PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active. If the parallel input pins are not connected (independent of high or low activity) it is guaranteed that the channels 1 to 4 are switched OFF. PRG pin itself is internally pulled up when it is not connected.
PRG - Program pin.
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Preliminary Data Sheet TLE 6230 GP
Power Transistor Protection Functions Each of the eight output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A. The continuous current for each channel is 500 mA (all channels ON). Each output is protected by embedded protection functions. In the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). If this operation leads to an overtemperature condition, a second protection level (about 170 C) will change the output into a low duty cycle PWM (selective thermal shutdown with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6230 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the C and vice versa. CS High to Low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - SO changes from high impedance state to logic high or low state corresponding to the SO bits CS Low to High transition: - transfer of SI bits from shift register into output buf fers - reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS . When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6230 GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any transition. SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consists of two bytes - a "control byte" followed by a "data byte". The control byte contains the information as to whether the data byte will be accepted or ignored (see diagnostics section). The data byte contains the input information for the eight channels. A logic high level at this pin (within the data byte) will switch on the power switch, provided that the corresponding parallel input is also switched on (AND-operation for channel 1 to 4).
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Preliminary Data Sheet TLE 6230 GP
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK.
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Diagnostics
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
tion as soon as an error occurs for any one of the eight channels. This fault indication can be used to generate a C interrupt. Therefore a `diagnosis' interrupt routine need only be called after this fault indication. This saves processor time compared to a cyclic reading of the SO information. As soon as an error occurs, error information is latched into the diagnosis register. A new error will over-write the old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal, all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers.
Diagnostic Serial Data Out SO
15 14 13 12 11 10 9 8 - ----
Ch.8
Ch.7
Ch.6
Ch.5
HH HL LH LL
Normal function Overload, Shorted Load or Overtemperature Open Load Shorted to Ground
Figure 1: Two bits per channel diagnostic feedback There are two diagnostic bits per channel configured as shown in Figure 1. Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function. Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemperature condition. Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit combination is set. Short Circuit to GND: If the drain source voltage falls below 2 V (typ.), short to ground is detected by the LL bit combination. A definite distinction between open load and short to ground is guaranteed by design.
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Preliminary Data Sheet TLE 6230 GP
The standard way of obtaining diagnostic information is as follows: Clock in serial information into SI pin and wait approximately 150 s to allow the outputs tosettle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described in figure 1. By means of the control byte it is possible either to: a) control the eight outputs according to the data byte, as well as being able to read the diagnostic information or b) purely get diagnostic information without changing the state of the outputs. a) Serial Control of Outputs HHHHHHHH LHLHHLLL : Serial input information 14 244 14 244 4 3 4 3
Control Byte Data Byte
Control byte is set to FFhex: Data byte will be accepted. The outputs will be switched ON or OFF according to the information of the data byte. b) Diagnosis Only LLLLLLLL XXXXXXXX : Serial input information 14 24 3 14 244 4 4 4 3
Control Byte Data Byte
Control byte is set to 00hex: Data byte will be ignored. Diagnostic information can be read out at any time with no change of the switching conditions.
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Preliminary Data Sheet TLE 6230 GP Timing Diagrams
CS SCLK SI
C O N T R O L Byte 7 6 5 4 3 2 1 0
MSB
SO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LSB
0
Figure 2: Serial Interface
CS
0.2 VS tSCKH tlead
0.7VS 0.2VS
trSI
tlag
SCLK
tSU tSCKL tH
0.7VS 0.2VS
tfSI
SI
Figure 3: Input Timing Diagram
0.7 VS
CS
0.2 VS
SCLK tvalid
tEN SO
0.7 VS 0.2 VS
tDis
SO
SO
trSO
0.7 VS 0.2 VS
tfSO
Figure 4: SO Valid Time Waveforms
Enable and Disable Time Waveforms
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Preliminary Data Sheet TLE 6230 GP
VIN
t
VDS 80% 20%
tON
tOFF
t
Figure 5: Power Outputs
Application Circuits
VBB
VS = 5V
10k
PRG
VS OUT1
FAULT
RESET
OUT2
IN1
C e.g. C167 MTSR MRST CLK P xy
IN2 IN3 IN4
SI SO CLK CS
TLE 6230 GP
OUT8
GND
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Preliminary Data Sheet TLE 6230 GP Parallel SPI Configuration
Engine Management Application
TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16 can be controlled direct in parallel for PWM applications.
Injector 1
P x.1-4 4
4 PWM Channels
SI SO CLK CS
Injector 2 Injector 3 Injector 4
MTSR MRST CLK P x.y
CS
TLE 6220 GP Quad
4 P x.1-4
4 PWM Channels
C
C167
P x.y 8 P x.1-8 SI SO CLK
CS
TLE 6230 GP Octal
8 PWM Channels
SI SO CLK P x.y
CS
TLE 6240 GP 16-fold
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Preliminary Data Sheet TLE 6230 GP
Package and Ordering Code
(all dimensions in mm)
P-DSO 36-10
TLE 6230 GP
Ordering Code
Q67006-A9329 C702
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