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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
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High-Performance Floating-Point DSP - TMS320C32-60 (5 V) 33-ns Instruction Cycle Time 330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second (MIPS) - TMS320C32-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS - TMS320C32-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS 32-Bit High-Performance CPU 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations 32-Bit Instruction Word, 24-Bit Addresses Two 256 x 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks Flexible Boot-Program Loader On-Chip Memory-Mapped Peripherals: - One Serial Port - Two 32-Bit Timers - Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities Enhanced External Memory Interface That Supports 8- / 16- / 32-Bit-Wide External RAM for Data Access and Program Execution From 16- / 32-Bit-Wide External RAM TMS320C30 and TMS320C31 Object Code Compatible Fabricated using 0.7 m Enhanced Performance Implanted CMOS (EPICTM) Technology by Texas Instruments (TITM)
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144-Pin Plastic Quad Flat Package ( PCM Suffix ) 5 V Eight Extended-Precision Registers Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits Two Sets of Memory Strobes (STRB0 and STRB1) and One I / O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes) Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes
description
The TMS320C32 is the newest member of the TMS320C3x generation of digital signal processors ( DSPs) from Texas Instruments. The TMS320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-m triple-level-metal CMOS technology. The enhancements to the TMS320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible boot loader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
pin assignments
PCM PACKAGE ( TOP VIEW )
DV SS CV SS RESET PRGW R/W STRB1_B0 STRB1_B1 DV DD STRB1_B2 / A -2 V SSL STRB1_B3 / A -1 V DDL V DDL STRB0_B0 STRB0_B1 STRB0_B2 / A -2 STRB0_B3 / A -1 IOSTRB IV SS RDY DV DD HOLD
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144
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135
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DR0 DVDD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DVDD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL / MP CVSS DVSS A23 A22 A21 A20 A19 A18 DVDD A17 A16 A15 A14 A13 CVSS DVSS
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V SUBS NC
HOLDA CLKIN DV SS CV SS
NC INT3 INT2 INT1 INT0 IACK XF1 XF0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
H3 H1 D0 D1 D2 D3 DVDD D4 D5 D6 D7 D8 D9 VSSL VSSL DVSS CVSS D10 DVDD D11 IVSS D12 VDDL VDDL D13 D14 D15 D16 D17 DVDD D18 D19 D20 D21 DVSS CVSS
A12 DVDD
NC=No internal connection
2
A11 A10 A9 A8 A7 A6 DVDD A5 A4 A3 V DDL V DDL A2 CVSS DV SS A1 V SSL V SSL A0 DVDD D31 D30 D29 D28 D27 D26 IV SS D25 DVDD D24 D23 D22 NC
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
Pin Assignments
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 NAME DR0 DVDD FSR0 CLKR0 CLKX0 FSX0 DX0 IVSS SHZ TCLK0 TCLK1 DVDD EMU3 EMU0 VDDL VDDL EMU1 EMU2 VSSL MCBL / MP CVSS DVSS A23 A22 A21 A20 A19 A18 DVDD NUMBER 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 PIN NAME A17 A16 A15 A14 A13 CVSS DVSS NC A12 DVDD A11 A10 A9 A8 A7 A6 DVDD A5 A4 A3 VDDL VDDL A2 CVSS DVSS A1 VSSL VSSL A0 NUMBER 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 PIN NAME DVDD D31 D30 D29 D28 D27 D26 IVSS D25 DVDD D24 D23 D22 NC CVSS DVSS D21 D20 D19 D18 DVDD D17 D16 D15 D14 D13 VDDL VDDL D12 NUMBER 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 PIN NAME IVSS D11 DVDD D10 CVSS DVSS VSSL VSSL D9 D8 D7 D6 D5 D4 DVDD D3 D2 D1 D0 H1 H3 NC VSUBS CVSS DVSS CLKIN HOLDA HOLD DVDD NUMBER 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PIN NAME RDY IVSS IOSTRB STRB0_B3 / A-1 STRB0_B2 / A-2 STRB0_B1 STRB0_B0 VDDL VDDL STRB1_B3/ A-1 VSSL STRB1_B2/ A-2 DVDD STRB1_B1 STRB1_B0 R/W PRGW RESET CVSS DVSS XF0 XF1 IACK INT0 INT1 INT2 INT3 NC
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
pin functions
This section provides signal descriptions for the TMS320C32 device. The following table lists each signal, the number of pins, operating modes, and a brief signal description. The following table groups the signals according to their function. TMS320C32 Pin Functions
PIN NAME NO. EXTERNAL-BUS INTERFACE (70 PINS) A23 - A0 D31 - D0 R/W IOSTRB STRB0_B3 / A -1 STRB0_B2 / A -2 STRB0_B1 STRB0_B0 STRB1_B3 / A -1 STRB1_B2 / A -2 STRB1_B1 STRB1_B0 RDY 24 32 1 1 1 1 1 1 1 1 1 1 1 O/Z I/O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z I 24-bit address port of the external-bus interface 32-bit data port of the external-bus interface Read / write for external-memory interface. R / W is high when a read is performed and low when a write is performed over the parallel interface. External-peripheral I / O strobe for the external-memory interface External-memory access strobe 0, byte enable 3 for 32-bit external-memory interface, and address pin for 8-bit and 16-bit external-memory interface External-memory access strobe 0, byte enable 2 for 32-bit external-memory interface, and address pin for 8-bit external-memory interface External-memory access strobe 0, byte enable 1 for the external-memory interface External-memory access strobe 0, byte enable 0 for the external-memory interface External-memory access strobe 1, byte enable 3 for 32-bit external-memory interface, and address pin for 8-bit and 16-bit external-memory interface External-memory access strobe 1, byte enable 2 for 32-bit external-memory interface, and address pin for 8-bit external-memory interface External-memory access strobe 1, byte enable 1 for the external-memory interface External-memory access strobe 1, byte enable 0 for the external-memory interface Ready. RDY indicates that the external device is prepared for an externalmemory interface transaction to complete. Hold signal for external-memory interface. When HOLD is a logic low, any ongoing transaction is completed. A23 - A0, D31 - D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are placed in the high-impedance state, and all transactions over the external-memory interface are held until HOLD becomes a logic high or the NOHOLD bit of the STRB0 bus-control register is set. Hold acknowledge for external-memory interface. HOLDA is generated in response to a logic low on HOLD. HOLDA indicates that A23 - A0, D31 - D0, IOSTRB, STRB0_Bx, STRB1_Bx, and R / W are in the high-impedance state and that all transactions over the memory are held. HOLDA is high in response to a logic high of HOLD or when the NOHOLD bit of the external bus-control register is set. Program memory width select. When PRGW is a logic low, program is fetched as a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are performed to fetch a single 32-bit instruction word. The status of PRGW at device reset affects the reset value of the STRB0 and STRB1 bus-control register. S H R S S S S S S S S S S S S H H H H H H H H H H H H R R TYPE DESCRIPTION CONDITIONS WHEN SIGNAL IS IN HIGH Z
HOLD
1
I
HOLDA
1
O/Z
S
PRGW
1
I
A23 - A0 24 O/Z 24-bit address port of the external-bus interface I = input, O = output, Z = high-impedance state S = SHZ active, H = HOLD active, R = RESET active
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
TMS320C32 Pin Functions (Continued)
PIN NAME NO. CONTROL SIGNALS (9 PINS) RESET INT3 - INT0 IACK MCBL / MP XF1 - XF0 1 4 1 1 2 I I O/Z I I/O/Z Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. External interrupts Interrupt acknowledge. IACK is generated by the IACK instruction. This signal can be used to indicate the beginning or end of an interrupt-service routine. Microcomputer boot loader / microprocessor mode External flags. XF1 and XF0 are used as general-purpose I / Os or used to support interlocked-processor instructions. SERIAL PORT SIGNALS (6 PINS) CLKX0 DX0 FSX0 CLKR0 DR0 FSR0 1 1 1 1 1 1 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial-port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. Data-transmit output. Serial port 0 transmits serial data on DX0. Frame-synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data process over DX0. Serial-port 0 receive clock. CLKR0 is the serial-shift clock for the serial-port 0 receiver. Data receive. Serial port 0 receives serial data on DR0. Frame-synchronization pulse for receive. The FSR0 pulse initiates the receive-data process over DR0. TIMER SIGNALS (2 PINS) TCLK0 TCLK1 1 1 I/O/Z I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. CLOCK SIGNALS (3 PINS) CLKIN H1 H3 EMU0 - EMU2 EMU3 1 1 1 3 1 I O/Z O/Z I O/Z Input to the internal oscillator from an external clock source External H1 clock. H1 has a period equal to twice CLKIN. External H3 clock. H3 has a period equal to twice CLKIN. RESERVED (5 PINS) Reserved for emulation. Use 18 k - 22 k pullup resistors to 5 V. Reserved for emulation Shutdown high impedance. When active, SHZ shuts down the 'C32 and places all 3-state I/O pins in the high-impedance state. SHZ is used for board-level testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts 'C32 memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. S S S S S R R S S S S S S R R R R R R S R S TYPE DESCRIPTION CONDITIONS WHEN SIGNAL IS IN HIGH Z
SHZ
1
I
I = input, O = output, Z = high-impedance state S = SHZ active, H = HOLD active, R = RESET active
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
TMS320C32 Pin Functions (Continued)
PIN NAME NO. POWER / GROUND CVSS DVSS IVSS DVDD VDDL VSSL 7 7 4 12 8 6 I I I I I I Ground Ground Ground + 5-V dc supply + 5-V dc supply Ground TYPE DESCRIPTION CONDITIONS WHEN SIGNAL IS IN HIGH Z
VSUBS 1 I Substrate, tie to ground I = input, O = output, Z = high-impedance state S = SHZ active, H = HOLD active, R = RESET active Recommended decoupling capacitor is 0.1 F.
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
functional block diagram
32 32 IR PC 24 DDATA Bus RESET INT(3-0) IACK XF(1,0) H1 H3 MCBL / MP CLKIN VDD VSS SHZ EMU0-3 DADDR1 Bus PDATA Bus PADDR Bus
24
24
32
24
32
DADDR2 Bus Controller DMADATA Bus DMAADDR Bus
Multiplexer DMA Controller DMA Channel 0 Multiplexer CPU1 CPU2 REG1 REG2 CPU1 REG1 REG2 32 32 Multiplier 40 40 32-Bit Barrel Shifter ALU Global-Contol Register Source-Address Register Destination-Address Reg. Peripheral Address Bus Transfer-Counter Reg. DMA Channel 1 Global-Control Register Source-Address Register Destination-Address Reg. Transfer-Counter Reg. Peripheral Data Bus STRB0 STRB0 Control Reg. STRB1 STRB1 Control Reg. IOSTRB IOSTRB Control Reg.
Multiplexer
40 40 40 32
40 ExtendedPrecision Registers (R0-R7) 40
40
DISP0, IR0, IR1
ARAU0
BK
ARAU1
24 24 32 32 32 32 Other Registers (12) Auxiliary Registers (AR0 - AR7)
24 24 Timer 1 Global-Control Register Timer-Period Register Timer-Counter Register
32
32
operation
Operation of the TMS320C32 is identical to the TMS320C30 and TMS320C31 digital signal processors, with the exception of an enhanced external memory interface and the addition of two CPU power-management modes. external-memory interface The TMS320C32 has a configurable external-memory interface with a 24-bit address bus, a 32-bit data bus, and three independent multifunction strobes. The flexibility of this unique interface enables product designers to minimize external-memory chip count.
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EEEE EEEEE E EEEE E EEE EEEEE EEE
EEE
24 32 External Memory Interface Serial Port FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Serial PortControl Reg. Receive/Transmit (R/X)Timer Register Data-Transmit Register Data-Receive Register Timer 0 Global-Control Register Timer-Period Register Timer-Counter Register TCLK0 TCLK1
Program Cache (64 x 32)
RAM Block 0 (256 x 32)
RAM Block 1 (256 x 32)
Boot ROM
A23 - A0 D31 - D0 R/W RDY HOLD HOLDA PRGW
STRB0_B3/A-1 STRB0_B2/A-2 STRB0_B1 STRB0_B0 STRB1_B3/A-1 STRB1_B2/A-2 STRB1_B1 STRB1_B0 IOSTRB
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
external memory interface (continued) Up to three mutually exclusive memory areas (one program area and two data areas) can be implemented. Each memory area configuration is independent of the physical memory width and independent of the configuration of other memory areas. See Figure 1.
8-/16-/32-Bit Data in 8-/16-/32-Bit-Wide Memory 32-Bit Program in 16-/32-BitWide Memory 32-Bit CPU PRGW Pin STRB1
'C32
STRB0
8-/16-/32-Bit Data in 8-/16-/32-Bit-Wide Memory 32-Bit Program in 16-/32-BitWide Memory
StrobeControl Registers
Memory Interface IOSTRB
32-Bit Data in 32-Bit-Wide Memory 32-Bit Program in 32-BitWide Memory
Figure 1. 'C32 External Memory Interface The TMS320C32's external-memory configuration is controlled by a combination of hardware configuration and memory-mapped control registers and can be reconfigured dynamically. The signals that control external-memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows:
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The TMS320C32 is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The external-memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high, 32 bits if the PRGW signal is low. STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of external-memory addresses. When an address within one of these ranges is accessed by a read or write instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the TMS320C32 memory map, showing the address ranges for which the strobe signals become active.
The behavior of the STRB0 and STRB1 control signals is determined by the contents of the STRB0 and STRB1 control registers. The STRB0 and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or 32 bits) of the external-memory address ranges they control. Another field specifies the data width (8, 16, or 32 bits) of the data contained in those addresses. The values in these fields are not required to match. For example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four consecutive 8-bit locations, each having its own address. Each control-signal set has two pins (STRBx_B2/A-2 and STRBx_B3/A-1) that can act as either byte-enable (chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and STRBx_B1). The pin functions are determined by the physical memory width specified in the corresponding control register.
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TMS320C32 DIGITAL SIGNAL PROCESSOR
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external memory interface (continued)
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For 8-bit-wide physical memory, the STRBx_B2/A-2 and STRBx_B3/A-1 pins function as address pins (least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin. STRBx_B1 is unused. See Figure 2.
8-Bit Data Bus
8 8 Data A14 A13 A12 . . A1 A0 STRB0_B3/ A -1 STRB0_B2/ A -2 STRB0_B1 STRB0_B0 TMS320C32
A14 . . A3 A2 A1 A0 NC
Data Memory CS
Figure 2. 'C32 With 8-Bit-Wide External Memory
D
For 16-bit-wide physical memory, the STRBx_B3/A-1 pin functions as an address pin (least significant address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins. STRBx_B2/A-2 is unused. See Figure 3.
16-Bit Data Bus
16 8 Data TMS320C32 A14 A13 . . A2 A1 A0 STRB0_B3/ A -1 STRB0_B2 / A -2 STRB0_B1 STRB0_B0 8
A14 . . A3 A2 A1 A0 NC
Data Memory
CS
A14 . . A3 A2 A1 A0
Data Memory CS
Figure 3. 'C32 With 16-Bit-Wide External Memory
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TMS320C32 DIGITAL SIGNAL PROCESSOR
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external memory interface (continued)
D
For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins. See Figure 4.
32-Bit Data Bus
32 8 Data TMS320C32 8 8 8
Memory
Memory
A2 A1 A0
Memory
A2 A1 A0
CS
A2 A1 A0
CS
A2 A1 A0
CS
A2 A1 A0
CS
STRB0_B3/A -1 STRB0_B2/A -2 STRB0_B1 STRB0_B0
Figure 4. 'C32 With 32-Bit-Wide External Memory For more detailed information and examples see TMS320C32 Addendum to the TMS320C3x User's Guide (literature number SPRU132) and Interfacing Memory to the TMS320C32 DSP Application Report (literature number SPRA040).
D
The IOSTRB control signal, like STRB0 and STRB1, also is mapped to a specific range of addresses but it is a single signal that can access only 32-bit data from 32-bit-wide memory. Its range of addresses appears in the TMS320C32 memory map, shown in Figure 8. The IOSTRB bus timing is different from the STRB0 and STRB1 bus timings to accommodate slower I/O peripherals.
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Memory
A14 A13 . .
A14 A13 . .
Data
A14 A13 . .
Data
A14 A13 . .
Data
A14 A13 . .
Data
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
external memory interface (continued) examples Figure 5 and Figure 6 show examples of external memory configurations that can be implemented using the TMS320C32 external memory interface. The first example has a 32-bit-wide external memory with 8- and 16-bit data areas and a 32-bit program area.
32-Bit-Wide Memory 8-Bit Data 8-Bit Data 8-Bit Data 8-Bit Data
320C32 16-Bit Data
32-Bit Program 16-Bit Data
32
8
8
8
8
32-Bit-Wide Data Bus
Figure 5. 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit Program Memory Figure 6 shows a configuration that can be implemented with 16-bit external memory. The 32-bit data and program words can be stored and retrieved as half-words.
16-Bit-Wide Memory
8-Bit Data
8-Bit Data
320C32
32-Bit Program
16-Bit Data
16
8
8
16-Bit-Wide Data Bus
Figure 6. 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit Program Area
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TMS320C32 DIGITAL SIGNAL PROCESSOR
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external memory interface (continued) Figure 7 shows one possible configuration that can be implemented with 8-bit external memory. Program words, which are 32-bit, cannot be executed from 8-bit-wide memory.
8-Bit-Wide Memory
8-Bit Data 320C32 16-Bit Data
8
8
8-Bit-Wide Data Bus
Figure 7. 8-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas
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TMS320C32 DIGITAL SIGNAL PROCESSOR
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memory map
Figure 8 depicts the memory map for the TMS320C32. Refer to theTMS320C32 Addendum to the TMS320C3x User's Guide (literature number SPRU132) for a detailed description of this memory mapping, with shading to indicate external memory.
0h Reset-Vector Location 0h FFFh 1000h 1001h External Memory STRB0 Active (8.192M Words) 7FFFFFh 800000h Reserved (32K Words) 807FFFh 808000h 8097FFh 809800h Peripheral-Bus Memory-Mapped Registers (6K-Word Internal) Reserved (26K Words) 80FFFFh 810000h 80FFFFh 810000h 810001h 807FFFh 808000h 8097FFh 809800h 7FFFFFh 800000h Reserved (32K Words) Peripheral-Bus Memory-Mapped Registers (6K-Word Internal) Reserved (26K Words) Boot 2 External Memory STRB0 Active (8.188M Words) Reserved for Boot-Loader Operations Boot 1
External Memory IOSTRB Active (128K Words)
External Memory IOSTRB Active (128K Words)
82FFFFh 830000h 87FDFFh 87FE00h 87FEFFh 87FF00h 87FFFFh 880000h
Reserved (314.5K Words) RAM Block 0 (256-Word Internal) RAM Block 1 (256-Word Internal) External Memory STRB0 Active (512K Words)
82FFFFh 830000h 87FDFFh 87FE00h 87FEFFh 87FF00h 87FFFFh 880000h
Reserved (319.5K Words) RAM Block 0 (256-Word Internal) RAM Block 1 (256-Word Internal) External Memory STRB0 Active (512K Words) Boot 3
External Memory STRB1 Active (7.168M Words)
FFFFFFh
FFFFFFh
Microprocessor Mode
Figure 8. TMS320C32 Memory Map
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EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE
External Memory STRB1 Active (7.168M Words) Microcomputer/Boot-LoaderMode 13
EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE
8FFFFFh 900000h
8FFFFFh 900000h 900001h
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
power management The TMS320C32 CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2 mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN frequency divided by 16 (that is, TMS320C32 with a 32-MHz CLKIN frequency performs the same as a 2-MHz TMS320C32 with an instruction cycle time of 1000 ns (1 MHz). boot loader The TMS320C32 flexible boot loader loads programs from the serial port, EPROM, or other standard non-volatile memory device. The boot-loader functionality of the TMS320C32 is equivalent to that of the TMS320C31, and has added modes to handle the data-type sizes and memory widths supported by the external memory interface. The memory-boot load supports data transfers with and without handshaking. The handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and data-ready signals. peripherals The TMS320C32 peripherals are composed of one serial port, two timers, and two DMA channels. The serial port and timers are the functional equivalent of those in the TMS320C31 peripherals. The TMS320C32 two-channel DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA.
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
peripherals (continued) Figure 9 shows the TMS320C32's peripheral-bus control-register mapping, with the reserved areas shaded.
808000h 808004h 808006h 808008h 808009h 808010h 808014h 808016h 808018h 808020h 808024h 808028h 808030h 808034h 808038h 808040h 808042h 808043h 808044h 808045h 808046h 808048h 80804Ch 808050h 80805Fh 808060h 808064h 808068h 808069h 8097FFh
DMA 0 Global Control DMA 0 Source Address DMA 0 Destination Address DMA 0 Transfer Counter DMA 1 Global Control DMA 1 Source Address DMA 1 Destination Address DMA 1 Transfer Counter Timer 0 Global Control Timer 0 Counter Timer 0 Period Timer 1 Global Control Timer 1 Counter Timer 1 Period Register Serial Port Global Control FSX/DX/CLKX Port Control FSR/DR/CLKR Port Control R/X Timer Control R/X Timer Counter R/X Timer Period Data Transmit Data Receive Reserved IOSTRB-Bus Control STRB0-Bus Control STRB1-Bus Control Reserved Reserved
Figure 9. Peripheral-Bus Memory-Mapped Registers
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15
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
interrupts To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered. Unlike the fixed interrupt-trap vector-table location of the TMS320C30 and TMS320C31 devices, the TMS320C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a 256-word boundary. Figure 10 shows the interrupt and trap vector locations memory mapping with shading to indicate reserved areas. The reset vector is fixed to address 0h as shown in Figure 8.
EA (ITTP) + 00h EA (ITTP) + 01h EA (ITTP) + 02h EA (ITTP) + 03h EA (ITTP) + 04h EA (ITTP) + 05h EA (ITTP) + 06h EA (ITTP) + 07h EA (ITTP) + 08h EA (ITTP) + 09h EA (ITTP) + 0Ah EA (ITTP) + 0Bh EA (ITTP) + 0Ch EA (ITTP) + 0Dh Reserved EA (ITTP) + 1Fh EA (ITTP) + 20h TRAP0 . . . . EA (ITTP) + 3Bh EA (ITTP) + 3Ch EA (ITTP) + 3Dh EA (ITTP) + 3Eh EA (ITTP) + 3Fh TRAP27 TRAP28 TRAP29 TRAP30 TRAP31 Reserved Reserved INT0 INT1 INT2 INT3 XINT0 RINT0 Reserved Reserved TINT0 TINT1 DINT0 DINT1
Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
absolute maximum ratings over specified temperature ranges (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W Operating case temperature, TC (PCM (commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 85C (PCMA (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. This value calculated for the 'C32-40. Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external bus at the maximum rate possible. See normal (IDD) current specification in the electrical characteristics table and refer the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRU031).
recommended operating conditions (see Note 3)
MIN VDD VSS VIH VIL IOH IOL TC Supply voltage (DVDD, VDDL) Supply voltage (CVSS, VSSL, IVSS, DVSS, VSUBS) High-level High level input voltage Low-level input voltage High-level output current Low-level output current Operating case temperature (commercial) 0 - 40 CLKIN All other inputs 2.6 2 - 0.3 4.75 NOM 5 0 VDD + 0.3 VDD + 0.3 0.8 - 300 2 85 125 MAX 5.25 UNIT V V V V V A mA C C
Operating case temperature (extended) All nominal values are at VDD = 5 V, TA (ambient air temperature)= 25C. These values are derived from characterization and not tested. NOTE 3: All input and output voltage levels are TTL compatible.
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17
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
PARAMETER VOH VOL IOZ II High-level output voltage Low-level output voltage High-impedance state output current Input current fx = 40 MHz fx = 50 MHz fx = 60 MHz Standby CI Input capacitance All other inputs TEST CONDITIONS VDD = MIN, IOH = MAX VDD = MIN, IOL = MAX VDD = MAX VI = VSS to VDD TA = 25C, 25 C, VDD = MAX, fx = MAX IDLE2, CLKIN shut off MIN 2.4 - 20 - 10 160 200 225 50 15 20 NOM 3 0.3 0.6 20 10 390 425 475 A pF pF mA MAX UNIT V V A A
IDD
Supply current (see Note 4)
Co Output capacitance All nominal values are at VDD = 5 V, TA (ambient air temperature) = 25C. fx is the input clock frequency. VOL(max) = 0.7 V for A(0:23) Assured by design but not tested NOTE 4: Actual operating current is less than this maximum value (reference Note 2).
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin Electronics
VLoad CT
Output Under Test
IOH
Where: IOL IOH VLoad CT
= = = =
2 mA (all outputs) 300 A (all outputs) 2.15 V 80-pF typical load-circuit capacitance
Figure 11. Test Load Circuit
18
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
PARAMETER MEASUREMENT INFORMATION (CONTINUED) signal-transition levels for 'C32 (see Figure 12 and Figure 13)
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Output transition times are specified in the following paragraph. For a high-to-low transition on an output signal, the level at which the output is said to be no longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V ( see Figure 12 ).
2.4 V 2V 1V 0.6 V
Figure 12. 'C32 Output Levels Transition times for TTL-compatible inputs are specified as follows. For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.8 V and the level at which the input is said to be high is 2 V ( see Figure 13 ).
2V
0.8 V
Figure 13. 'C32 Input Levels
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameter symbology
Timing parameter symbols used in this document are in accordance with JEDEC Standard 100-A. Unless otherwise noted, in order to shorten the symbols, pin names and other related terminology have been abbreviated as follows: A23- A0 when the physical-memory-width-bit field of the STRBx control register is set to 32 bits A23- A0 and STRBx_B3/A-1 when the physical-memory-width-bit field of the STRBx control register is set to 16 bits A23- A0, STRBx_B3/A-1, and STRBx_B2/A-2 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits CLKIN D(31 - 0) H1, H3 IOSTRB tc(H) tc(CI) R/ W STRBx_B(3- 0) when the physical-memory-width-bit field of the STRBx control register is set to 32 bits STRBx_B(1- 0) when the physical-memory-width-bit field of the STRBx control register is set to 16 bits STRBx_B0 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits XF0 or XF1
A
CI D H IOS P Q RW S XF
RDY RDY
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
operating characteristics for CLKIN, H1 and H3 [Q = tc(CI)] (see Figure 14 and Figure 15)
NO. NO 1 2 3 4 5 6 7 8 9 9.1 tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL-HH) PARAMETERS Fall time, CLKIN Pulse duration, CLKIN low Pulse duration, CLKIN high Rise time, CLKIN Cycle time, CLKIN Fall time, H1 / H3 Pulse duration, H1 / H3 low Pulse duration, H1 / H3 high Rise time, H1 / H3 Delay time, H1 / H3 low to H1 / H3 high 0 50 Q-5 Q-6 3 4 606 0 40 25 Q = MIN Q = MIN 9 9 5 303 3 Q-5 Q-6 3 4 606 0 33.33 20 TEST CONDITIONS 'C32 - 40 MIN MAX 5 'C32 - 50 MIN 7 8 5 303 3 Q-4 Q-5 3 4 606 16.67 MAX 5 'C32 - 60 MIN 6 6 4 303 3 MAX 4 UNIT ns ns ns ns ns ns ns ns ns ns ns
10 tc(H) Cycle time, H1 / H3 The minimum CLKIN high pulse duration at 3.3 MHz is 10 ns. Assured by design but not tested 5 4 1 CLKIN
3 2
Figure 14. CLKIN Timing
10 9 H1 8 9.1 7 9.1 H3 8 9 7 10 6 6
Figure 15. H1 / H3 Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
NO. NO 11 12 13 14 15 16 17 18 19 20 21 22 td(H1L - SL) td(H1L - SH) td(H1H - RWL) td(H1L - A) tsu(D)R th(D)R tsu(RDY) th(RDY) td(H1H - RWH) tv(D)W th(D)W td(H1H - A) Delay time, H1 low to STRBx low Delay time, H1 low to STRBx high Delay time, H1 high to R / W low (read) Delay time, H1 low to A valid Setup time, D valid before H1 low (read) Hold time, D after H1 low (read) Setup time, RDY before H1 low Hold time, RDY after H1 low Delay time, H1 high to R / W high (write) Valid time, D after H1 low (write) Hold time, D after H1 high (write) Delay time, H1 high to A valid on back-to-back write cycles 0 11 'C32 - 40 MIN 0 0 0 0 13 0 21 0 11 17 0 9 MAX 11 11 11 11 'C32 - 50 MIN 0 0 0 0 10 0 19 0 9 14 0 8 MAX 9 9 9 9 'C32 - 60 MIN 0 0 0 0 10 0 17 0 8 12 MAX 7 7 8 7 UNIT ns ns ns ns ns ns ns ns ns ns ns ns
Assured from characterization but not tested
H3
H1 11 STRBx 12
R/W 14
15 13
A 16 D 18 RDY STRBx remains low during back-to-back operations. 17
Figure 16. Memory-Read-Cycle Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17) (continued)
H3
H1 11 STRBx 13 R/W 14 A 20 D 18 RDY 17 21 22 19 12
Figure 17. Memory-Write-Cycle Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
memory-read-cycle timing using IOSTRB (see Figure 18)
NO. NO 11.1 12.1 13.1 14.1 15.1 16.1 17.1 18.1 td(H3L-IOSL) td(H3L-IOSH) td(H1L-RWL) td(H1L-A) tsu(D)R th(D)R tsu(RDY) th(RDY) Delay time, H3 low to IOSTRB low Delay time, H3 low to IOSTRB high Delay time, H1 low to R / W high Delay time, H1 low to A valid Setup time, D before H1 high Hold time, D after H1 high Setup time, RDY before H1 high Hold time, RDY after H1 high 'C32 - 40 MIN 0 0 0 0 13 0 9 0 0 11 MAX 11 11 11 11 'C32 - 50 MIN 0 0 0 0 10 0 8 0 0 9 MAX 9 9 9 9 'C32 - 60 MIN 0 0 0 0 9 0 7 0 0 8 MAX 8 8 8 8 UNIT ns ns ns ns ns ns ns ns ns
23 td(H1L-RWH) Delay time, H1 low to R / W low Assured from characterization but not tested
H3
H1 11.1 IOSTRB 13.1 R/W 14.1 A 15.1 D 17.1 18.1 RDY 16.1 23 12.1
See Figure 19 and accompanying table.
Figure 18. Memory-Read-Cycle Timing Using IOSTRB
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
memory-write-cycle timing using IOSTRB (see Figure 19)
NO. NO 11.1 12.1 13.1 14.1 17.1 18.1 23 24 25 td(H3L-IOSL) td(H3L-IOSH) td(H1L-RWL) td(H1L-A) tsu(RDY) th(RDY) td(H1L-RWH) tv(D)W Delay time, H3 low to IOSTRB low Delay time, H3 low to IOSTRB high Delay time, H1 low to R / W high Delay time, H1 low to A valid Setup time, RDY before H1 high Hold time, RDY after H1 high Delay time, H1 low to R / W low Valid time, D after H1 high 0 'C32 - 40 MIN 0 0 0 0 9 0 0 11 17 0 MAX 11 11 11 11 'C32 - 50 MIN 0 0 0 0 8 0 0 9 14 0 MAX 9 9 9 9 'C32 - 60 MIN 0 0 0 0 7 0 0 8 12 MAX 8 8 8 8 UNIT ns ns ns ns ns ns ns ns ns
th(D)W Hold time, D after H1 low Assured from characterization but not tested
H3
H1 11.1 IOSTRB 23 R/W 14.1 A 24 D 17.1 18.1 RDY 25 13.1 12.1
See Figure 18 and accompanying table.
Figure 19. Memory-Write-Cycle Timing Using IOSTRB
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for XF0 and XF1 when executing LDFI or LDII (see Figure 20)
NO. NO 38 39 40 td(H3H-XF0L) tsu(XF1) th(XF1) Delay time, H3 high to XF0 low Setup time, XF1 before H1 low Hold time, XF1 after H1 low Fetch LDFI or LDII H3 9 0 'C32 - 40 MIN MAX 13 9 0 'C32 - 50 MIN MAX 12 8 0 'C32 - 60 MIN MAX 11 UNIT ns ns ns
Decode
Read
Execute
H1
STRBx
R/W
A
D
RDY 38 XF0 39 40 XF1
Figure 20. XF0 and XF1 When Executing LDFI or LDII
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for XF0 when executing STFI or STII (see Figure 21)
'C32 - 40 NO. MIN MAX 'C32 - 50 MIN MAX 'C32 - 60 MIN MAX UNIT
41 td(H3H-XF0H) Delay time, H3 high to XF0 high 13 12 11 ns XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of the store is driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from executing, the address of the store is not driven until the store can execute. Fetch STFI or STII H3
Decode
Read
Execute
H1
STRBx
R/W
A
D
RDY
41
XF0
Figure 21. XF0 When Executing a STFI or STII
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for XF0 and XF1 when executing SIGI (see Figure 22)
NO. NO 41.1 42 43 44 td(H3H-XF0L) td(H3H-XF0H) tsu(XF1) th(XF1) Delay time, H3 high to XF0 low Delay time, H3 high to XF0 high Setup time, XF1 before H1 low Hold time, XF1 after H1 low Fetch SIGI H3 9 0 'C32 - 40 MIN MAX 13 13 9 0 'C32 - 50 MIN MAX 12 12 8 0 'C32 - 60 MIN MAX 11 11 UNIT ns ns ns ns
Decode
Read
Execute
H1 43 XF0 44 XF1 41.1 42
Figure 22. XF0 and XF1 When Executing SIGI
timing for loading XF register when configured as an output pin (see Figure 23)
NO. NO 45 tv(H3H-XF) Valid time, H3 high to XF valid Fetch Load Instruction H3 'C32 - 40 MIN MAX 13 'C32 - 50 MIN MAX 12 'C32 - 60 MIN MAX 11 UNIT ns
Decode
Read
Execute
H1
OUTXF Bit
1 or 0 45
XFx OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 23. Loading XF Register When Configured as an Output Pin
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing of XF changing from output to input mode (see Figure 24)
NO. NO 46 47 th(H3H-XF01) tsu(XF) Hold time, XF after H3 high Setup time, XF before H1 low 9 0 'C32 - 40 MIN MAX 13 'C32 - 50 MIN 9 0 MAX 12 'C32 - 60 MIN 8 0 MAX 11 UNIT ns ns ns
48 th(XF) Hold time, XF after H1 low Assured from characterization but not tested Buffers Go from Ouput to Input
H3
Execute Load of IOF
Synchronizer Delay
Value on Pin Seen in IOF
H1 I / OXFx Bit 46 XFx Output 47 48
INXFx Bit
Data Sampled Data Seen
I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 24. Change of XF From Output to Input Mode
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing of XF changing from input to output mode (see Figure 25)
NO. NO 49 td(H3H-XFIO) Delay time, H3 high to XF switching from input to output Execution of Load of IOF H3 'C32 - 40 MIN MAX 17 'C32 - 50 MIN MAX 17 'C32 - 60 MIN MAX 15 UNIT ns
H1
I / OXFx Bit 49 XFx I / OXFx represents either bit 1 or bit 5 of the IOF register.
Figure 25. Change of XF From Input to Output Mode
30
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for RESET [Q = tc(CI)] (see Figure 26)
NO. NO 50 51 52 53 54 55 56 57 58.1 58.2 59 60 tsu(RESET) td(CLKINH-H1H) td(CLKINH-H1L) tsu(RESETH-H1L) td(CLKINH-H3L) td(CLKINH-H3H) tdis(H1H-D) tdis(H3HL-A) td(H3H-CONTROLH) td(H1H-RWH) td(H1H-IACKH) tdis(RESETL-ASYNCH) Setup time, RESET before CLKIN low Delay time, CLKIN high to H1 high Delay time, CLKIN high to H1 low Setup time, RESET high before H1 low and after ten H1 clock cycles Delay time, CLKIN high to H3 low Delay time, CLKIN high to H3 high Disable time, H1 low to D in the high-impedance state Disable time, H3 low to A in the high-impedance state Delay time, H3 high to control signals high Delay time, H1 low to R / W high Delay time, H1 high to IACK high Disable time, RESET low to asynchronous reset signals in the high-impedance state 'C32 - 40 MIN 10 2 2 9 2 2 12 12 13 9 9 9 9 21 MAX Q 12 12 'C32 - 50 MIN 10 2 2 7 2 2 10 10 12 8 8 8 8 17 MAX Q 10 10 'C32 - 60 MIN 7 2 2 6 2 2 10 10 11 7 7 7 7 14 MAX Q 10 10 UNIT ns ns ns ns ns ns ns ns ns ns ns ns
Assured by design but not tested Assured from characterization but not tested
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for RESET [Q = tc(CI)] (continued)
CLKIN RESET 50 51 H1 54 H3 10 H1 Clock Cycles 55 D 57 A 58.1 Control Signals 58.2 R/W 59 IACK Asynchronous Reset Signals # 60 56
52
53
RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The R / W output is placed in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 - 22 k, if undesirable spurious writes can occur when these outputs go low. In microprocessor mode (MCBL / MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode (MCBL / MP = 1), the reset vector is fetched two times, with no software wait states. Control signals include STRBx and IOSTRB. # Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx .
Figure 26. RESET Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for INT3 -INT0 interrupt response [P = tc(H)] (see Figure 27)
NO. NO 61 62.1 62.2 tsu(INT) tw(INT) Setup time, INT3-INT0 before H1 low Pulse duration of interrupt to assure only one interrupt seen for level-triggered interrupts 'C32 - 40 MIN 13 P P 2P MAX 'C32 - 50 MIN 10 P P 2P MAX 'C32 - 60 MIN 8 P P 2P MAX UNIT ns ns ns
tw(INT) Pulse duration of interrupt for edge-triggered interrupts Assured from characterization but not tested.
Reset or Interrupt Vector Read H3
Fetch First Instruction of Service Routine
H1 61 INT3 - INT0 Pin 62.1 INT3 - INT0 Flag 62.2 A Vector Address D First Instruction Address
Figure 27. INT3-INT0 Interrupt-Response Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for IACK (see Notes 5 and Figure 28)
NO NO. 63 64 td(H1H-IACKL) td(H1H-IACKH) Delay time, H1 high to IACK low Delay time, H1 high to IACK high 'C32 - 40 MIN MAX 9 9 'C32 - 50 MIN MAX 7 7 'C32 - 60 MIN MAX 6 6 UNIT ns ns
NOTES: 5. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states. Fetch IACK Instruction H3 Decode IACK Instruction IACK Data Read
H1 63 64 IACK
A
D
Figure 28. IACK Timing
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serial-port timing [P = tc(H)] (see Figure 29 and Figure 30)
NO. NO 65 66 td(H1-SCK) tc(SCK) (SCK) tw(SCK) (SCK) tr(SCK) tf(SCK) td(DX) tsu(DR) (DR) th(DR) td(FSX) tsu(FSR) (FSR) th(FS) tsu(FSX) (FSX) td(CH DX)V d(CH-DX)V td(FSX-DX)V td(DXZ) Delay time, H1 high to internal CLKX / R high/low Cycle time CLKX / R time, CLKX / R ext CLKX / R int CLKX / R ext CLKX / R int 2.6P 2P P + 10 [tc(SCK) / 2] - 5 [tC(SCK) / 2] + 5 7 7 CLKX ext CLKX int CLKR ext CLKR int CLKR ext CLKR int CLKX ext CLKX int CLKR ext CLKR int CLKX / R ext CLKX / R int CLKX ext CLKX int CLKX ext CLKX int 9 9 9 0 8 - P 21 - P [tc(SCK) / 2]-10 tc(SCK) / 2 30 18 30 17 9 21 9 0 27 15 7 7 7 0 8 - P 21 - P [tc(SCK) / 2]-10 tc(SCK) / 2 24 14 24 14 30 17 9 17 7 0 22 15 6 6 6 0 8 - P 21 - P [tc(SCK) / 2]-10 tc(SCK) / 2 20 12 20 12 (232)P
'C32 - 40
MIN
'C32 - 50 MAX
13 2.6P 2P P + 10 [tc(SCK) / 2] - 5 [tc(SCK) / 2] + 5 6 6 24 16 8 15 6 0 (232)P MIN
'C32 - 60 MAX
10 2.6P 2P P + 10 [tc(SCK) / 2] - 5 [tc(SCK) / 2] + 5 5 5 20 15 (232)P MIN
MAX
8
UNIT ns ns
67 68 69 70
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Pulse duration CLKX / R high / low duration, Rise time, CLKX / R Fall time, CLKX / R Delay time CLKX to DX valid time,
ns ns ns ns
71
Setup time DR before CLKR low time,
ns ns ns 20 14 ns
72
Hold time, DR from CLKR low time Delay time, CLKX to internal FSX y , high / low Setup time FSR before CLKR low time, Hold time, FSX / R input from CLKX / R , low Setup time, external FSX before , CLKX high Delay time, CLKX to first DX bit, FSX y , , precedes CLKX high
73
74
75
ns
ns
76
ns
SPRS027C - JANuARY 1995 - REVISED DECEMBER 1996
TMS320C32 DIGITAL SIGNAL PROCESSOR
77 78 79
ns ns ns
Delay time, FSX to first DX bit, CLKX precedes FSX Delay time, CLKX high to DX in the high-impedance state following last data bit
Assured from characterization but not tested
35
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
serial-port timing [P = tc(H)] (see Figure 29 and Figure 30) (continued)
65 H1 65 67 CLKX / R 69 77 DX DR Bit n-1 FSR 73 FSX(INT) FSX(EXT) 75 76 NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. 75 74 73 Bit n-2 68 72 Bit n-1 71 70 Bit n-2 Bit 0 79 67 66
Figure 29. Fixed Data-Rate-Mode Timing
CLKX / R
73
FSX(INT) 76 FSX(EXT) 77 DX
78
70 Bit n-1 75 Bit n-2 Bit n-3
79 Bit 0
FSR 74 DR 71 Bit n-1 72 Bit n-2 Bit n-3
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed data-rate mode.
Figure 30. Variable Data-Rate-Mode Timing
36
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for HOLD/HOLDA [P = tc(H)] (see Note 6 and Figure 31)
NO. NO 80 81 82 83 84 84.1 85 86 87 88 89 90 91 tsu(HOLD) tv(HOLDA) tw(HOLD) tw(HOLDA) td(H1L-SH)H td(H1H-IOS)H tdis(H1L-S) ten(H1L-S) tdis(H1L-RW) ten(H1L-RW) tdis(H1L-A) ten(H1L-A) tdis(H1H-D) Setup time, HOLD before H1 low Valid time, HOLDA after H1 low Pulse duration, HOLD low Pulse duration, HOLDA low Delay time, H1 low to STRBx high for a HOLD Delay time, H1 high to IOSTRB high for a HOLD Disable time, H1 low to STRBx or IOSTRB (in the high-impedance state) Enable time, H1 low to STRBx or IOSTRB active Disable time, H1 low to R/W in the high-impedance state Enable time, H1 low to R/W (active) Disable time, H1 low to A in the high-impedance state Enable time, H1 low to A valid Disable time, H1 high to D disabled in the high-impedance state 'C32 - 40 MIN 13 0 2P P - 5 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 10 13 9 MAX 9 'C32 - 50 MIN 10 0 2P P - 5 0 0 0 0 0 0 0 0 0 7 7 8 7 8 7 8 12 8 MAX 7 'C32 - 60 MIN 8 0 2P P - 5 0 0 0 0 0 0 0 0 0 6 6 7 6 7 6 7 11 7 MAX 6 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
Assured from characterization but not tested Not tested NOTE 6: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The NOHOLD bit of the primary-bit-control register overwrites the HOLD signal.
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for HOLD/HOLDA [P = tc(H)] (see Note 6 and Figure 31) (continued)
H3
H1 80 HOLD 80 82 81 83 HOLDA (see Note A) STRBx 84.1 IOSTRB 87 R/W 89 A 91 D Write Data 90 88 85 86 84 85 86 81
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.
Figure 31. HOLD / HOLDA Timing
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing of peripheral pin configured as general-purpose I/O (see Figure 32)
NO. NO 92 93 94 tsu(GPIOH1L) th(GPIOH1L) td(GPIOH1H) H3 H1 93 92 Peripheral Pin (see Note A) NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral. 94 94 Setup time, general-purpose input before H1 low Hold time, general-purpose input after H1 low Delay time, general-purpose output after H1 high 'C32 - 40 MIN 10 0 13 MAX 'C32 - 50 MIN 9 0 10 MAX 'C32 - 60 MIN 8 0 8 MAX UNIT ns ns ns
Figure 32. Peripheral-Pin General-Purpose I / O Timing
timing of peripheral pin changing from general-purpose output to input mode (see Figure 33)
NO NO. 95 96 97 th(H1H) tsu(GPI0H1L) th(GPIOH1L) Hold time, after H1 high Setup time, peripheral pin before H1 low Hold time, peripheral pin after H1 low Execute Store of Peripheral Control Register H3 10 0 'C32 - 40 MIN MAX 13 9 0 'C32 - 50 MIN MAX 12 8 0 'C32 - 60 MIN MAX 11 UNIT ns ns ns
Buffers Go From Output to Input
Synchronizer Delay
Value on Pin Seen in Peripheral Control Register
H1 I/O Control Bit 95 Peripheral Pin (see Note A) Output 96 97
Data Bit Data Sampled Data Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral.
Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input-Mode
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing of peripheral pin changing from general-purpose input to output mode (see Figure 34)
NO. NO 98 td(GPIOH1H) Delay time, H1 high to peripheral pin switching from input to output Execution of Store of Peripheral Control Register 'C32 - 40 MIN MAX 13 'C32 - 50 MIN MAX 10 'C32 - 60 MIN MAX 8 UNIT ns
H3
H1
I / O Control Bit
98 Peripheral Pin (see Note A) NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents of internal control registers associated with each peripheral.
Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input to Output Mode
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for timer pin [P = tc(H)] (see Figure 35)
NO. NO 99 100 101 102 103 tsu(TCLKH1L) th(TCLKH1L) td(TCLKH1H) tc(TCLK) (TCLK) tw(TCLK) (TCLK) Setup time, TCLK external before H1 low Hold time, TCLK external after H1 low Delay time, H1 high to TCLK internal valid Cycle time TCLK time, Pulse duration, TCLK high / low duration TCLK external TCLK internal TCLK external TCLK internal 2.6P 2P (232)P 'C32 - 40 MIN 10 0 9 MAX UNIT ns ns ns ns
P + 10 ns [tc(TCLK) / 2] - 5 [tc(TCLK) / 2]+5 Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. Assured by design but not tested NO. NO 99 100 101 102 103 tsu(TCLKH1L) th(TCLKH1L) td(TCLKH1H) tc(TCLK) (TCLK) tw(TCLK) (TCLK) Setup time, TCLK external before H1 low Hold time, TCLK external after H1 low Delay time, H1 high to TCLK internal valid Cycle time TCLK cycle time time, Pulse duration, TCLK high / low duration TCLK external TCLK internal TCLK external TCLK internal 2.6P 2P P + 10 (232)P 'C32 - 50 MIN 8 0 9 MAX UNIT ns ns ns ns
ns [tc(TCLK) / 2] - 5 [tc(TCLK) / 2]+5 Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. Assured by design but not tested NO. NO 99 100 101 102 103 tsu(TCLKH1L) th(TCLKH1L) td(TCLKH1H) tc(TCLK) (TCLK) tw(TCLK) (TCLK) Setup time, TCLK external before H1 low Hold time, TCLK external after H1 low Delay time, H1 high to TCLK internal valid Cycle time TCLK cycle time time, Pulse duration, TCLK high / low duration TCLK external TCLK internal TCLK external TCLK internal 2.6P 2P (232)P 'C32 - 60 MIN 6 0 8 MAX UNIT ns ns ns ns
P + 10 ns [tc(TCLK) / 2] - 5 [tc(TCLK) / 2]+5 Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. Assured by design but not tested H3 H1 100 99 TCLKx 103 102 101 101
Figure 35. Timing for Timer Pin
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41
TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
timing for SHZ pin [Q = tc(CI)] (see Figure 36)
'C32 - 50 NO. 104 tdis(SHZ) Disable time, SHZ low to all O, I/O pins in the high-impedance state Assured by characterization but not tested H3 MIN 0 MAX 2Q 'C32 - 60 MIN 0 MAX 2Q UNIT ns
H1
SHZ (see Note A) 104 All I/O Pins NOTE A: Enabling SHZ destroys 'C32 register and memory contents. Assert SHZ = 1 and reset the 'C32 to restore it to a known condition.
Figure 36. SHZ Pin Timing Table 1. Thermal Resistance Characteristics for PCM package
PARAMETER RJA RJC Junction-to-free-air Junction-to-case MIN MAX 39 10.0 UNIT C / W C / W
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TMS320C32 DIGITAL SIGNAL PROCESSOR
SPRS027C - JANUARY 1995 - REVISED DECEMBER 1996
MECHANICAL DATA
PCM(S-PQFP-G***)
144 PIN SHOWN
PLASTIC QUAD FLATPACK
108
73
109
72
0,38 0,22
0,13
M
0,65 TYP
NO. OF PINS*** 144 160
A 22,75 TYP 25,35 TYP
144
37 0,16 NOM
1 A 28,20 SQ 27,80 31,45 SQ 30,95
36
3,60 3,20
0,25 MIN
0- 7 1,03 0,73
Seating Plane 0,10 4,10 MAX (see Note C) 4040015/A-10/93 NOTES: A. B. C. D. E. F. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-022 The 144PCM is identical to 160PCM except that 4 leads per corner are removed. Foot length is measured from lead tip to a position on backside of lead 0,25 mm above seating plane (gage plane) Preliminary drawing
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43
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