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CMOS Highly Accurate : 2% Low Power Consumption : 0.7 A (VIN = 1.5V) Ultra small SSOT-24 (SC-82) Package
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General Description
The XC61C series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N channel open drain output configurations are available.
Applications Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors Features
Highly accurate : 2% Low power consumption : TYP 0.7 A [ VIN=1.5V ] Detect voltage range : 0.9V to 1.5V in 0.1V increments Operating voltage range : 0.7V to 6.0V Detect voltage temperature characteristics : TYP 100ppm/C Output configuration : N-channel open drain or CMOS Ultra small package : SSOT-24 (150mW) super mini-mold : SOT-23 (150mW) mini-mold : SOT-89 (500mW) mini-power mold Note : There are no products available with a set-up voltage accuracy of 1%.
Pin Configuration
VSS
4
Pin Assignment
PIN NUMBER SSOT-24 2 SOT-23 3 2 1 SOT-89 2 3 1 PIN NAME V IN VSS VOUT NC Supply Voltage Input Ground Output No Connection FUNCTION
NC
3
1
2
VOUT
VIN
4 1 3
S S OT-24(SC-82) (TOP VIEW )
V IN 3
1 V OUT
2 V SS
1 V OUT
S O T-2 3 (TO P V IE W )
2 3 V IN V SS S O T-8 9 (TO P V IE W )
Block Diagram (1) CMOS Output (2) Nch Open Drain Output
VIN
V IN VOUT
+ +
VO U T
' '
V ref VS S
V ref VSS
Absolute Maximum Ratings
Ta = 25 OC
PARAMETER Input Voltage Output Current Output Voltage CMOS Nch open drain SSOT-24 Power Dissipation SOT-23 SOT-89 Operating Ambient Temperature Storage Temperature
SYMBOL V IN IOUT VOUT
RATINGS 9 50
VSS -0.3 to VIN +0.3 VSS -0.3 to 9
UNITS V mA V
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150 Pd Topr Tstg 150 500 -40 to +85 -40 to +125
O
mW C C
O
Electrical Characteristics
V DF (T) = 0.9 to 1.5V 2% Ta = 25 OC
PARAMETER Detect Voltage Hysteresis Range
SYMBOL V DF V HYS
CONDITIONS
MIN VDF
x 0.98
TYP VDF VDF
x 0.05
MAX VDF
x 1.02
UNITS V V
CIRCUIT 1 1
VDF
x 0.02
VDF
x 0.08
Supply Current
ISS
Operating Voltage
V IN
Output Current
IOUT
Temperature Characteristics Delay Time (VDR VOUT inversion)
VDF Topr * VDF tDLY
VIN = 1.5V =2.0V =3.0V =4.0V =5.0V VDF(T) = 0.9V to 1.5V Nch VDS=0.5V VIN=0.7V =1.0V Pch VDS=2.1V VIN=6.0V ( with CMOS output ) -40 OC Topr 85OC
0.7 0.8 0.9 1.0 1.1 0.7 0.1 0.85 0.8 2.7 -7.5 100
2.3 2.7 3.0 3.2 3.6 6.0
A
2
V
1 3
mA -1.5 ppm/C 0.2 ms 4 5
Note : VDF (T) : Established Detect Voltage Value Release Voltage : VDR = VDF + VHYS
Functional Description ( CMOS output )
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1. When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with Nch open drain output configurations. ) 2. When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage (VSS) level. 3. When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output ( should output be pulled-up.) 4. When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS) level will be maintained. 5. When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. ( A condition of high impedance exists with Nch open drain output configurations. ) 6. The difference between VDR and VDF represents the hysteresis range.
Timing Chart
6
INPUT VOLTAGE (VIN ) DETECT RELEASE VOLTAGE(VDR) DETECT VOLTAGE(VDF)
MIN. OPERATING VOLTAGE(VMIN) GROUND VOLTAGE (VSS) OUTPUT VOLTAGE (VOUT)
GROUND VOLTAGE(VSS)
1
2
3
4
5
Ordering Information XC61C x x x x x x x a b cdef DESIGNATOR a DESCRIPTION Output Configuration : C = CMOS N = Nch open drain Detect Voltage : 09 = 0.9V 15 = 1.5V Output Delay : 0 = No delay Detect Accuracy : 2 = within 2.0% DESIGNATOR e DESCRIPTION Package Type : N = SSOT-24 ( SC-82 ) M = SOT-23 P = SOT-89 T = TO-92 Device Orientation : R = Embossed Tape ( Right ) L = Embossed Tape ( Left ) H = Paper Type ( TO-92) B = Bag ( TO-92 )
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b
c
f
d
Marking
SSOT-24(SC-82) (TOP VIEW)
SOT - 23 ( TOP VIEW )
SOT - 89 ( TOP VIEW )
x
Represents the integer of the Output Voltage and Detect Voltage N-Channel Open Drain Output (XC61CN series) DESIGNATOR CONFIGURATION VOLTAGE (V) 0.y K Nch L 1.y Nch
CMOS Output (XC61CC series) DESIGNATOR CONFIGURATION A CMOS B CMOS
VOLTAGE (V) 0.y 1.y
y
Represents the decimal point of the Detect Voltage VOLTAGE x.0 x.1 x.2 x.3 x.4 DESIGNATOR 5 6 7 8 9 VOLTAGE x.5 x.6 x.7 x.8 x.9
z
Based on internal standards ( SSOT-24 excepted )
DESIGNATOR 0 1 2 3 4
DESIGNATOR 3
{
Represents the assembly lot no. Based on internal standards
Measuring Circuits
Circuit 1
Circuit 2 A
VIN R VOUT VSS 100 k (Note 1)
VIN VSS VIN VOUT
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VIN
V
Circuit 3
Circuit 4
VIN
VIN
VIN
VIN
VDS
VOUT VSS
A
VDS
VOUT VSS
A
Circuit 5
100 k (Note 1)
VIN VOUT VSS
R
Waveform measurement
Note 1 : Not necessary with CMOS output products.
Notes on Use
1. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. ( refer to N.B. 1 - (1) below ) 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of Nch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. ( refer to N.B. 1 - (2) below ) 3. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. 4. In order to stabilise the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than several sec / V.
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N.B.
1. Oscillation (1) Output current oscillation with the CMOS output configuration When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow at RL. Because a voltage drop ( RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current Since the XC61C series are CMOS IC S, through current will flow when the IC's internal circuit switching operates ( during release and detect operations ). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current's resistor (RIN) during release voltage operations. ( refer to diagram 2 ) Since hysteresis exists during detect operations, oscillation is unlikely to occur.
Input
Input
XC61CC Series RIN RIN x IOUT voltage drop VIN VOUT
IOUT
RIN x ISS* voltage drop
RIN
XC61CC Series XC61CN Series
VIN
VOUT
VSS
VSS ISS* ( includes through current )
Electrical Characteristics
(1) SUPPLY CURRENT vs. INPUT VOLTAGE
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(2) DETECT, RELEASE VOLTAGE vs. AMBIENT TEMP.
(3) OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4) Nch DRIVER OUTPUT CURRENT vs. VDS
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(5) Nch DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE
(6) Pch DRIVER OUTPUT CURRENT vs. INPUT VOLTAGE

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