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CMOS Mini Mold Package Highly Accurate : 2% Built-In Delay Circuit (1ms to 50ms) (50ms to 200ms) (80ms to 400ms) Low Power Consumption : 1.0 A (VIN = 2.0V)
Applications Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors Delay circuitry Features
Highly Accurate : Detect voltage 2% Low Power Consumption : TYP 1.0 A [ VIN=2.0V ] Detect Voltage Range : 1.6V to 6.0V in 0.1V increments Operating Voltage Range : 0.7V to 10.0V Detect Voltage Temperature Characteristics : TYP 100ppm/ C
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General Description
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N channel open drain output configurations are available. Since the delay circuit is built-in, peripherals are unecessary and high density mounting is possible.
Built-In Delay Circuit : 1ms to 50ms, 50ms to 200ms, 80ms to 400ms Output Configuration : N-channel open drain or CMOS Ultra Small Packages : SOT-23 (150mW) mini-mold SOT-89 (500mW) mini-power mold
* No parts are available with an accuracy of 1%
Pin Configuration
V IN 3
Pin Assignment
PIN NUMBER SOT-23 3 2
1 V OUT 2 3 V IN V SS S O T -8 9 (T O P V IE W )
SOT-89 2 3 1
PIN NAME V IN V SS VOUT
FUNCTION Supply Voltage Input Ground Output
1 V OUT
2 V SS
1
S O T -2 3 (T O P V IE W )
Block Diagram
(1) CMOS output
Absolute Maximum Ratings
Ta = 25 OC
PARAMETER Input Voltage Output Current Output Voltage
CMOS Nch open drain SOT-23 SOT-89
SYMBOL VIN IOUT VOUT
Pd Topr Tstg
RATINGS 12 50 VSS -0.3 VIN +0.3 9 150 500 -30 -40 +80 +125 VSS -0.3
UNITS V mA V mW
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VIN
VOUT
D e lay C irc u it
Continuous Total Power Dissipation
V re f
Operating Ambient Temperature Storage Temperature
C C
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VS S
(2) N-channel open drain output
VIN VOUT
D e lay C i rc u it
Vref
VSS
Electrical Characteristics
Ta = 25 OC
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PARAMETER Detect Voltage Hysteresis Range
SYMBOL V DF VHYS
CONDITIONS
MIN VDF
x 0.98
TYP VDF VDF
x 0.05
MAX VDF
x 1.02
UNITS V V
CIRCUIT 1 1
VDF
x 0.02
VDF
x 0.08
Supply Current
ISS
Operating Voltage
V IN Nch
Output Current
IOUT Pch
VIN = 1.5V =2.0V =3.0V =4.0V =5.0V VDF=1.6V to 6.0V VDS=0.5V VIN=1.0V =2.0V =3.0V =4.0V =5.0V VDS=2.1V VIN=8.0V ( CMOS output )
0.9 1.0 1.3 1.6 2.0 0.7 2.2 7.7 10.1 11.5 13.0 -10.0 100
2.6 3.0 3.4 3.8 4.2 10.0
A
2
V
1
3 mA
4 ppm/C 200 ms 5
Detect Voltage Temperature Characteristics Transient Delay Time (VDR VOUT inversion)
VDF Topr * VDF tDLY *
VIN changes from 0.6V to 10V
50
V DF (T) : established detect voltage value Release Voltage : VDR = V DF + V HYS
* Transient Delay Time : 1ms to 50ms & 80ms to 400ms versions are also available. Note : The power consumption during power-start to output being stable (release operation) is 2 A greater than it is after that period (completion of release operation) because of delay circuit through current.
Torex Semiconductor Ltd.
Functional Description ( CMOS output )
1. When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN ), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN , output (VOUT) will be equal to the input at VIN. Note that high impedeance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage. 2. When V IN falls below VDF , VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-channel open drain configurations. 3. When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage. 4. When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level. 5. Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. 6. Following transient delay time, VIN will be output at VOUT . Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up. Notes : 1. 2. The difference between V DR and VDF represents the hysteresis range. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage DR has exceeded the V level.
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Timing Chart
Input Voltage (VIN)
6
Detect Release Voltage (VDR) Detect Voltage (VDF)
Minimum Operating Voltage(VMIN) Ground Voltage (VSS)
Output Voltage (VOUT)
Propagation Delay Time (tDLY)
Ground Voltage (VSS)
1
2
3
4
5
6
Ordering Information XC61F x xx x x x x a b cdef
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DESIGNATOR a
b
c
d
DESCRIPTION Output Configuration : C = CMOS N = Nch open drain Detect Voltage (VDF) : 25 = 2.5V 38 = 3.8V Output Delay : 1 = 50ms to 200ms 4 = 80ms to 400ms 5 = 1ms to 50ms Detect Accuracy : 2 = within 2.0%
DESIGNATOR e
DESCRIPTION Package Type : M = SOT-23 P = SOT-89
f
Device Orientation : R = Embossed Tape ( Right ) L = Embossed Tape ( Left )
Marking
xy z{
y x
{ z
SOT - 23 ( TOP VIEW )
SOT - 89 ( TOP VIEW )
x
Represents the integer of the Detect Voltage and the Output Configuration N-channel open drain (XC61FN series) DESIGNATOR CONFIGURATION VOLTAGE (V) Nch K 0.y Nch L 1.y Nch M 2.y Nch N 3.y Nch P 4.y Nch 5.y R 6.y Nch S
CMOS output (XC61FC series) DESIGNATOR CONFIGURATION CMOS A CMOS B CMOS C CMOS D CMOS E CMOS F CMOS H
VOLTAGE (V) 0.y 1.y 2.y 3.y 4.y 5.y 6.y
y
Represents the decimal point of the Detect Voltage
z
Indicates the presence of delay time
DESIGNATOR VOLTAGE (V) DESIGNATOR VOLTAGE (V) x.5 x.0 5 0 x.6 x.1 6 1 x.7 x.2 2 7 x.3 x.8 8 3 x.9 x.4 9 4
DESIGNATOR 5 6 7
DELAY TIME 50 to 200ms 80 to 400ms 1 to 50ms
{
Represents the assembly lot no. Based on internal standards
Measuring Circuits
Circuit 1
Circuit 2 A
VIN R VOUT VSS 100 k (Note 1)
VIN VSS VIN VOUT
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VIN
V
Circuit 3
Circuit 4
VIN
VIN
VIN
VIN
VDS VOUT
VOUT VSS
A
VDS
A
VSS
Circuit 5
100 k (Note 1)
VIN VOUT VSS
R
Waveform measurement
Note 1 : Not necessary with CMOS output products.
Notes on Use
1. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added. ( refer to N.B. 1 - (1) below ) 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of Nch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT ) does not exist. ( refer to N.B. 1 - (2) below ) 3. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. 4. If a resistor (RIN ) must be used, then please use with as small a level of input impedance as possible in order to control the occurences of oscillation as described above. Further, please ensure that RIN is less than 10k and that CIN is more than 0.1F (Diagram 1). In such cases, detect and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.
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N.B.
1. Oscillation (1) Oscillation as a result of output current with the CMOS output configuration : When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT ) will flow through RL. Because a voltage drop ( RIN x I OUT ) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the V IN pin. When the V IN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current : Since the XC61F series are CMOS IC S, through current will flow when the IC's internal circuit switching operates ( during release and detect operations ). Consequently, oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this through current ( Diagram 3 ). Since hysteresis exists during detect operations, oscillation is unlikely to occur.
R IN
X C 6 1F N S eries
R IN
XC 61 FC S eries
V IN VSS C IN
VOU
T
V IN V SS C IN
VOU
T
Diagram 1. When using an input resistor
XC61FC S eries XC61FN S eries
R IN R IN X IOU T Voltage drop
XC 61FC S eries
R IN X IOU T IOU T VIN VSS RL VOU T V oltag e drop
R IN
V IN V SS
VOU T
ISS *
(includes through current)
Diagram 2. Oscillation in relation to output current
Diagram 3. Oscillation in relation to through current
Electrical Characteristics
(1) Supply Current vs. Input Voltage
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(2) Detect Voltage, Release Voltage vs. Ambient Temperature
(3) Output Voltage vs. Input Voltage
(4) N-Channel Driver Output Current vs. VDS
(4) N-Channel Driver Output Current vs. VDS (contd.)
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(5) N-Channel Driver Output Current vs. Input Voltage
(6) P-Channel Driver Output Current vs. Input Voltage
(7) Ambient Temperature vs. Transient Delay Time

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