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IEEE 1394 1995 and P1394a Compliant General Purpose Link Layer Controller for Computer Peripherals and Consumer Audio/Video Electronics
TSB12LV32, TSB12LV32I
Data Manual
August 2003
Mixed-Signal Products
SLLS336B
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303, Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Contents
Contents
Section 1 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 TSB12LV32 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 TSB12LV32 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5.1 STAT0, STAT1, and STAT2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 TSB12LV32 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Configuration Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Version Register at 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Data-Mover Control Register at 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.3 Control Register at 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 Interrupt/Interrupt Mask Registers at 0Ch and 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.5 Cycle Timer Register at 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.6 Isochronous Port Register at 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.7 Maint_Control Register at 1Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.8 Diagnostic Register at 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.9 Phy Access Register at 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.10 Reserved Registers at 28h-2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.11 FIFO Status Register at 30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.12 Bus Reset Register at 34h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.13 Header0 Register at 38h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.14 Header1 Register at 3Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.15 Header2 Register at 40h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.16 Header3 Register at 44h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.17 Trailer Register at 48h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.18 Asynchronous Retry Register at 4Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 Microcontroller Byte Stack (Write) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Microcontroller Byte Unstack (Read) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 Microcontroller Interface Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1 Microcontroller Handshake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.2 Microcontroller Fixed-Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.3 Microcontroller ColdFire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.4 Microcontroller Critical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.5 Endian Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Link Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4 Cycle Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 Cycle Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 Received Packet Routing Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Contents
Data-Mover Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Data-Mover Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Isochronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Isochronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Asynchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Asynchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Data-Mover Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Isochronous Transmit With Automatic Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Isochronous Transmit Without Automatic Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Isochronous Packet Receive Without Header and Trailer Removal . . . . . . . . . . . . . . . . . . 5.2.4 Isochronous Packet Receive With Header and Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Asynchronous Packet Transmit With Automatic Header Insertion . . . . . . . . . . . . . . . . . . . 5.2.6 Asynchronous Packet Transmit Without Automatic Header Insertion . . . . . . . . . . . . . . . . 5.2.7 Asynchronous Packet Receive With Headers and Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.8 Asynchronous Packet Receive With Automatic Header and Trailer Removal . . . . . . . . . . 5.3 Data-Mover Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Data-Mover Endian Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Data-Mover Handshake Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Data-Mover Critical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIFO Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 ATF Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 ATF Burst Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 General-Receive FIFO (GRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 GRF Stored Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TSB12LV32 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Asynchronous Transmit/Receive (Microcontroller Interface/Data-Mover Port to/From TSB12LV32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 Quadlet Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Block Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Quadlet Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 Block Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Isochronous Transmit (Data-Mover Port to TSB12LV32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Isochronous Receive (TSB12LV32 to Microcontroller Interface/Data-Mover Port) . . . . . . 7.3 Phy Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Extended Phy Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Receive Self-ID Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSB12LV32/Phy Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 TSB12LV32 Service Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Status Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 TSB12LV32/Phy Interface Critical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . 9.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
45 47 47 49 51 52 54 55 56 57 58 59 60 61 62 62 62 63 63 65 65 65 66 67 67 69 69 69 70 71 73 74 75 76 77 79 83 83 84 87 88 89 91 93 93 93 94 95
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SLLS336B
August 2003
List of Illustrations
List of Illustrations
Figure Title Page
1-1 TSB12LV32 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3-1 Microcontroller Byte Stack (Write) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-2 Microcontroller Byte Unstack (Read) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3-3 Byte Handshake Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-4 Word Handshake Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-5 Byte Handshake Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3-6 Word Handshake Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3-7 Byte Fixed-Timing Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3-8 Word Fixed-Timing Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3-9 Byte Fixed-Timing Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3-10 Word Fixed-Timing Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-11 GRF Read Access (Byte Fixed-Timing Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3-12 GRF Read Access (Word Fixed-Timing Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3-13 ColdFire Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3-14 ColdFire Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-15 Microcontroller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3-16 Big Endian Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-17 Little Endian Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-18 Little-Endian Data-Invariance Illustration Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-19 Little-Endian Address-Invariance Illustration Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4-1 Link Core Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5-1 A Typical System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5-2 Isochronous Transmit DM Flow Control (TSB12LV32 Transmit to 1394 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . 46 5-3 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5-4 Asynchronous Transmit DM Flow Control (TSB12LV32 Transmit to 1394 Bus) (DMASYNC = 1) . . . . . . . . 47 5-5 Isochronous Receive With Auto Header and Trailer Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-6 Isochronous Receive With Header and Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-7 Isochronous Transmit With Auto Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5-8 Isochronous Transmit Without Auto Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5-9 Asynchronous Receive Without Header and Trailer Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5-10 Asynchronous Receive With Headers and Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5-11 Asynchronous Transmit With Auto Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5-12 Asynchronous Transmit Without Auto Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5-13 Isochronous Transmit With Auto Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5-14 Isochronous Transmit With Auto Header Insertion at 200 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5-15 Isochronous Transmit With Auto Header Insertion at 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5-16 Isochronous Transmit Without Auto Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5-17 Isochronous Receive With Automatic Header and Trailer Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5-18 Isochronous Receive With Header and Trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5-19 Isochronous Receive With Header and Trailer at 200 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5-20 Asynchronous Quadlet Transmit With Automatic Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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5-21 Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps . . . . . . . . . . . . . . . . . . . . . . . . 59 5-22 Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . . . . . . 59 5-23 Asynchronous Quadlet Transmit Without Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . 60 5-24 Asynchronous Block Transmit Without Automatic Header Insertion at 400 Mbps . . . . . . . . . . . . . . . . . . . . . 60 5-25 Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5-26 Asynchronous Block Receive With Headers and Trailer at 400 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5-27 Asynchronous Quadlet Receive With Automatic Header and Trailer Removal at 400 Mbps . . . . . . . . . . . . 62 5-28 Asynchronous Block Receive With Automatic Header and Trailer Removal at 400 Mbps . . . . . . . . . . . . . . 62 5-29 Endian Swapping in Byte Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5-30 Endian Swapping in Word Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5-31 Data-Mover Handshake Mode (GPLynx Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5-32 Clock-to-Output Timing With Respect to DMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6-1 TSB12LV32 Controller-FIFO-Access Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6-2 Asynchronous Packet With N Quadlets (ATF Loading Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7-1 Quadlet Transmit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7-2 Block Transmit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7-3 GRF Quadlet-Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7-4 Data-Mover Quadlet-Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7-5 GRF Block-Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7-6 Data-Mover Block-Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7-7 Isochronous Transmit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7-8 Data-Mover Isochronous Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7-9 GRF Isochronous Receive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7-10 Phy Configuration Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7-11 Receive Phy Configuration Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7-12 Ping Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-13 Remote Access Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-14 Remote Command Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7-15 Resume Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7-16 Receive Self-ID Packet Format (RXSID = 1, FULLSID = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-17 Receive Self-ID Packet Format (RXSID = 1, FULLSID = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-18 Phy Self-ID Packet #0 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-19 Phy Self-ID Packet #1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-20 Phy Self-ID Packet #2 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8-1 Phy-LLC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8-2 LREQ Request Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8-3 Status Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-4 Normal Packet Reception Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8-5 Null Packet Reception Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8-6 Normal Packet Transmission Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8-7 Critical Timing for the TSB12LV32/Phy Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Table Title Page
1-1 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1-2 STAT Terminal Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2-1 Configuration Register (CFR) Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-2 Header/Trailer Usage for CFRs 38th-48h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3-1 Microcontroller Interface Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-2 TSB12LV32 MP/MC Interface Terminal Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-3 Microcontroller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3-4 Endian Swapping Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4-1 Receiver Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5-1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5-2 CLK-to-Output Timing With Respect to DMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6-1 Packet Token Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7-1 Quadlet Transmit Format Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7-2 Block Transmit Format Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7-3 Quadlet Receive Format Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7-4 Block Receive Format Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7-5 Isochronous Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7-6 Isochronous Receive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7-7 Phy Configuration Packet Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7-8 Receive Phy Configuration Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7-9 Ping Packet Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-10 Remote Access Packet Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7-11 Remote Command Packet Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7-12 Resume Packet Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7-13 GRF Receive Self-ID Setup Using Control Register Bits (RXSID and FULLSID) . . . . . . . . . . . . . . . . . . . . . 79 7-14 Receive Self-ID Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-15 Phy Self-ID Packet Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8-1 CTL Encoding When the Phy Has Control of the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8-2 CTL Encoding When the TSB12LV32 Has Control of the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8-3 Request Stream Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-4 Request Type Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-5 Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-6 Bus Request Speed Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-7 Read Register Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8-8 Write Register Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8-9 Acceleration Control Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8-10 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-11 Receive Speed Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8-12 TSB12LV32/Phy Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
August 2003
SLLS336B
vii
List of Tables
viii
SLLS336B
August 2003
Overview
1
1.1
Overview
TSB12LV32 Description
The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC) with the capability of transferring data between the 1394 Phy-link interface, an external host controller, and an external device connected to the data-mover port (local bus interface). The 1394 Phy-link interface provides the connection to a 1394 physical layer device and is supported by the LLC. The LLC provides the control for transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via internal 2-Kbyte FIFOs at rates up to 400 Mbps. The TSB12LV32 transmits and receives correctly formatted 1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit requests to the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV32 is capable of being 1394 cycle master (CM), 1394 bus manager, 1394 isochronous resource manager (IRM) if additional control status registers (CSRs) are added via the external host controller, and supports reception of 1394 isochronous data on two channels and transmission of 1394 isochronous data on four channels. The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers by including programmable endian swapping. TSB12LV32 has a generic 16-/8-bit host bus interface which includes support for a ColdFireE microcontroller mode at rates up to 60 MHz. The microcontroller interface can operate in byte or word (16 bit) accesses. The data-mover block in GP2Lynx handles the external memory interface of large data blocks. This local bus interface can be configured either to transmit or receive data packets. The packets can be either asynchronous, isochronous, or asynchronous streaming data packets. The data-mover (DM) port can receive any type of packet, but it can only transmit one type of packet at a time: isochronous data packets, asynchronous data packets, or asynchronous stream data packets. The internal FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each of 520 quadlets (2 Kbytes). Asynchronous and/or isochronous receive packets can be routed to either the DM port or the GRF via the receiver routing control logic. Asynchronous data packets or asynchronous stream data packets can be transmitted from the DM port or the internal FIFO: ATF. If there is contention the ATF has priority and is transmitted first. Isochronous packets can only be transmitted by the data-mover port. The LLC also provides the capability to receive status information from the physical layer device and to access the physical layer control and status registers by the application software.
1.2
TSB12LV32 Features
* * * * * * * * * Compliant With IEEE 1394-1995 Standards and 1394a-2000 Supplement for High Performance Serial Bus Supports Transfer Rates of 400, 200, or 100 Mbps Compatible With Texas Instruments Physical Layer Controllers (Phys) Supports the Texas Instruments Bus Holder Galvanic Isolation Barrier Glueless Interface to 68000 and ColdFire Microcontrollers/Microprocessors Supports ColdFire Burst Transfers 2-Kbyte General Receive FIFO (GRF) Accessed Through Microcontroller Interface Supports Asynchronous and Isochronous Receive. 2-Kbyte Asynchronous Transmit FIFO (ATF) Accessed Through Microcontroller Interface Supports Asynchronous Transmissions. Programmable Microcontroller Interface With 8-Bit or 16-Bit Data Bus, Multiple Modes of Operation Including Burst Mode, and Clock Frequency to 60 MHz
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited. ColdFire is a trademark of Motorola, Inc.
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
1
Overview
* * * * * *
8-Bit or 16-Bit Data-Mover Port (DM Port) Supports Isochronous, Asynchronous, and Asynchronous Streaming Transmit/Receive From an Unbuffered Port at a Clock Frequency of 25 MHz. Backward Compatible With All TSB12LV31(GPLynx) Microcontroller and Data-Mover Functionality in Hardware Two-Channel Support for Isochronous Receive to Unbuffered 8/16 Data-Mover Port Four-Channel Support for Isochronous Transmit From Unbufferred 8/16 Bit Data-Mover Port Single 3.3-V Supply Operation With 5-V Tolerance Using 5-V Bias Terminals High Performance 100-Pin PZ Package
1.3
Functional Block Diagram
Microcontroller Interface 7 MA[0:6] Host Interface Byte Stacker 8-/16-to-32 Bits Data 32 CFR Status CTL[0:1] Packet Router Control Link Core ATF 32 D[0:7] LREQ LPS IRF 32 LinkOn Physical Layer Chip (PHY) 7 Address 7 Control
16 MD[0:15] MCA MCS MRW BCLK
32
FIFO
ATF
2K ATF 2K GRF 16 DMD[0:15] DataMover Port DMCLK DM Control Data Mover (DM) 32 32
GRF
ARF 32
DM IR/AR DM IT/AT
/2
SCLK
Figure 1-1. TSB12LV32 Functional Block Diagram
2
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Overview
1.4
Terminal Assignments
PZ PACKAGE (TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND MD0 MD1 MD2 MD3 VDD MD4 MD5 MD6 MD7 GND MD8 MD9 MD10 MD11 VDD5V MD12 MD13 MD14 MD15 VDD DIRECT GND DMREADY CYCLEIN
INT CYSTART TEA MCA GND BCLK MCS MWR RESET VDD5V MDINV COLDFIRE M8BIT/SIZ0 MCMODE/SIZ1 VDD TESTMODE MA6 MA5 MA4 VDD MA3 MA2 MA1 MA0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TSB12LV32
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LENDIAN LREQ GND SCLK VDD CTL0 CTL1 VDD D0 D1 CONTNDR LINKON D2 D3 D4 D5 D6 D7 GND STAT2 STAT1 STAT0 LPS DMERROR PKTFLAG
DMD0 DMD1 DMD2 DMD3 GND DMD4 DMD5 DMD6 DMD7 VDD5V DMD8 DMD9 DMD10 DMD11 VDD DMD12 DMD13 DMD14 DMD15 GND DMCLK VDD DMPRE DMRW DMDONE
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
3
Overview
1.5
Terminal Functions
The terminal functions are described in Table 1-1. No input terminals or I/O terminals should be left floating; unless otherwise specified, connect any unused input terminals or I/O terminals to ground using 1-k resistors. Table 1-1. Terminal Functions
TERMINAL NAME NO. 6 12 75 I/O DESCRIPTION Microcontroller/Microprocessor Interface
BCLK COLDFIRE LENDIAN
I I I
Microcontroller interface clock. Maximum frequency is 60 MHz. In the ColdFire mode, BCLK is the same as CLK, which is the clock-input signal to the ColdFire. ColdFire mode. To operate in this mode, COLDFIRE must be asserted high. Little-endian mode for the microcontroller interface. When this terminal is pulled up, the data on MD0-MD15 is byte-swapped to little endian byte format before it is written to the CFR or FIFO and after it is read from the CFR or FIFO. Microcontroller address bus. MA0 is the most significant bit (MSB) of these 7 bits. Configuration bit for microcontroller interface. If the microcontroller interface is 8 bits wide, this terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal represents burst SIZ0. Mode bit for microcontroller interface. If the microcontroller interface is used in a handshake mode, this terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal represents burst SIZ1. Microcontroller interface cycle acknowledge. When asserted low, MCA signals an acknowledge of the microcontroller cycle from the TSB12LV32. Microcontroller interface cycle start. When asserted low, MCS signals the beginning of a microcontroller operation to the TSB12LV32. Microcontroller interface data invariant mode. This terminal is meaningful only when LENDIAN (75) is high. When asserted high, the microcontroller interface operates in the data invariant mode. When low, the microcontroller interface operates in address invariant mode. Microcontroller interface bidirectional data bus. MD0 is the most significant bit. However, byte significance is dependent on the state of the LENDIAN and MDINV terminals.
MA[0:6] M8BIT/SIZ0 MCMODE/SIZ1 MCA MCS MDINV
24-21 19-17 13 14 4 7 11
I I I O I I
MD[0:15]
99-96 94-91 89-86 84-81 8 3
I/O
MWR TEA
I O
Microcontroller read/write indicator. When driven high, MWR indicates a read access from the TSB12LV32. When driven low, MWR indicates a write access to the TSB12LV32. Transfer error acknowledge. This active-low signal is asserted low for one BCLK cycle whenever there is an illegal transfer request by the microcontroller (i.e., requested data transfer size is unsupported or MCS is asserted low for more than one BCLK cycle in ColdFire mode). Data-Mover Port Interface Data-mover (DM) bidirectional data port. DMD0 is the MSB of these 16 bits.
DMD[0:15]
26-29 31-34 36-39 41-44 46 50
I/O
DMCLK DMDONE
O O
Data-mover clock at (SCLK/2) MHz Data mover done. For transmit, this signal is activated when the internal packet counter counts down to zero from the value loaded into the PACKET PER BLOCK field in the CFR @ 04h. For receive, this terminal pulses for one DMCLK prior to the first byte/word available to the DM interface. Data-mover error. DMERROR is asserted high when there is an error in the received packet or an illegal transmit speed was attempted. Data-mover predata indicator. In transmit mode, DMPRE pulses for one DMCLK prior to accepting the first quadlet on the DM port. In isochronous receive mode, DMPRE pulses for one DMCLK when the sync bit in the header matches a bit set in the isochronous port CFR at 18h. DMPRE is not used in asynchronous receive mode. Data mover ready. Must be asserted high by the external logic controlling the DM interface when data is ready for transmit. DMREADY must be set low when the data mover is in receive mode. DMREADY cannot be used to throttle the data rate through the data-mover port; see Section 5 for more information.
DMERROR DMPRE
52 48
O O
DMREADY
77
I
4
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Overview
Table 1-1. Terminal Functions (Continued)
TERMINAL NAME DMRW NO. 49 I/O DESCRIPTION Data-Mover Port Interface (Continued) O Data-mover read/write indicator. When data is being moved from 1394 to the DM port (receive) this signal goes high to indicate data is available on DMD[0:15]. When data is being moved from DM to 1394 bus (transmit) this signal goes high to indicate that data must be supplied to the DMD[0:15] port for transmission. Packet flag. PKTFLAG is asserted high to indicate the first (header) or last (trailer) quadlet of a received packet on the DM interface. PKTFLAG is not valid in transmit mode. The PKTFLAG signal is not valid when the header/trailer extraction option is selected. Phy/Link Interface CTL[0:1] D[0:7] LINKON 70, 69 67, 66, 63-58 64 I/O I/O I Phy-link interface control lines Phy-link interface data lines. Data is only expected on D0 and D1 at 100 Mbps, D0-D3 at 200 Mbps, and D0-D7 at 400 Mbps. D0 is the MSB bit. Link-on from the Phy is a 4 MHz - 8 MHz clock. This signal is activated when the link is inactive and the Phy has detected a link-on packet or a Phy interrupt. This clock persists for no more than 500 ns. When the link detects this terminal as active, it turns on and drives LPS. Link power status. LPS is used to drive the LPS input of the Phy. It indicates to the Phy that the link is powered up and active. LPS toggles at a rate = 1/16 of BCLK by default (see CFR at 08h for more information). Link request to Phy. LREQ makes bus requests and register access requests to the Phy. System clock. SCLK is a 49.152-MHz clock supplied by the Phy. DMCLK is generated from SCLK. SCLK can also be used as the source for BCLK. Miscellaneous Functions CONTNDR 65 I/O Contender. When asserted high, this terminal tells the link that this node is a contender for isochronous resource manager (IRM) or bus manager functions. The state of CONTNDR must match the state of the Phy contender terminal for 1394-1995 compliant Phys, and the Phy register bit for 1394a-2000 compliant Phys. This terminal defaults to being an input on power up. After power up, the value of this terminal can be driven internally by the CTNDRSTAT bit (bit 12 at 08h). Additional CSRs must be implemented in software for the device to support IRM functionality. Cycle in. This input is an optional external 8-kHz clock used as the isochronous cycle clock. It only is used if attached to the cycle-master node. It is enabled by the cycle source bit and should be tied high when not used. Isochronous cycle start indicator. CYSTART signals the beginning of an isochronous cycle by pulsing for one DMCLK period. Isolation terminal. When this terminal is asserted high, no isolation is present between the TSB12LV32 and the Phy. When low, TI bus holder isolation is active. Ground reference
PKTFLAG
51
O
LPS
53
O
LREQ SCLK
74 72
O I
CYCLEIN
76
I
CYSTART DIRECT GND
2 79 5, 25, 30, 45, 57, 73, 78, 90, 100 1 9 54-56 16 10, 35, 85
O I
INT RESET STAT[0:2] TESTMODE VDD5V
O I O I
Interrupt. NOR of all internal interrupts. System reset. This active low signal is asynchronous to the TSB12LV32. General status outputs. STATn is the output signal selected with the CFR at address 20h. This terminal is used to place the TSB12LV32 in the test mode (for TI internal use only). In normal operation, this terminal must be tied to ground. 5 V ( 0.5V) supply voltage for 5-V tolerant inputs. Only the Phy/link interface of the TSB12LV32 is not 5-V tolerant. Tie this terminal to the 3.3-V supply voltage if the TSB12LV32 is not connected to any devices driving 5-V signals. Tie this terminal to the 5-V supply voltage if the TSB12LV32 is connected to any devices driving 5-V signals. This terminal is only used to make inputs 5-V tolerant, it is not used for any outputs. 3.3 V ( 0.3 V) supply voltage
VDD
15, 20, 40, 47, 68, 71, 80, 95
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
5
Overview
1.5.1 STAT0, STAT1, and STAT2 Programming
The STAT0, STAT1, and STAT2 terminals can be independently programmed to show one of fourteen possible internal hardware status signals. The controls for the STAT terminals are in the Diagnostic register at address 20h of the CFR register. STAT0 is controlled by STATSEL0 (bits 16-19), STAT1 is controlled by bits STATSEL1 (bits 20-23), and STAT2 is controlled by STATSEL2 (bits 24-27). See Table 1-2 for programming the STAT terminals. Table 1-2. STAT Terminal Programming
STATSEL0, STATSEL1, OR STATSEL2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STAT0/STAT1/STAT2 Reserved ATFFULL Bus reset (PHYRST) Arbitration reset gap CYCLEOUT RXDMPKT RXGRFPKT BX_BUSY SUBGP CYCLE_DONE ATSTARTED (default setting for STAT1) DMACKERR DMEN GRFEMPTY (default setting for STAT2) Reserved Reserved Reserved Indicates that the ATF is full. Bit 12 in the FIFO status CFR at 30h. 1394 bus reset. Bit 3 in the Interrupt CFR at 0Ch. The 1394 bus has been idle for an arbitration reset gap. Bit 26 in the interrupt CFR at 0Ch. Cycle out. The LLC clock. It is based on the timer controls and the received cycle-start messages. Packet received to DM interrupt. Activated at the end of a received packet. Bit 9 in the interrupt CFR at 0Ch. Packet received to GRF interrupt. Activated at the end of a received packet. Bit 6 in the interrupt CFR at 0Ch. Byte busy. This represents the OR of bits 0-3 of the diagnostic CFR at 20h. Subaction gap. Activated upon detection of a subaction gap. Bit 27 in the interrupt CFR at 0Ch. Cycle done. Indicates the end of the isochronous period. This happens when a subaction gap has been detected. Bit 22 in the interrupt CFR at 0Ch. Activated when an asynchronous packet transfer has started from the ATF. Bit 5 in the interrupt CFR at 0Ch. DM acknowledge was not complete. Bit 17 in the interrupt CFR at 0Ch. DM enable. Bit 26 in the DM control CFR at 04h. GRF is empty. Bit 15 in the FIFO status CFR at 30h. Reserved Reserved DESCRIPTION
NOTE: An interrupt remains set until cleared by writing a 1 to the interrupt CFR at 0CH, but the associated STAT signal pulses for only one clock cycle.
6
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2
2.1
Internal Registers
TSB12LV32 Configuration Registers
Table 2-1. Configuration Register (CFR) Map
MSB 01 00h 0 1 2 1 34 10 5 0 6 0 7 1 8 0 LSB 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 1 0
ENDSWAP
1
BYTEMODE
0 HANDSHK
1
AUTOUP
0
0
1
1
1
0
0 SPEED
0
1 CHNLCNT
0
1
DMEN
0
DMHDR
0 AR0
0
AR1
0
DMASYNC
0 DMRX
IARBFL IARBFL MONTAG LPS_OFF
VERSION (711538A0h)
04h
PACKET PER BLOCK
DMACK
DM Control
ENA_INSERT_IDLE
FIFOACKCOMP
PHY_PKT_ENA
ENA_CONCAT
DMACKCOMP
ENA_ACCEL
CTNDRSTAT
CTNDRISIN
BUSNRST
FLSHERR
FULLSID
BSYCTL
IRP1EN
IRP2EN
CYMAS
CYSRC
RXSLD
RSTRX
CYTEN
RSTTX
BDIV0
BDIV1
RXEN
TXEN
08h
CLSIDER
SID ERROR CODE
CMAUTO
Control
ATSTARTED ATSTARTED
SELFIDEND SELFIDEND
DMACKERR
ATFEMPTY
DMERROR
RXDMPKT
MCERROR
RXGRFPKT
SELFIDER
LINKON ATSTK
CMDRST
HDRERR
FIFOACK
PHRRX
CARBFL
TCERR
CYDNE
PHRST
SNTRJ
CYSEC
PHINT
0Ch
ARBGP
SUBGP
CYLST
CYST
INT
Interrupt
DMACKERR
ATFEMPTY
DMERROR
RXDMPKT
MCERROR
RXGRFPKT
SELFIDER
LINKON ATSTK
CMDRST
HDRERR
FIFOACK
PHRRX
CARBFL
TCERR
CYDNE
PHRST
SNTRJ
CYSEC
PHINT
ARBGP
SUBGP
CYLST
CYST
INT
10h
Interrupt Mask Cycle Timer
14h 18h
B0_BUSY E_HCRC
SECONDS COUNT TAG1 TAG2 IRPORT1 B2_BUSY NO_PKT NO_ACK F_ACK
CYCLE COUNT IRPORT2
CYCLE OFFSET IRCVALL ISYNCRCVN
Isochronous Port
WRPHY B1_BUSY E_DCRC
1Ch
ACK RAM_TEST
PING VALUE
Maint_Control
B3_BUSY
B1_PND
B2_PND
B0_PND
B3_PND
20h
REGRW
STATSEL0
STATSEL1
STATSEL2
Diagnostic
24h 28h-2Ch
RDPHY
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
Phy Access Reserved
ATFWBMTY
GRFEMPTY
ATFFULL
GRFCLR
ATFCLR
CD
30h
ATFAVAIL
ATACK
GRFUSED
FIFO Status
CONTENDER
NRIDVAL
ROOT
NODECNT
IRMNODEID
BUS NUMBER
NODE NUMBER
34h 38h 3Ch 40h 44h
Bus Reset
(See Section 2.2.13) (See Section 2.2.14) (See Section 2.2.15) (See Section 2.2.16)
LPS_RESET
Header0 Header1 Header2 Header3
48h
NUMBER OF QUADLETS
ACKCODE
SPD
Trailer
4Ch
ASYNC RETRY COUNT
RETRY INTERVAL
Asynchronous Retry
NOTES: A. All dark gray areas (bits) are reserved bits. B. All light gray areas are read-only bits. All remaining are read/write bits.
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
7
Internal Registers
Table 2-2. Header/Trailer Usage for CFRs 38h-48h
DIRECTION OF DM DATA TRANSFER PACKET TYPE AUTO HEADER/ TRAILER INSERT/ EXTRACT YES Isochronous Data-Mover TRANSMIT (to 1394 Bus) Asynchronous/ asynchronous stream packets NO YES NO HEADER/TRAILER REGISTER Header0 CFR is formatted for isochronous transmission. Header1-header3 CFRs can be used for additional channels. Isochronous header is supplied by the external device on the DM interface. The header0 CFR is automatically written with the isochronous header extracted from the transmitted packet. Header0-header3 CFRs are formatted for asynchronous transmission. Asynchronous header is supplied by the external device on the DM interface. The header0-header3 CFRs are automatically written with the header extracted from the transmitted packet. Header0-header3 CFRs and trailer CFR are automatically updated. Isochronous headers are not streamed through the DM port. The trailer quadlet is removed from the data stream. Header0-header3 CFRs and trailer CFR are automatically updated. The isochronous header is streamed through the DM port along with the payload data. The trailer quadlet is appended to the data stream. Header0-header3 CFRs and trailer CFR are automatically updated. Asynchronous headers are not streamed through the DM port. The trailer quadlet is removed from the data stream. Header0-header3 CFRs and trailer CFR are automatically updated. Asynchronous headers are streamed through the DM port along with data. The trailer quadlet is appended to the data stream.
Isochronous/ asynchronous stream packets Data-Mover RECEIVE (from 1394 Bus) Asynchronous
YES
NO
YES
NO
2.2
Configuration Register Definitions
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0111000100 0 1 0 1 0 10 0 1 1 1 0 0 0 1 0 1 0 0 0 00
2.2.1 Version Register at 00h
This register uniquely identifies this device to the software. The value is fixed at 7115 38A0h. This register is read only.
2.2.2 Data-Mover Control Register at 04h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BYTEMODE ENDSWAP HANDSHK DMASYNC CHNLCNT AUTOUP
DMHDR
SPEED
DMEN
PACKET PER BLOCK
DMACK
This register controls the data-mover port and must be set up before using the port. The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0-11 BIT NAME PACKET PER BLOCK FUNCTION Data packets per block transfer DIR R/W DESCRIPTION Number of data packets per block transfer. A block transfer is made up of multiple data packets. A packet is the size of the data payload and is specified as part of the header. This field remains fixed throughout the block transfer; it does not count down. It does not change value until rewritten or reset. The data-mover logic uses this value to activate DMDONE. In asynchronous mode, this field states how many packets the DM should transfer before checking the status of DMREADY again. In isochronous mode, this field states how many isochronous packets should be sent in the DM cycle. These packets are sent over multiple channels if more than one isochronous channel is active. The block transfer may take more than one isochronous cycle. This field is only used in transmit mode. Swap endian. When this bit is set, the quadlet formed by stacking the DM data is byte reversed, (i.e. the quadlet formed by fetching doublet AB01 then CD02 is 02CD 01AB instead of AB01 CD02).
12
ENDSWAP
Endian swap
R/W
8
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
DMRX
AR0
AR1
Internal Registers
BIT NUMBER 13
BIT NAME BYTEMODE
FUNCTION Byte mode
DIR R/W
DESCRIPTION Byte mode. When this bit is set the DM port only looks at DM0-DM7. DM8-DM15 are ignored for transmit and are not driven on receive. In this mode, the maximum speed supported on the 1394 bus is 200 Mbps. Handshake. When this bit is set, DMREADY and DMDONE are in strict handshake mode (i.e., TSB12LV31 compatible mode). DMREADY must not be deactivated until DMDONE activates. When DMDONE goes high, it checks for DMREADY low as an acknowlegde. When this bit is set to 0, DMREADY may be deactivated before DMDONE activates. Automatic update offset address. Valid only for asynchronous transmit using header insert mode (bit 27, DMHDR, set to 0). For write request asynchronous packets, header quadlet 2 contains the destination offset low address for the write. When this bit is set, header quadlet 2 is updated by the value of the payload size (rounded up to the nearest quadlet boundary). DM acknowledge. This is the acknowledge received from the receiving node. This is updated only when the transfer is from the DM port. Reserved
14
HANDSHK
Handshake mode (GPLynx mode)
R/W
15
AUTOUP
Automatic address update
R/W
16-20 21 22-23
DMACK RESERVED SPEED
DM acknowledge
R
DM speed code
R/W
Speed code. This field is valid for isochronous transmit and asynchronous transmit through the DM port. The DM logic uses this field to specify to the Phy the speed of the data transfer. Channel count. This field is valid only in isochronous transmit mode. This field allows the node to transmit multiple data packets during a single isochronous period. The device expects to transmit a packet on every active channel during each isochronous cycle. If valid data is not provided, the value on the DM port is latched and sent. Each packet must have a different channel number, however, hardware does not check this. When the isochronous transmit header is supplied by the DM interface or automatically inserted by the hardware, a maximum of four different channels can be accessed in one isochronous period. In isochronous transmit with automatic header insert, Header0-Header3 CFRs are used as the isochronous header registers. DMEN controls the transmission of packets (asynchronous or isochronous) from the DM port. If this bit is 0, transmission through from the DM port is inhibited. This bit is typically used for asynchronous flow control. In normal operation, if an asynchronous packet transmitted from the DM port receives an acknowledge from the receiving node other than ack complete, this bit is set to 0 and DMERROR is asserted high. Software must set this bit high to allow further transmission of asynchronous packets from the DM port. The default and power-up value is 0. DM header insert bit. When this bit is set to 0, the hardware automatically inserts the header(s) into the DM transmit data. During receive, setting this bit to 0 strips off the header(s)/trailer before routing packet to the DM. Header(s)/trailer are always written to the CFR header/trailer registers regardless of the value of DMHDR. Receive packet routing control encoded bits. These bits in conjunction with DMASYNC and DMRX, bits 30 and 31 in the DM control register, control the routing of received packets to either the data-mover port or to the GRF. See Table 4-1. If this bit is set to 1, the DM port is configured to transmit asynchronous traffic only. If this bit is set to 0, the DM port is configured to transmit isochronous traffic only. The DM port can not transmit both asynchronous and isochronous traffic simultaneously. It must be configured for asynchronous (DMASYNC = 1) or isochronous (DMASYNC = 0). The DM port can receive asynchronous and isochronous data packets simultaneously. See Table 4-1 for more information. If this bit is set to 1, the DM port is configured to receive. If this bit is set to 0, the DM port is configured to transmit. The DM port cannot both transmit and receive data at the same time, it must be configured for either transmit or receive. See Table 4-1 for more informaiton.
24-25
CHNLCNT
Channel count
R/W
26
DMEN
DM enable
R/W
27
DMHDR
DM header insert control
R/W
28-29
AR0, AR1
Receive control routing DM asynchronous
R/W
30
DMASYNC
R/W
31
DMRX
DM receive
R/W
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
9
Internal Registers
2.2.3 Control Register at 08h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ENA_INSERT_IDLE FIFOACKCOMP PHY_PKT_ENA ENA_CONCAT DMACKCOMP ENA_ACCEL CTNDRSTAT CTNDRISIN BUSNRST FLSHERR BSYCTRL
CLSIDER
CMAUTO
FULLSID
IRP1EN
SID ERROR CODE
The control register dictates the basic operation of the TSB12LV32. The power-up reset value of this register equals E004 0200h.
BIT NUMBER 0 BIT NAME FLSHERR FUNCTION Flush GRF on error Receive self-ID packets DIR R/W DESCRIPTION This bit controls the flushing of the GRF when a packet with a data CRC error is detected. The power-up value is 1, which means flush the GRF when a data CRC error is detected. If this bit is set, the self-identification (SID) packets generated by 1394 Phy devices during the bus initialization phase are received and placed into the GRF as a single packet. The default setting of this bit is 1. When this bit is set to 0, the SIDs are not placed into the GRF. This bit must be set to 1 for the SELFIDEND interrupt to function. Save the full self-ID packets. When this bit is 1, the self-ID data quadlet and its inverse quadlet are saved in the GRF. When this bit is 0, only the self-ID data quadlet is saved in the GRF. Phy packet enable allows reception of all Phy packets. If this bit is set to 0, all Phy packets, except for self-IDs, are rejected and interrupt HDERR (if not masked) is generated. One HDERR interrupt is generated for every Phy packet received. BSYCTRL controls which busy status the device returns to incoming packets. When this bit is 0, the device follows normal busy/retry protocol: only send busy when necessary. When this bit is 1, the device sends a busy acknowledge to all incoming packets . When TXEN is cleared, the 1394 transmitter does not arbitrate or send packets. TXEN bit is cleared following a bus reset, and all traffic through the DM port is interrupted. TXEN must be set before packet transmit can resume. The power-on reset value of TXEN is 0. If the TXEN bit is not set after a bus reset when the node is master, the CYSTART terminal does not toggle. When RXEN is cleared, the 1394 receiver does not receive any packets. This bit is not affected by a bus reset and is set to 0 after a power-on reset. Enable acceleration. When this bit is set, fly-by acceleration and accelerated arbitration are enabled. This bit cannot be set while TXEN and RXEN are set. This bit can only be used with a 1394a-2000 capable Phy. Enable concatenation. When this bit is set it allows the link to concatenate multiple isochronous or asynchronous packets. This bit can only be used with a 1394a-2000 capable Phy. Per the 1394a-2000 specification, the link is required to insert an idle state on the control lines after the Phy grants the link control of the Phy/link interface. If using a 1394a-2000 Phy, this bit should be set to 1 in order for the link to drive an idle state following the grant state from the Phy. For 1394-1995 Phys this bit must remain low. When RSTTX is set, the entire transmitter resets synchronously. This bit clears itself. When RSTRX is set, the entire receiver resets synchronously. This bit clears itself. Contender status. On power up, this bit reflects the status of the CONTNDR pin. When bit 13, CTNDRISIN, is 0 this bit is driven out to the CONTNDR pin. If CTNDRISIN is 1 this bit is not used. (Only use on 1394-1995 Phys, or 1394a-2000 Phys when using hardware reset; otherwise, use the 1394a-2000 Phy registers to set the node contender status). Driver enable for the CONTNDR pin. On power up this bit is set to 1, which disables the driver and allows reading of the state of the CONTNDR pin. Writing a 0 to this bit enables the driver and drives bit 12, CTNDRSTAT, to output on the CONTNDR pin. Reserved
1
RXSID
R/W
2
FULLSID
Save full self-ID packet in GRF Phy packets receive enable Busy control
R/W
3
PHY_PKT_ENA
R/W
4
BSYCTRL
R/W
5
TXEN
Transmit enable
R/W
6 7
RXEN ENA_ACCEL
Receive enable Acceleration enable Concatenation enable Insert idle enable
R/W R/W
8
ENA_CONCAT
R/W
9
ENA_ INSERT_IDLE
R/W
10 11 12
RSTTX RSTRX CTNDRSTAT
Transmitter reset Receiver reset Contender status
R/W R/W R/W
13
CTNDRISIN
Contender driver enable
R/W
14
RESERVED
10
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
IRP2EN
CYMAS
CYSRC
RSTRX
CYTEN
RSTTX
RXSID
BDIV0
BDIV1
RXEN
TXEN
Internal Registers
BIT NUMBER 15 16-17
BIT NAME BUSNRST BDIV0, BDIV1
FUNCTION Bus number reset enable BCLK divisor encode bits
DIR R/W R/W
DESCRIPTION When this enable is set high, the bus number field in the bus reset CFR at 34h clears to 3FFh when a local 1394 bus reset is received. BCLK divisor encode bits. Used to divide down the BCLK to generate the link power status (LPS) clock to the Phy. BDIV0 0 0 1 1 BDIV1 0 1 0 1 DESCRIPTION Divide by 16. Default power-on value. Recommended for BCLK frequencies in the range of 8-60 MHz Divide by 2. Recommended for BCLK frequencies in the range of 1-11 MHz Divide by 4. Recommended for BCLK frequencies in the range of 2-22 MHz Divide by 32. Recommended for BCLK frequencies in the range of 16-80 MHz
18
DMACKCOMP
Data-mover acknowledge complete
R/W
Data-mover acknowledge complete. This bit controls the acknowledge response to an asynchronous packet received and routed to the DM port. The default and power-on value is 0, which causes the device to respond with an ack pending. A value of 1 causes the device to respond with an ack complete for write request packets. FIFO acknowledge complete. This bit controls the acknowledge response to an asynchronous packet received and routed to the GRF. The default and power-on value is 0, which causes the device to respond with an ack pending. A value of 1 causes the device to respond with an ack complete. When CYMAS is set and the TSB12LV32 is attached to the root Phy, the cyclemaster function is enabled. When the cycle_count field of the cycle timer register increments, the 1394 transmitter sends a cycle-start packet. When CYMAS is cleared, the TSB12LV32 cannot be cyclemaster. When CYSRC is set, the cycle_count field increments and the cycle_offset field resets for each positive transition of CYCLEIN. When CYSRC is cleared, the cycle_count field increments when the cycle_offset field rolls over. When CYTEN is set, the cycle_offset field increments. When CLSIDER is set, the SIDERCODE field (bits 24-27) is cleared. This bit clears itself. SID ERROR CODE contains the error code of the first self-ID error. The error code is as follows: 0000 0001 0010 0011 0100 0101 0110 0111 1000 No error Last self-ID received was not all child ports Received Phy ID in self-ID not as expected Quadlet not inverted (phase error) Phy ID sequence error (two or more gaps in IDs) Phy ID sequence error (large gap in IDs) Phy ID error within packet Quadlet not the inverse of the prior quadlet Reserved
19
FIFOACKCOMP
FIFO acknowledge complete Cycle master
R/W
20
CYMAS
R/W
21
CYSRC
Cycle source
R/W
22 23 24-27
CYTEN CLSIDER SID ERROR CODE
Cycle timer enable Self-ID error-code clear Self-ID error code
R/W W R
28 29 30 31
CMAUTO IRP1EN IRP2EN RESERVED
Auto set cycle master IR port 1 enable IR port 2 enable
R/W R/W R/W
When CMAUTO is high, the TSB12LV32 automatically enables CYMAS if this node becomes the root following a bus reset. When IRP1EN is set, the 1394 receiver accepts isochronous packets when the channel number matches the value in the IR port1 field at 18h. When IRP2EN is set, the 1394 receiver accepts isochronous packets when the channel number matches the value in the IR Port2 field at 18h. Reserved
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
11
Internal Registers
2.2.4 Interrupt/Interrupt Mask Registers at 0Ch and 10h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ATSTARTED SELFIDEND ATFEMPTY
DMACKERR
DMERROR
MCERROR
RXGRFPKT
SELFIDER
RXDMPKT
CMDRST
FIFOACK
LINKON
HDRERR
CARBFL
ARBGP
SUBGP
PHRRX
CYDNE
ATSTK
TCERR
The interrupt and interrupt mask register work in tandem to inform the microcontroller interface when the state of the TSB12LV32 changes. The interrupt register is at 0Ch and the interrupt mask register is at 10h. The interrupt register powers up all 0s, however, the interrupt mask register powers up with the INT and the MCERROR bits set, i.e., 8000 1000h. The mask bits allows individual control for each interrupt. A 1 in the mask bit field allows the corresponding interrupt in the interrupt register to be generated. Once an interrupt is generated it must be cleared by writing a 1 to the bit in the interrupt register. For testing, each interrupt bit can be set manually. This is done by first setting the REGRW bit in the diagnostic register at 20h and then setting the individual interrupt bit. This is also true for bit 0 in the interrupt register. In this test mode, the interrupt mask register is not used and has no effect.
BIT NUMBER 0 1 2 BIT NAME INT PHINT PHRRX FUNCTION Interrupt Phy chip interrupt Phy register information received Phy reset started Self-ID validated Asynchronous transfer started GRF packet received CSR register reset request Data-mover error DIR R/W R/W R/W DESCRIPTION INT contains the value of all interrupt and interrupt mask bits ORed together. When PHINT is set, the Phy has signalled an interrupt through the Phy interface When PHRRX is set, a register value has been transferred to the Phy access register (CFR at offset 24h) from the Phy interface. When PHRST is set, a Phy-LLC reconfiguration has started (1394 bus reset). Self-ID end. This bit is set at the end of the self-ID reporting process. When this bit is set, the contents of the bus reset CFR at 34h are valid. The RXSID bit must be set to 1 for the SELFIDEND interrupt to function. Asynchronous transfer started. This bit is activated when the 1394 bus has been granted and the first quadlet from the FIFO is about to be transmitted from the ATF. Receive packet to GRF. This bit is set whenever a complete packet has been confirmed into the GRF (asynchronous or isochronous). If the CMDRST bit is set, the device has been sent a quadlet write request to the Reset_Start CSR register (target address is FFFF F000 000Ch). DM error. This bit is set if there is an error in the DM stream. For transmit, if the DM port is configured for byte access and the speed code in the DM control register or the asynchronous header register is set for 400 Mbps, then this bit is set. Under this condition DMEN (bit 24 of the DM control CFR at 04h) is reset to 0, preventing further transmit. For receive this bit is set if there is a header or data CRC error or if the DM port is configured for byte access and the data is received at 400 Mbps. Any packet with a CRC error is discarded. Receive packet to DM. This bit is set whenever a packet is received to the DM port. This bit is set if an error in the self-ID quadlet/packet has been detected. This bit is set if a link-on pulse is detected on the LINKON input terminal. This bit should be used by software to reactivate the LPS output to the Phy. When ATSTK is set, the transmitter has detected invalid data at the asynchronous transmit-FIFO interface. If the first quadlet of a packet is not written to the ATF_First or ATF_First&Update or there is an underflow of the ATF, an ATSTK interrupt is generated. When this state is entered, no asynchronous packets can be sent until the ATF is cleared by way of the ATFCLR control bit in the FIFO status CFR at 30h. Isochronous packets can be sent while in this state. ATFEMPTY. This bit is set to 1 when the ATF becomes empty.
3 4
PHRST SELFIDEND
R/W R/W
5 6 7 8
ATSTARTED RXGRFPKT CMDRST DMERROR
R/W R/W R/W R/W
9 10 11 12
RXDMPKT SELFIDER LINKON ATSTK
Data-mover packet receive Self-ID packet error Link-ON detect Transmitter is stuck (AT)
R/W R/W R/W R/W
13
ATFEMPTY
ATF empty interrupt
R/W
12
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
IARBFL
CYSEC
PHRST
SNTRJ
PHINT
CYLST
CYST
INT
Internal Registers
BIT NUMBER 14
BIT NAME SNTRJ
FUNCTION Busy acknowledge sent by receiver Header error
DIR R/W
DESCRIPTION When SNTRJ is set, the receiver is forced to send a busy acknowledge to any packet addressed to this node because the GRF overflowed. When HDRERR is set, the receiver detected a header CRC error on an incoming packet that may have been addressed to this node. Any packet with a CRC error is discarded. When TCERR is set, the transmitter detected an invalid transaction code in the data at the transmit-FIFO interface. DM acknowledge error. This bit is set to 1 when the acknowledge received is not ack complete. When this occurs, DMEN (bit 26) of the DM control CFR at 04h is reset to 0 and no more asynchronous transmissions from the DM port are allowed to take place until DMEN is set to 1. FIFO ack interrupt. This bit is set when an acknowledge from a previous ATF transmission has been received. Microcontroller interface error. This bit is set whenever the microcontroller write protocol is violated. This bit is set to 1 when read or write errors occur on the microcontroller interface. This bit latches the value on the TEA signal terminal. This interrupt is set one clock cycle after the triggering error occurs. When CYSEC is set, the cycle-second field in the cycle timer register has incremented. This occurs about every second when the cycle timer is enabled. When CYST is set, the transmitter has sent or the receiver has received a cycle-start packet. When CYDNE is set, a subaction gap has been detected on the bus after the transmission or reception of a cycle-start packet. This bit indicates that the isochronous cycle is complete. Reserved When CYLST is set, the cycle timer has rolled over twice without the reception of a cycle-start packet. This occurs only when this node is not the cycle master. All isochronous traffic stops once CYLST is set. However, asynchronous and asynchronous stream packet traffic is not affected. When CARBFL is set, the arbitration to send a cycle-start packet has failed. When ARBGP is set, the 1394 bus has been idle for an arbitration reset gap. When SUBGP is set, the 1394 bus has been idle for a subaction gap time (fair gap). This bit can be set only when the REGRW bit has been set in the diagnostics CFR at 20h. Reserved
15
HDRERR
R/W
16 17
TCERR DMACKERR
Transaction code error Data-mover acknowledge error FIFO acknowledge interrupt Microcontroller interface error
R/W R/W
18
FIFOACK
R/W
19
MCERROR
R/W
20 21 22
CYSEC CYST CYDNE
Cycle second incremented Cycle started Cycle done
R/W R/W R/W
23 24
RESERVED CYLST Cycle lost R/W
25 26 27 28-30 31
CARBFL ARBGP SUBGP RESERVED IARBFL
Cycle arbitration failed Arbitration gap Subaction gap
R/W R/W R/W
Isochronous arbitration failed
R/W
When IARFL is set, the arbitration to send an isochronous packet has failed.
2.2.5 Cycle Timer Register at 14h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SECONDS COUNT CYCLE COUNT CYCLE OFFSET
This register must be written to as a quadlet. The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0-6 7-19 20-31 BIT NAME SECONDS COUNT CYCLE COUNT CYCLE OFFSET FUNCTION Seconds count Cycle count Cycle offset DIR R/W R/W R/W 1-Hz cycle timer counter 8,000-Hz cycle timer counter 24.576-MHz cycle timer counter DESCRIPTION
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
13
Internal Registers
2.2.6 Isochronous Port Register at 18h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
IRPORT1 IRPORT2 ISYNCRCVN MONTAG IRCVALL TAG1 TAG2
The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0-1 2-7 BIT NAME TAG1 IRPORT1 FUNCTION Tag field 1 Isochronous receive port 1 channel number Tag field 2 Isochronous receive port 2 channel number Synchronous enable Receive all isochronous packets Match on tag DIR R/W R/W DESCRIPTION The TAG1 field can further qualify the isochronous reception for isochronous receive PORT1 when the MONTAG bit is set. IRPORT1 contains the channel number of the isochronous packets that the receiver accepts. The receiver accepts isochronous packets with this channel number when the IRP1EN bit is set. The TAG2 field can further qualify the isochronous reception for isochronous receive PORT2 when the MONTAG bit is set. IRPORT2 contains the channel number of the isochronous packets that the receiver accepts. The receiver accepts isochronous packets with this channel number when the IRP2EN bit is set. Reserved R/W In isochronous receive mode to the DM port, when the ISYNCRCVN enable bits are high, the DMPRE terminal pulses when an isochronous packet is received whose SYNC bit field in its header matches the bit pattern in this field. The default is 0000b. When the IRCVALL bit is set high, the TSB12LV32 receives all isochronous packets regardless of the channel number or tag number. The default for this bit is 0. Reserved R/W MONTAG is set when the user wants to accept only isochronous packets that match both the tag field and the channel number field. When set, MONTAG indicates that isochronous receive data is accepted. The default for this bit is 0.
8-9 10-15
TAG2 IRPORT2
R/W R/W
16-23 24-27
RESERVED ISYNCRCVN
28
IRCVALL
R/W
29-30 31
RESERVED MONTAG
14
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2.2.7 Maint_Control Register at 1Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
NO_ACK E_HCRC E_DCRC NO_PKT F_ACK
ACK
PING VALUE
This register is used to generate test conditions. The control bits in this register allow errors to be inserted into various places in the packets generated by this node. After the completion of error insertion, enabled error-insertion controls are disabled. The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0 BIT NAME E_HCRC FUNCTION Header CRC error Data CRC error DIR R/W DESCRIPTION If E_HCRC is set, the packet header CRC component of the next primary packet generated by this node is in error or is invalid; otherwise, this bit has no effect. After the next packet for this node is generated, this bit is cleared. If E_DCRC is set, the packet data CRC component of the next primary packet generated by this node is in error or is be invalid; otherwise, this bit has no effect. After the next packet for this node is generated, this bit is cleared to zero immediately upon transmission of the erroneous CRC. If NO_PKT is set, the next primary packet to be generated by this node is discarded. This bit is cleared to zero immediately after the next packet for this node is discarded. If F_ACK is set, the ack field is used within the next acknowledge packet generated by this node. This bit is cleared to zero immediately after the next acknowledge packet for this node is generated. If NO_ACK is set, the next acknowledge packet (that would normally have been generated by this node) is not sent. This bit is cleared to zero immediately when the next acknowledge packet for this node is discarded. Reserved Ack packet field R/W The 8-bit ACK field contains the 8-bit acknowledge packet (ack_code and ack_parity) to be supplied when the F_ACK bit indicates a modified acknowledge packet is to be generated. Reserved Ping timer value R/W Ping timer value. This value reflects the time it takes a node to respond to a ping packet. The granularity of this timer is 40 ns.
1
E_DCRC
R/W
2 3
NO_PKT F_ACK
No packet Ack field
R/W R/W
4
NO_ACK
No ack
R/W
5-7 8-15 16-23 24-31
RESERVED ACK RESERVED PING VALUE
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
15
Internal Registers
2.2.8 Diagnostic Register at 20h
0
B0_BUSY
1
B1_BUSY
2
B2_BUSY
3
B3_BUSY
4
B0_PND
5
B1_PND
6
B2_PND
7
B3_PND
8
RAMTEST
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
REGRW STATESEL0 STATESEL1 STATESEL2
The power-up reset value of this register equals 0000 4AD0h.
BIT NUMBER 0 1 2 3 4 BIT NAME B0_BUSY B1_BUSY B2_BUSY B3_BUSY B0_PND FUNCTION Byte 0 busy Byte 1 busy Byte 2 busy Byte 3 busy Byte 0 pending Byte 1 pending Byte 2 pending Byte 3 pending Internal test DIR R R R R R DESCRIPTION Byte 0 busy. When this bit is set, no microcontroller write to byte 0 of any CFRs is allowed. The microcontroller must first poll this bit before writing to byte 0. Byte 1 busy. When this bit is set, no microcontroller write to byte 1 of any CFRs is allowed. The microcontroller must first poll this bit before writing to byte 1. Byte 2 busy. When this bit is set, no microcontroller write to byte 2 of any CFRs is allowed. The microcontroller must first poll this bit before writing to byte 2. Byte 3 busy. When this bit is set, no microcontroller write to byte 3 of any CFRs is allowed. The microcontroller must first poll this bit before writing to byte 3. Byte 0 pending. When this bit is set, it indicates that byte 0 of a word or quadlet write has been accepted and the hardware is waiting for the remaining bytes to be written. When the full write is complete, this bit is cleared. Byte 1 pending. When this bit is set, it indicates that byte 1 of a word or quadlet write has been accepted and the hardware is waiting for the remaining bytes to be written. When the full write is complete, this bit is cleared. Byte 2 pending. When this bit is set, it indicates that byte 2 of a word or quadlet write has been accepted and the hardware is waiting for the remaining bytes to be written. When the full write is complete, this bit is cleared. Byte 3 pending. When this bit is set, it indicates that byte 3 of a word or quadlet write has been accepted and the hardware is waiting for the remaining bytes to be written. When the full write is complete this bit is cleared. This bit can be set only when TESTMODE is high. When this bit is set, the built-in self-test (BIST) for the FIFOs (transmit and receive) is run. On completion of the test hardware resets this bit to 0 and simultaneously sets bits 30 and 31. This is for TI internal test purposes only. When REGRW is set, write-protected bits in various registers can be written (particularly in the interrupt / interrupt mask registers). Reserved State0 select State1 select State2 select R/W R/W R/W Status output select bits. Used to program the output of STAT0 terminal. See Table 1-2. Status output select bits. Used to program the output of STAT1 terminal. See Table 1-2. Status output select bits. Used to program the output of STAT2 terminal. See Table 1-2. Reserved
5
B1_PND
R
6
B2_PND
R
7
B3_PND
R
8
RAM_TEST
R/W
9
REGRW
Register read/write access
R/W
10-15 16-19 20-23 24-27 28-31
RESERVED STATSEL0 STATSEL1 STATSEL2 RESERVED
16
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2.2.9 Phy Access Register at 24h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WRPHY RDPHY PHYRGAD PHYRGDATA PHYRXAD PHYRXDATA
The Phy access register allows access to the registers in the attached 1394 Phy. The most-significant 16 bits send read and write requests to the Phy registers. The least-significant 16 bits are for the Phy to respond to a read request sent by the TSB12LV32. The Phy access register also allows the Phy interface to send information back to the TSB12LV32. When the Phy interface sends new information to the TSB12LV32, the Phy register-information-receive (PhyRRx) interrupt is set. The power-up reset value of this register equals 0000 0000h. This register, like the cycle timer register, must be accessed as a quadlet. However, the most significant word can be accessed as a doublet, because the least significant word is unwriteable except in test mode. This register is not byte accessible.
BIT NUMBER 0 BIT NAME RDPHY FUNCTION Read Phy register Write Phy register DIR R/W DESCRIPTION When RDPHY is set, the TSB12LV32 sends a read register request with the address equal to the PHYRGAD field to the Phy interface. This bit is cleared when the request is sent. When WRPHY is set, the TSB12LV32 sends a write register request with the address equal to the PHYRGAD field to the Phy interface. This bit is cleared when the request is sent. Reserved Phy-register transmitted address Phy-register transmitted data Phy-register received address Phy-register received data R/W PHYRGAD is the address of the Phy register that is to be accessed.
1
WRPHY
R/W
2-3 4-7
RESERVED PHYRGAD
8-15
PHYRGDATA
R/W
PHYRGDATA is the data to be written to the Phy register indicated in PHYRGAD.
16-19 20-23
RESERVED PHYRXAD R/W
Reserved PHYRXAD is the address of the register from which PHYRXDATA came. For testing, these bits can be set only when the REGRW bit has been set in the diagnostics CFR at 20h. PHYRXDATA contains the data from the register addressed by PHYRXAD. For testing, these bits can be set only when the REGRW bit has been set in the diagnostics CFR at 20h.
24-31
PHYRXDATA
R/W
2.2.10
Reserved Registers at 28h-2Ch
These registers are reserved for future use.
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
17
Internal Registers
2.2.11
FIFO Status Register at 30h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ATFWBMTY GRFEMPTY ATFFULL ATFCLR GRFCLR CD
ATFAVAIL
ATACK
GRFUSED
The power-up reset value of this register equals 6083 0000h.
BIT NUMBER 0 1 2-11 12 13 14 15 16 17-21 22-31 BIT NAME ATFCLR ATFWBMTY ATFAVAIL ATFFULL GRFCLR RESERVED GRFEMPTY CD ATACK GRFUSED GRF empty Check 33rd bit (GRF read) ATF acknowledge GRF space used R R R R FUNCTION ATF clear ATF write buffer empty ATF space available ATF full bit GRF clear bit DIR R/W R R R R/W DESCRIPTION ATF clear. When this bit is set to 1, the ATF is cleared. This bit clears itself. ATF write buffer empty. This bit is set when the 4-quadlet ATF write buffer is empty. Size of ATF available, in quadlets. The power-on value of this field is 10 0000 1000 (520 quadlets). When the ATF is full, this bit is set. GRF clear. Set this bit to 1 to clear the contents of the GRF. This bit clears itself. Reserved GRF empty. GRFEMPTY is set when the four-quadlet GRF read buffer is empty and the GRF is empty too. This bit is set to 1 when the quadlet pointed to by the GRF read pointer is the first quadlet or the packet trailer (packet token). The acknowledge received in response to a packet sent via the ATF GRF space used, in quadlets. This value is the number of quadlets written in the GRF. This does not count the entire read buffer, which can hold five quadlets. If the GRF is empty and the microcontroller attempts to read the GRF, the last quadlet in the GRF is reread.
18
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2.2.12
Bus Reset Register at 34h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CONTENDER NRIDVAL ROOT
NODECNT
IRMNODEID
BUS NUMBER
NODE NUMBER
The power-up reset value of this register equals 81BF FFC0h. NOTE: The power-up reset value shown above assumes one node on the bus only. A 1394a-2000 compliant Phy is assumed to be attached to the TSB12LV32. If a 1394-1995 Phy is attached to the TSB12LV32 link, the NODECNT filed is 0. This is due to the fact that a 1394-1995 compliant Phy does not report its self-ID packet back to the local link.
BIT NUMBER 0 1 2-7 8 9 10-15 16-25 26-31 BIT NAME NRIDVAL RESERVED NODECNT ROOT CONTENDER IRMNODEID BUS NUMBER NODE NUMBER Node count Root Contender IRM node identification Bus number Node number R R R R R/W R/W FUNCTION Valid DIR R DESCRIPTION When set, NRIDVAL indicates that the node ID, IRM node ID, node count, and root information are valid. This bit is read-only. Reserved NODECNT contains the number of nodes detected in the system. This field is loaded with 1 following a power-on reset. The NODECNT field is read-only. Root is set when the current node is the root node. This bit is read-only. Contender contains the status of the TSB12LV32 CONTNDR terminal. This bit is readonly. IRMNODEID is the isochronous resource manager node identification. If there is no IRM node present on the bus, these bits are equal to 3Fh. These bits are read-only. BUSNUMBER is the 10-bit IEEE 1212 bus number. These bits are set to 3FFh when the BUSNRST bit in the control CFR at 08h is set and there is a bus reset. NODENUMBER is the node number of the current node. These bits are automatically updated following a bus reset. To change the node number of this node (spoofing), the TESTMODE terminal must be set high. Spoofing is used for TI internal test purposes only.
2.2.13
Header0 Register at 38h
Header0 register contains the isochronous packet header or the first quadlet of an asynchronous packet header if the device is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert transmit mode or if it is in receive mode, this register is updated with the received header or the DM-supplied transmit header. This register is write protected such that it cannot be written to unless automatic header insert mode is enabled and the DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0). The power-up reset value of this register equals 0000 0000h.
ISOCHRONOUS HEADER FOR QUADLET 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
BIT NUMBER 0-15 16-17 18-23 24-27 28-31
BIT NAME PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
FUNCTION Packet data length Tag field Channel number Transmission code Synchronization code
DIR R/W R/W R/W R/W R/W Packet data length in bytes.
DESCRIPTION
The tag field provides a high-level label for the format of the data carried by the isochronous packet. Channel number field Packet transaction code An application-specific control field
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
19
Internal Registers
ASYNCHRONOUS HEADER FOR QUADLET 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPEED TLABEL RT TCODE PRIORITY
BIT NUMBER 0-13 14-15
BIT NAME RESERVED SPEED
FUNCTION
DIR Reserved
DESCRIPTION
Speed
R/W
Speed at which the Phy is to transmit the packet: 00 => S100 01 => S200 10 => S400 Transaction label The retry code specifies whether this packet is a retry attempt and the retry protocol to be followed by the destination node. The transaction code specifies the packet format and the type of transaction that is to be performed. Priority code (applies only to the backplane Phy)
16-21 22-23 24-27 28-31
TLABEL RT TCODE PRIORITY
Transaction label Retry code Transaction code Priority field
R/W R/W R/W R/W
2.2.14
Header1 Register at 3Ch
Header1 register contains the isochronous packet header (if multiple channels are supported) or the second quadlet of an asynchronous packet header if the deivce is in automatic header insert transmit mode. If the device is not in automatic-header-insert transmit mode or if it is in receive mode, this register is updated with the second received header quadlet or the DM-supplied transmit header. This register powers up with all bits reset to 0. For multiple isochronous channels (multiple isochronous packets within the same isochronous cycle), this register contains the isochronous header of the second isochronous packet in the same format as the header0 register if the device is in automatic-header-insert transmit mode. This register is write protected such that it cannot be written to unless automatic-header-insert mode is enabled and the DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0).
ISOCHRONOUS HEADER FOR QUADLET 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
BIT NUMBER 0-15 16-17 18-23 24-27 28-31
BIT NAME PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
FUNCTION Packet data length Tag field Channel number Transmission code Synchronization code
DIR R/W R/W R/W R/W R/W Packet data length in bytes
DESCRIPTION
The tag field provides a high-level label for the format of the data carried by the isochronous packet. Channel number field Packet transaction code An application-specific control field
ASYNCHRONOUS HEADER FOR QUADLET 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DESTINATION ID
BIT NUMBER 0-15 16-31
BIT NAME DESTINATION ID RESERVED
FUNCTION Destination ID
DIR R/W
DESCRIPTION For asynchronous packets this field contains the destination node ID. Reserved
20
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2.2.15
Header2 Register at 40h
Header2 register contains the isochronous packet header (if multiple channels are supported) or the third quadlet of an asynchronous packet header if the deivce is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert transmit mode or if it is in receive mode, this register is updated with the third quadlet of the asynchronous received header or the DM-supplied transmit header. This register powers up with all bits reset to 0. For multiple isochronous channels (multiple isochronous packets within the same isochronous cycle), this register contains the isochronous header of the third isochronous packet in the same format as the header0 register if the device is in automatic-header-insert transmit mode. This register is write protected such that it cannot be written to unless automatic-header-insert mode is enabled and the DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0).
ISOCHRONOUS HEADER FOR QUADLET 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
BIT NUMBER 0-15 16-17 18-23 24-27 28-31
BIT NAME PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
FUNCTION Packet data length Tag field Channel number Transmission code Synchronization code
DIR R/W R/W R/W R/W R/W Packet data length in bytes
DESCRIPTION
The tag field provides a high-level label for the format of the data carried by the isochronous packet. Channel number field Packet transaction code An application-specific control field
ASYNCHRONOUS HEADER FOR QUADLET 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HEADER2
BIT NUMBER 0-31
BIT NAME HEADER2
DIR R/W
DESCRIPTION Third header quadlet for an asynchronous packet or header for a multiple isochronous packet
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
21
Internal Registers
2.2.16
Header3 Register at 44h
Header3 register contains the isochronous packet header (if multiple channels are supported) or the fourth quadlet of an asynchronous packet header if the device is in automatic-header-insert transmit mode. If the device is not in automatic-header-insert mode or if it is in receive mode, this register is updated with the fourth quadlet of the asynchronous received header or DM-supplied transmit header. This register powers up with all bits reset to 0. For multiple isochronous channels (multiple isochronous packets within the same isochronous cycle), this register would contain the isochronous header of the fourth isochronous packet in the same format as the header0 register if the device is in automatic-header-insert transmit mode. This register is write protected such that it cannot be written to unless automatic-header-insert mode is enabled and the DM is in transmit mode (i.e., DMHDR = 0 and DMRX = 0).
ISOCHRONOUS HEADER FOR QUADLET 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
BIT NUMBER 0-15 16-17 18-23 24-27 28-31
BIT NAME PACKET DATA LENGTH TAG CHANNEL NUMBER TCODE SYNC BITS
FUNCTION Packet data length Tag field Channel number Transmission code Synchronization code
DIR R/W R/W R/W R/W R/W Packet data length in bytes
DESCRIPTION
The tag field provides a high-level label for the format of the data carried by the isochronous packet. Channel number field Packet transaction code An application-specific control field
ASYNCHRONOUS HEADER FOR QUADLET 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
HEADER3
BIT NUMBER 0-31
BIT NAME Header3
DIR R/W
DESCRIPTION Fourth header quadlet for an asynchronous packet or header for a multiple isochronous packet
22
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Internal Registers
2.2.17
Trailer Register at 48h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LPS_RESET NUMBER OF QUADLETS ACKCODE SPD LPS_OFF
The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0-1 2-15 16-18 19-23 BIT NAME RESERVED NUMBER OF QUADLETS RESERVED ACKCODE Acknowledge code R/W Number of quadlets R/W FUNCTION DIR Reserved Total number of quadlets in the current packet (data payload and header quadlets only) Reserved This 5-bit field holds the acknowledge code sent by the receiver for the current packet (see Note following the table): ACKCODE 00000 00001 00010 00011 00100 00101 00110 00111-01010 01011 01100 01101 01110 01111 10000 10001 10010 10011-11111 24-25 26-27 RESERVED SPD Speed code R/W Reserved The SPD field indicates the speed at which the current packet was sent. 00 100 Mbps, 10 400 Mbps, 01 200 Mbps, 11 is undefined. Reserved LPS reset R/W Link power status reset. This bit is set by software and is reset by hardware. When this bit is set, hardware deactivates LPS for a fixed period to ensure that the Phy has reset the interface. It then reactivates LPS. When this bit is cleared by hardware, a PHRST interrupt in the interrupt CFR at 0Ch is also generated. Link power status off. If set to 1, this bit turns off the LPS-pulsed output to the Phy. This bit can also be turned off from the Phy. Upon detection of the LINKON pulsed input signal, this bit is turned off, allowing LPS to be driven to the Phy which, in turn, activates SCLK and powers up the link. Name Reserved Ack_complete Ack_pending Reserved Ack_busy_X Ack_busy_A Ack_busy_B Reserved Ack_tardy Ack_conflict_error Ack_data_error Ack_type_error Ack_address_error These codes are added by the link layer and are not part of the IEEE 1394-1995 Ack too long specification. (more than 8 bits) No ack received Ack too short (less than 8 bits) Reserved DESCRIPTION
28 - 29 30
RESERVED LPS_RESET
31
LPS_OFF
LPS off
R/W
NOTE: The acknowledge code specified by the IEEE 1394-1995 specification is a 4-bit field. The ACKCODE field in this register is a 5-bit field. The TSB12LV32 logic core is able to provide (specifiy) three additional ACKCODEs, which are not part of the original specification. The ACKCODEs are 10000, 10001, and 10010.
SLLS336B--August 2003 TSB12LV32, TSB12LV32I 23
Internal Registers
2.2.18
Asynchronous Retry Register at 4Ch
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ASYNC RETRY COUNT RETRY INTERVAL
The TSB12LV32 only supports single-phase retry protocol and does not implement dual-phase retry protocol. See Section 7.3.5 of the IEEE Std 1394-1995 (IEEE standard for a high-performance serial bus) for more information on retry protocol. The power-up reset value of this register equals 0000 0000h.
BIT NUMBER 0-7 BIT NAME ASYNC RETRY COUNT FUNCTION Retry count DIR R/W DESCRIPTION The asynchronous retry count field specifies the number of times to automatically retry sending asynchronous packets from the ATF before giving up. After the retry count is exhausted the FIFOACK interrupt in the interrupt CFR at 0Ch is generated when an ACK_BUSY_X is received. Asynchronous retry interval is the time in increments of isochronous cycles between asynchronous retries. Reserved
8-15 16-31
RETRY INTERVAL RESERVED
Retry interval
R/W
24
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Microcontroller Interface
3
Microcontroller Interface
The microcontroller interface allows the local microcontroller/microprocessor to communicate with the internal control and configuration registers (CFR), asynchronous transfer FIFO (ATF) and general receive FIFO (GRF). All microcontroller reads/writes are initiated by the microcontroller. The microcontroller interface supports read transactions from the CFR or GRF, and write transactions to the CFR or ATF. The microcontroller interface can operate in byte (8-bit) or word (16-bit) accesses. Each CFR, with the exception of the cycle timer register at 14h and the Phy access register at 24h, can be addressed on byte or word boundaries. The possible configurations for the interface are shown in Table 3-1. The TSB12LV32 can also be directly connected to the Motorola 68000 and ColdFire line of MC/MP. Table 3-2 defines the mapping of the microcontroller interface pins between the TSB12LV32, the Motorola 68000 and the ColdFire microprocessor. Table 3-1. Microcontroller Interface Modes of Operation
TSB12LV32 MODE-CONFIGURATION TERMINALS COLDFIRE 0 0 0 0 1 1 1 1 M8BIT_SIZ0 0 0 1 1 0 0 1 1 MCMODE_SIZ1 0 1 0 1 0 1 0 1 16-bit fixed timing mode 16-bit MCS-MCA handshake mode 8-bit fixed timing mode 8-bit MCS-MCA handshake mode ColdFire 4-byte (2-word) burst mode ColdFire 2-byte (1-word) mode ColdFire 1-byte mode (not supported) ColdFire 16-byte (8-word) burst mode MODE OF OPERATION
Table 3-2. TSB12LV32 MP/MC Interface Terminal Function Matrix
TSB12LV32 TERMINAL NAME MA0-MA6 MD0-MD15 MCA MCS MWR MCMODE/SIZ1, M8BIT/SIZ0 TEA BCLK USAGE Input I/O Output Input Input Input Output Input MOTOROLA 68000/ColdFire MICROCONTROLLER TERMINAL NAME A[6:0] D[31:16] TAZ TSZ R/WZ SIZ1, SIZ0 TEAZ SCLK / CLK USAGE Output I/O Input Output Output Output Input Input
The byte stacker allows the TSB12LV32 to be easily connected to most processors. The byte stacker consists of a programmable 8-/16-bit data bus and a 7-bit address bus. The TSB12LV32 uses cycle-start and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be asynchronous to one another. The TSB12LV32 has an interrupt driver to reduce cycling. All bus signal labeling on the TSB12LV32 microcontroller interface uses bit 0 to denote the most significant bit (MSB). The transfer error acknowledge (TEA) is asserted whenever there is an illegal transfer request by the microcontroller, such as:
ColdFire is a trademark of Motorola, Inc. SLLS336B--August 2003 TSB12LV32, TSB12LV32I 25
Microcontroller Interface
*
The requested data transfer size is unsupported. - - - - - An ATF burst access ends on a nonquadlet boundary. A microcontroller address is not on a word boundary whil in 16-bid data-bus mode. The microcontroller attempts to write to the CFR across quadlet boundaries. A GRF read-byte address does not start from 00h. GRF read is not done on a quadlet boundary.
*
ColdFire error - MCS is asserted for more than one BCLK cycle for each transaction.
3.1
Microcontroller Byte Stack (Write) Operation
The microcontroller byte stack (write) protocol is shown in Figure 3-1.
TSB12LV32 Write No Yes Yes No
M8BIT/SIZ0 = 1
Microcontroller Writes MSByte (Byte 0) to TSB12LV32 Yes
No
No
Microcontroller Writes MSDoublet (Doublet0) to TSB12LV32 Yes
Microcontroller Writes Byte 1 to TSB12LV32 Yes
No
No
Microcontroller Writes LSDoublet (Doublet1) to TSB12LV32 Yes
Microcontroller Writes Byte 2 to TSB12LV32 Yes
No
Rejects Quadlet Write and Issues a MCERROR Interrupt
Microcontroller Writes Byte 3 to TSB12LV32 Yes
No
TSB12LV32 Accepts Quadlet Write
Figure 3-1. Microcontroller Byte Stack (Write) Operation
26 TSB12LV32, TSB12LV32I SLLS336B--August 2003
Microcontroller Interface
3.2
Microcontroller Byte Unstack (Read) Operation
The microcontroller byte unstack (read) protocol is shown in Figure 3-2.
TSB12LV32 Read No Yes
Microcontroller Reads Same Quadlet As Before Yes No
Microcontroller Reads Same Byte/Doublet As Before Yes No
TSB12LV32 Provides Updated Byte/Doublet Data
TSB12LV32 Provides Updated Byte/Doublet Data
TSB12LV32 Provides Held Byte/Doublet Data
Figure 3-2. Microcontroller Byte Unstack (Read) Operation
3.3
Microcontroller Interface Read/Write Timing
The microcontroller interface can be configured to operate in one of the following modes: handshake, fixed-timing, or ColdFire mode. Burst transfers are only supported in the latter two modes.
3.3.1 Microcontroller Handshake Mode
Byte handshake read and word handshake read are shown in Figure 3-3 and Figure 3-4, respectively. The signal timing sequence for a handshake read transaction can be summarized as follows: 1. The host takes MCS low to signal the start of access. When the rising edge of BCLK samples MCS low and MWR high, the MD[0:15] lines are enabled and driven with the read value. For an 8-bit data bus, the MD[0:7] lines are not used. 2. Following the next rising edge of BCLK, the TSB12LV32 takes MCA low to signal that the requested operation is complete. This takes place after two BCLK cycles. MCA remains low with the MD lines containing valid read data until the microcontroller interface releases MCS (high state) 3. The host takes MCS high to signal the end of the process. 4. The TSB12LV32 holds MCA low until MCS is sampled high, then MCA is set high to acknowledge the end of the access. The MD lines are not put in the high-impedance state until after MCA is taken high. After MCA is asserted high, another read or write transaction can begin after the next rising edge of BCLK. Note that data size is determined by the M8BIT/SIZ0 signal, it is asserted high to select byte mode in Figure 3-3 and asserted low to select word mode in Figure 3-4. The MCMODE/SIZ1 signal determines if the microcontroller is operating in handshake mode or fixed timing mode; it is asserted high to select handshake mode. The COLDFIRE signal is only asserted high when the microcontroller interface is operating in ColdFire mode.
SLLS336B--August 2003 TSB12LV32, TSB12LV32I 27
Microcontroller Interface
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE D0 D1 D2 D3 A0 A1 A2 A3
Figure 3-3. Byte Handshake Read Figure 3-4 shows a word handshake read transaction. In this case, all 16 bits of the MD lines are used. Note that MD[0] contains the MSB and MD[15] contains the LSB. As in the byte read case, after MCA is asserted high another read or write transaction can begin after the next rising edge of BCLK.
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE A0 D0 D1 A1 D2 D3 A2 D4 D5 A3 D6 D7
Figure 3-4. Word Handshake Read
28 TSB12LV32, TSB12LV32I SLLS336B--August 2003
Microcontroller Interface
Byte handshake write and word handshake write are shown in Figure 3-5 and Figure 3-6. In this case, the microcontroller interface asserts MCA low immediately after MCS is sampled low. The data on the MD bus is valid when MCS and MWR are both low. The microcontroller interface keeps MCA low until it samples MCS high. For 8-bit accesses, the MD[0:7] lines are not used. If a transfer error condition occurs, TEA is asserted low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1 or M8BIT/SIZ0 line changes state during the access cycle.
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE D0 D1 D2 D3 A0 A1 A2 A3
Figure 3-5. Byte Handshake Write
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
29
Microcontroller Interface
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE A0 D0 D1 A1 D2 D3 A2 D4 D5 A3 D6 D7
Figure 3-6. Word Handshake Write
3.3.2 Microcontroller Fixed-Timing Mode
Byte fixed-timing reads and word fixed-timing reads are shown in Figure 3-7 and Figure 3-8, respectively. In addition to single byte or single word transfers, fixed-timing mode supports burst transfers. If MCS is asserted low for more than one BCLK cycle, burst mode is enabled. The fixed-timing burst mode does not have a limit on the maximum burst size allowed. The signal timing sequence for a fixed-timing read transaction can be summarized as follows: 1. The microcontroller pulses MCS low to signal the start of access. Pulsing MCS low for more than one clock cycle enables burst mode. The number of BCLK cycles during which MCS is asserted low determines the total burst size. 2. When the rising edge of BCLK samples MCS low and MWR high, the register value or GRF data pointed to by the MA bus is latched onto the MD lines. The MD lines latch on every rising edge of BCLK if MCS continues to be asserted low. The first data transfer of each fixed-timing read (single byte/word or burst) requires one extra BCLK cycle due to propagation delay in the device. In the case of a burst data transfer, all subsequent reads require only one BCLK cycle. The data on the MD bus is valid when MCA is low. 3. After 2 BCLK cycles, the TSB12LV32 pulses MCA low for one clock cycle to signal the completion of the requested operation. If MCS is pulsed low for n BCLK cycles, MCA also is pulsed low for n cycles. Note that MA needs only contain valid data during the first cycle in which MCS is low. Except for the first one, every data transfer takes only one BCLK cycle. If a read transaction is accessing the CFR, it may not cross any register boundary (see Section 3.3.2.1 for information on fixed-timing read access to the GRF). During a burst read or a burst write, the initial latched address on the MA bus is automatically incremented by the hardware for each additional read or write, and the value on the MA bus is ignored until the next transfer. After MCA is asserted high, another read or write transaction can begin after the next rising edge of BCLK. Note that data size is determined by the M8BIT/SIZ0 signal, it is asserted high to indicate a byte transfer and it is asserted low to indicate a word transfer. The MCMODE/SIZ1 signal is asserted low to select fixed timing mode.
30 TSB12LV32, TSB12LV32I SLLS336B--August 2003
Microcontroller Interface
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE D0 D1 D2 D3 D4 D5 D6 D7 D8 A0 A1 A2
Figure 3-7. Byte Fixed-Timing Read
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE A0 D0 D1 A1 D2 D3 D4 D5 D6 D7 D8 D9 A2 D10 D11 D12 D14 D16 D13 D15 D17
Figure 3-8. Word Fixed-Timing Read
SLLS336B--August 2003 TSB12LV32, TSB12LV32I 31
Microcontroller Interface
Byte fixed-timing write and word fixed-timing write are shown in Figure 3-9 and Figure 3-10, respectively. Unlike the fixed-timing read transfers, no extra wait cycles are required for fixed-timing write transfers. For an 8-bit data bus, MD[0:7] is not used (don't care) and is driven with zeros. If the write transaction is accessing a CFR register, it cannot cross any register boundary. The first write data for each ATF quadlet must start at byte0. Write accesses to the ATF must be quadlet aligned. The microcontroller interface waits for all bytes of each quadlet to be available before creating a write request to the ATF. If a transfer error condition occurs, TEA is asserted low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1 or M8BIT/SIZ0 lines transition during the access cycle.
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A0 A1 A2
Figure 3-9. Byte Fixed-Timing Write
32
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Microcontroller Interface
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE A0 D0 D1 A1 D2 D3 D4 D5 D6 D7 D8 D10 D12 D9 D11 D13 A2 D14 D16 D18 D20 D22 D24 D15 D17 D19 D21 D23 D25
Figure 3-10. Word Fixed-Timing Write
3.3.2.1
GRF READ in Fixed-Timing Mode
The timing requirements when performing a GRF read access in fixed-timing mode are different from timing requirements of a CFR read access in the fixed-timing mode. In fixed-timing mode, the GRF must be accessed only on a quadlet boundary. In other words, only quadlet fetches are legal. If the microinterface is configured for a byte access, this means that MCS must be asserted low for 4 BCLK cycles, as shown in Figure 3-11. If configured for word access, then MCS must only be asserted for 2 BCLK cycles, as shown in Figure 3-12. After MCA is driven high, another read or write transaction can begin after the next rising edge of BCLK.
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
33
Microcontroller Interface
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1
Figure 3-11. GRF Read Access (Byte Fixed-Timing Mode)
BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE A0 D0 D1 D2 D3 A1 D4 D5 D6 D7
Figure 3-12. GRF Read Access (Word Fixed-Timing Mode)
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Microcontroller Interface
3.3.3 Microcontroller ColdFire Mode
The TSB12LV32 supports a glueless interface to the ColdFire family of microcontrollers. To enable this mode, the COLDFIRE pin must be asserted and kept high for the entire access cycle. The timing diagram for a ColdFire read operation is shown in Figure 3-13. The timing sequence for a ColdFire read access can be summarized as follows: 1. The ColdFire pulses MCS low for one BCLK cycle to signal the start of access. MCS must only be asserted for one clock cycle. 2. When the rising edge of BCLK samples MCS low and MWR high, MD lines are enabled, but do not yet contain valid data. The MA lines should contain the address information at this point. MA is only required to be available for one BCLK cycle. The data transfer size is determined by the state of the MCMODE/SIZ1 and M8BIT/SIZ0 lines. 3. The TSB12LV32 pulses MCA low for n clock cycles to signal the requested operation is complete. The number n depends on the data transfer size specified by the MCMODE/SIZ1 and M8BIT/SIZ0 lines. The CFR register value or GRF memory data pointed to by the MA lines is latched onto the MD lines. MCA pulses for one clock cycle on every word (2-byte) transfer. The microinterface uses burst transfers if the MCMODE/SIZ1 and M8BIT/SIZ0 lines indicate more than 2-bytes (1 word) of data. The TSB12LV32 does not support 1-byte transfers in the ColdFire mode.
MCMODE/SIZ0 0 0 1 1 M8BIT/SIZ1 0 1 0 1 Transfer Size (Bytes) 4 2 1* 0
* A transfer size of 1 byte is not valid and TEA is asserted lo for one BCLK cycle.
If any transfer error condition occurs, TEA is asserted low for one BCLK cycle. An error condition can occur if the MCMODE/SIZ1 and M8BIT/SIZ0 lines specify a transfer size of 1 byte or if their state changes during the access cycle. Note that all 16 bits of the MD lines are always used in the ColdFire mode.
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BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE TEA A1 D1 D2 D3 D4 A2 A3 D5 D6
Figure 3-13. ColdFire Read The ColdFire write transaction is shown in Figure 3-14. Unlike the handshake and fixed-timing write modes, the ColdFire write operation requires the data on the MD lines be available one BCLK cycle after the address on the MA lines is sampled. Violating this timing requirement can result in a transfer error, causing TEA to be asserted low for one BCLK cycle.
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BCLK MWR MCS MCA MA[0:6] MD[0:7] MD[8:15] M8BIT/SIZ0 MCMODE/SIZ1 COLDFIRE TEA A1 D1 D2 D3 D4 A2 A3 D5 D6
Figure 3-14. ColdFire Write
3.3.4 Microcontroller Critical Timing
tsu4 tsu3 tsu2 tsu1 tsu0 BCLK MWR MCS td0 MCA MA[0:6] XX ADDRESS td2 MD[0:15] XXXX DATA td1 TEA M8BIT/SIZ0 MCMODE/SIZ1 XXXX DATA XXXX XX ADDRESS XX th1 th0 th4 th3 th2 tsu5 th5
Figure 3-15. Microcontroller Timing
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Table 3-3. Microcontroller Timing
PARAMETER td0 td1 td2 tsu0 tsu1 tsu2 tsu3 tsu4 tsu5 th0 th1 th2 th3 th4 TERMINAL NAME MCA Delay time (BCLK to Q) TEA MD[0:15] MWR MCS MA[0:6] Setup time to BCLK M8BIT/SIZ0 MCMODE/SIZ1 MD[0:15] MWR MCS Hold time from BCLK MA[0:6] M8BIT/SIZ0 MCMODE/SIZ1 MD[0:15] ACCESS TYPE Read/Write Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Write Read/Write Read/Write Read/Write Read/Write Read/Write Write MIN 3.75 3.75 2.5 4.5 6.5 6.5 5 3.5 3 1.75 1.5 2 1.5 1.75 1.5 ns ns MAX 9.5 9.5 10.5 ns UNIT
th5 All timing parameters are referenced to the rising edge of BCLK.
3.3.5 Endian Swapping
The term endianness refers to the way data is referenced and stored in a processor's memory. For example, consider a 32-bit processor; any 32-bit word consists of four bytes which can be stored in memory in one of two ways. Of the four bytes, either byte 3 is considered the most significant byte and byte 0 the least significant byte, or vice versa (see Figure 3-16 and Figure 3-17). A little endian type memory considers byte 0 the least significant byte, whereas a big endian type memory considers byte 3 to be the least significant byte.
Byte #0 (Most Significant Byte) Byte #1 Byte #2 Byte #3 (Least Significant Byte)
Figure 3-16. Big Endian Format
Byte #3 (Most Significant Byte) Byte #2 Byte #1 Byte #0 (Least Significant Byte)
Figure 3-17. Little Endian Format The TSB12LV32 configuration register space (CFR) and FIFO memory, both of which are 32 bits wide, use a big endian architecture. The TSB12LV32 uses the same endianness as the internal 1394a-2000 link core. This means that the most significant byte is the left-most byte (byte 0) and the least significant byte is the right-most byte (byte 3).
3.3.5.1
Data and Address Invariance for Little Endian Processors
For little-endian processors, there are two modes of byte swapping, address invariant and data invariant. Address invariance preserves byte ordering between the internal system (GP2Lynx registers and FIFO) and external system (microcontroller/processor). Data invariance preserves the bit significance of the data, but changes the byte significance between the internal and external systems. The MDINV pin controls how the write/read data is swapped at the data bus (i.e., determines how the received bytes from the microcontroller are mapped into the TSB12LV32 internal registers and memory space). Note that when the COLDFIRE pin is high, the MDINV pin has no affect and data is always interpreted as big endian. See Endianness and the TSB12LV41 (MPEG2Lynx) Microprocessor Interface, TI literature number SLLA021, for a detailed description of endianness. The pin settings for all the swapping operations are shown in Table 3-3. Note that in performing the byte swapping operation in the little-endian mode, only the two least significant bits of the 32-bit address inside are involved. This is because there is a total of four bytes associated with the swapping operation.
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Table 3-4. Endian Swapping Operations
LENDIAN 0 1 M8BIT/SIZ0 X 1 (8-bits wide) MDINV X 1 DESCRIPTION Big-endian mode, no manipulation on byte address and data bytes Little-endian data invariance mode, swap the low order 2 bit address: External low-order 2-bit address Internal low order 2-bit address Byte Address 00 Byte Address 11 Byte Address 01 Byte Address 10 Byte Address 00 Byte Address 11 Byte Address 11 Byte Address 00 Little-endian data invariance mode, swap the low order 2 bit address: External low-order 2-bit address Internal low order 2-bit address Word Address 00 Word Address 10 Word Address 10 Word Address 00 16-bit little-endian address invariance mode, swap data between MD[0:7] and MD[8:15]. 8-bit little-endian address invariance mode, no manipulation on byte address and data bytes.
1
01 (16-bits wide)
1
1 1
1 1
0 0
Because the TSB12LV32 microprocessor interface is either 8 bits or 16 bits wide, but the internal configuration registers are 32 bits wide, a byte stacking (for writes) and a byte unstacking (for reads) operation must be performed on the data bus. For little endian processors, the TSB12LV32 can perform the swapping of bytes on the data bus required to allow both the processor and the TSB12LV32 to interpret the data the same. There are two methods of swapping the data bytes, address invariant and data invariant. Both of these methods are described in the following sections. NOTE: For the host processor to work correctly with the TSB12LV32, users must correctly connect the address and data busses of their microprocessor to the TSB12LV32 microprocessor port. Users must connect the MSB (most significant bit) of their address/data bus to the address/data MSB of the TSB12LV32. This must be done regardless of bit number labeling or which type of endianness the microprocessor uses.
3.3.5.2
Data-Invariant System Design
Figure 3-18 shows a little-endian data-invariant system design example. In this system, the actual value of the data as it was stored in the processor memory is preserved. Data-invariant designs do not preserve the addresses when mapping between endian domains. If the data represents an integer, it is interpreted the same by both systems. If the data represents a string, an array, or some other type of byte indexed structure, it is interpreted differently by both systems.
Byte 3 (MSByte) Little Endian Processor Memory aa Byte 2 Byte 1 Byte 0 (LSByte) dd
bb
cc
TSB12LV32 CFR/Memory
dd (MSByte) Byte 0
cc
bb
aa (LSByte) Byte 3
Byte 1
Byte 2
Figure 3-18. Little-Endian Data-Invariance Illustration Chart
3.3.5.3
Address Invariant System Design
Figure 3-19 shows a little-endian address-invariant system design example. In this case, the byte ordering between both systems is preserved (i.e., byte address is preserved). For example, byte 3 in the little-endian processor memory is also byte 3 in the TSB12LV32 CFR space. As Figure 3-19 shows, the byte ordering is automatically maintained by the TSB12LV32 when in the address-invariance mode by swapping the order in which the incoming bytes on the microprocessor are written to the CFRs.
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Byte 3 (MSByte) Little Endian Processor Memory aa
Byte 2
Byte 1
Byte 0 (LSByte) dd
bb
cc
TSB12LV32 CFR/Memory
dd (MSByte) Byte 0
cc
bb
aa (LSByte) Byte 3
Byte 1
Byte 2
Figure 3-19. Little-Endian Address-Invariance Illustration Chart
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Link Core
4
Link Core
This section describes the link core components and operations. Figure 4-1 shows the link core components.
Transmitter
Cycle Timer CRC Cycle Monitor Physical Interface
Receiver
Figure 4-1. Link Core Components
4.1
Physical Interface
The physical (Phy) interface provides Phy-level services to the transmitter and receiver. This includes gaining access to the serial bus, sending packets, receiving packets, and sending and receiving acknowledge packets. The Phy interface module also interfaces to the Phy chip and implements Texas Instruments patent-pending bus-holder galvanic isolation.
4.2
Transmitter
The transmitter retrieves data from either the asynchronous transmit FIFO (ATF) or the data-mover (DM) port and creates correctly formatted 1394 packets to be transmitted through the Phy interface. When data is present at the ATF interface to the transmitter, the TSB12LV32 Phy interface arbitrates for the 1394 bus and sends an asynchronous packet. When data is present at the DM port, the TSB12LV32 requests bandwidth during the next isochronous cycle from the 1394 bus isochronous resource master if the packet is isochronous or arbitrates for the 1394 bus if the packet is asynchronous. The transmitter autonomously sends the cycle-start packets when the device is a cycle master.
4.3
Receiver
The receiver takes incoming data from the Phy interface and determines if the incoming data is addressed to the node. When the incoming packet is addressed to the node, the CRC of the packet is checked. If the header CRC is good, the header is confirmed in the general receive FIFO (GRF). For asynchronous stream packets and isochronous packets, the remainder of the packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last quadlet of the packet is confirmed into the GRF. The status quadlet contains the error code for the packet. In the case of asynchronous packets, the error code is the acknowledge code that is sent (returned) for that packet. For isochronous and broadcast packets that do not need acknowledge packets, the error code is the acknowledge code that would have been sent. This acknowledge code tells the transaction layer whether or not the data CRC is good or bad. If the header CRC is bad, the header is flushed and the rest of the packet is ignored. When a cycle-start packet is received, it is detected and the cycle-start packet data is sent to the cycle timer. Cycle-start packets are not placed in the GRF like other quadlet packets.
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4.4
Cycle Timer
The cycle timer is only used by nodes that support isochronous data transfer. The cycle timer is a 32-bit cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as defined by the IEEE 1394-1995 specification. In the TSB12LV32, the cycle-timer register is implemented in the cycle timer located in the IEEE 1212 initial register space at location 200h and can also be accessed through the local bus at TSB12LV32 CFR address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which increments once every 24.576-MHz clock period (or 40.69 ns). The next 13 higher-order bits are a count of 8,000 Hz (or 125 s) cycles, and the highest 7 bits count seconds. The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle offset, cycle count, and seconds count. The cycle timer has two possible sources. First, when the cycle source (CYSRC) bit in the configuration register (bit 21 of the control CFR at 08h) is set, then the CYCLEIN input terminal causes the cycle count field to increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros. CYCLEIN should only be the source when the node is the cycle master. The timer can also be disabled using the cycle-timer-enable bit (CYTEN) in the control register. The second cycle-source option is when the CYSRC bit is cleared. In this state, the cycle-offset field of the cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the reception of the cycle-start packet for the noncycle master nodes. The cycle-offset field in the cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal isochronous cycle of 125 s. The cycle-start bit is set when the cycle-start packet is sent from the cycle master node or received by a noncycle master node.
4.5
Cycle Monitor
The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes device activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent, the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the cyclemaster bit (CYMAS) is set in the control register.
4.6
Cyclic Redundancy Check (CRC)
The CRC module generates a 32-bit CRC for error detection. This is done for both the header and the data. The CRC module generates the header and data CRC for transmitting packets and checks the header and data CRC for received packets (see the IEEE 1394-1995 standard for details on the generation of the CRC).
4.7
Received Packet Routing Control Logic
Asynchronous and isochronous receive packets can be routed to the DM port or the GRF depending on the setting of the receiver routing control logic. Bit IRCVALL in the isochronous port CFR at 18h must be set for all isochronous data to be routed according to Table 4-1. Note that self-ID packets and Phy packets are always received by the GRF regardless of the routing control settings.
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Link Core
Table 4-1. Receiver Routing
AR0 0 AR1 0 DMASYNC X X 0 1 1 X 0 1 0 X 0 1 DMRX 0 1 1 0 1 0 1 1 DATA MOVER (DM) Receives no data; Power-on default Receives read response packets with a tlabel of 11XXXX Receives asynchronous data Receives no data Receives isochronous/asynchronous stream packet Receives no data Receives no data Receives addressed write-request asynchronous packets in the address range of 0000 0000 0000h to 0000 FFFF FFFFh Receives no data Receives all data (asynchronous and isochronous) GENERAL-RECEIVE FIFO (GRF) Receives all data (asynchronous and isochronous); power-on default Receives all other asynchronous packets and isochronous packets Receives isochronous/asynchronous stream packet Receives all data Receives asynchronous data Receives all data Receives all data Receives addressed asynchronous packets in the address range of 0001 0000 0000h to FFFF FFFF FFFFh. Also receives any asynchronous packets not going to the DM port regardless of the address. Receives isochronous packets too. Receives all data Receives no data
1
1
X X
0 1
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Data-Mover Port Interface
5
Data-Mover Port Interface
The data-mover (DM) port in the TSB12LV32 is the physical medium by which autonomous data streams of different types are piped to/from an application that uses the TSB12LV32. The DM port is meant to support an external memory interface that supplies or accepts large data packets. The DM port can support three types of packets: * * * Asynchronous Isochronous Asynchronous stream packets (1394a-2000 supported format)
The DM port can be configured to either transmit data (asychronous packets or isochronous packets) or receive data (asychronous and/or isochronous) at one time (half duplex). A typical system diagram is shown in Figure 5-1:
Application Stream Process (External Memory Interface) Data-Mover I/F Phy/Link I/F
TSB12LV32
Phy
Processor/Controller (ColdFire)
Microcontroller Interface
Figure 5-1. A Typical System Diagram The DM port performs all operations synchronously, using a 24.576-MHz output clock called DMCLK. DMCLK is essentially SCLK/2. There is no asynchronous logic within the DM block. All data transfers are synchronized to the DMCLK output. The DM operates by setting the DM control CFR at 04h and the control CFR at 08h. The DM logic module interfaces internally with the configuration register (CFR) block and the link core (Link) block and interfaces externally with the data-mover external interface. The advantages of the DM port can be summarized as follows: * * * * Transmits or receives large blocks of data at speeds up to 400 Mbps. Allows for a large external FIFO specific to an individual application. Handles asynchronous, isochronous, or asynchronous stream packets. The DM interface goes to the high-impedance-state when not in use.
The DM isochronous transmit reads data from the DM interface (DMD[0:15] lines) and passes it to the 1394 isochronous transmit interface in accordance with Figure 5-2. The data path is shown in Figure 5-3.
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No
Isochronous DM Idle (DMDONE Is High) DMEN Is 1, DMASYNC Is 0 DMREADY Is High? Yes
No
Isochronous DM Go (DMDONE Is Low) New Isochronous Cycle Started?
Yes
Isochronous Arbitrate/Xmit (DMDONE Is Low) Arbitrate for Isochronous Transmit and Send One Isochronous Packet
No
All Channels Done (DMDONE Is Low) End of All Channels? Yes
No
Data Block Done (DMDONE Is Low) End of All Packets for This Data Block? Yes No
Handshake Mode? Yes Handshake (DMDONE Is High) DMREADY Is Low?
Yes
No
Figure 5-2. Isochronous Transmit DM Flow Control (TSB12LV32 Transmit to 1394 Bus)
MSB LSB
Data-Mover Data DMD[0:15]
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
1394 Packet Data
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 . . . Bit 31
Figure 5-3. Transmit Data Path The DM asynchronous transmit reads data from the DM interface (DMD[0:15] lines) and passes it to the 1394 asynchronous interface in accordance with Figure 5-4.
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Asynchronous DM Idle (DMDONE Is High) DMEN is 1, DMASYNC is 0 DMREADY Is High? Yes Asynchronous Arbitrate/Xmit (DMDONE Is Low) Arbitrate for Asynchronous Transmit and Send Asynchronous Packet
No
Wait for Acknowledge Ack Complete received? Yes No Data Block Done (DMDONE Is Low) End of All Packets for This Data Block? Yes
No
DM Disabled Re-enable via Software
Figure 5-4. Asynchronous Transmit DM Flow Control (TSB12LV32 Transmit to 1394 Bus) (DMASYNC = 1)
5.1
Data-Mover Data Flow Diagram
The data mover has eight modes of operation. There are four modes for transmit and four modes for receive. * * * * * * * * Isochronous receive with automatic header / trailer removal Isochronous receive without automatic header / trailer removal Isochronous transmit with automatic header insertion Isochronous transmit without automatic header insertion Asynchronous receive with automatic header / trailer removal Asynchronous receive without automatic header / trailer removal Asynchronous transmit with automatic header insertion Asynchronous transmit without automatic header insertion
Definitions * Data-mover port configured to operate in transmit mode means that the packet data is received through the data-mover port and forwarded (unbuffered) to the link core transmit logic to be sent to the physical layer device (Phy), which, in turn, transmits the data onto the 1394 bus. Data-mover port configured to operate in receive mode means that the packet data is received by the link core receive logic from the 1394 bus through the Phy. The data is then routed by the link core to the data-mover port without any internal buffering.
*
5.1.1 Isochronous Receive
In both the isochronous receive modes, the packet header information is always loaded into the header registers in the CFR. The isochronous packet header quadlet is loaded into the header0 register at 38h and the isochronous packet trailer quadlet is loaded into the trailer register at 48h.
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5.1.1.1
Isochronous Packet Receive With Automatic Header and Trailer Removal
Isochronous packet is received through the receiver logic of the link core. The packet header is stripped off from the packet and loaded into the header0 register at 38h. Packet data (payload only) is routed directly to the DM port without any buffering. Trailer quadlet is loaded into the trailer register at 48h.
CFR REGISTER
Step 1: Step 2: Step 3: Step 4:
Header0 Register at 38h Step 2 Trailer Register at 48h LINK CORE
Transmitter
DataMover Port
Step 4 Receiver Step 3 (Packet Data)
Step 1 Packet Received From 1394 Bus Through the Phy
Figure 5-5. Isochronous Receive With Auto Header and Trailer Removal
5.1.1.2
Isochronous Packet Receive With Header and Trailer
Isochronous packet is received through the receiver block of the link core. The header quadlet is both loaded into the header0 register at 38h and routed to the DM port without any buffering. Packet data (payload only) is sent directly through the DM port only. Trailer quadlet is loaded into the trailer register at 48h. It is also forwarded to the DM port.
CFR REGISTER
Step 1: Step 2: Step 3: Step 4:
Header0 Register at 38h
Step 2 LINK CORE Step 4
Trailer Register at 48h Transmitter
DataMover Port
Step 4 (Trailer Quadlet) Step 3 (Packet Data) Step 2 (Header Quadlet)
Step 1 Receiver Packet Received From 1394 Bus Through the Phy
Figure 5-6. Isochronous Receive With Header and Trailer
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5.1.2 Isochronous Transmit
There are two ways (modes of operation) to transmit isochronous data through the data mover: * Isochronous packet transmit with automatic header insertion. * Isochronous packet transmit without automatic header insertion. The difference between the two modes lies in the mechanism with which the header information is inserted into the data stream. However, in both cases the header information is always loaded into the link core transmitter from the header register starting with the CFR at 38h. There are no trailers for tranmitted packets. NOTE: With a camera application, if the sync bit field in the isochronous header quadlet needs to be changed more than once during the transmission of a data block (i.e. one frame), the header information must be applied manually through the data-mover port.
5.1.2.1
Isochronous Packet Transmit With Automatic Header Insertion
CFR REGISTER LINK CORE
Step 1 Write Header Information
MicroStep 1 controller Header Interface Loaded
Header0 Register at 38h
Step 2
Step 4 Transmitter Packet Sent to 1394 Bus Through the Phy
Step 3 Step 3 (Packet Data) DataMover Port (Packet Data)
Receiver
Figure 5-7. Isochronous Transmit With Auto Header Insertion In this mode, the isochronous header information is first loaded into the Header0 Register at 38h through the microcontroller interface. Subsequently, the header is inserted automatically into the data once the data mover starts streaming data through to the link core transmitter logic. The following steps further illustrate the process: Step 1: Isochronous header quadlet is loaded into the header0 register at 38h through a write operation from the microcontroller interface. Step 2: Step 3: Step 4: Header quadlet is forwarded to the transmitter of the link core. Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link core. Isochronous packet is sent to the 1394 bus through the Phy.
NOTE: The data coming through the data-mover port is typically supplied by an external fast memory block (i.e., FIFO, DRAM). This external memory logic can begin transmitting data through to the data-mover port exactly one DMCLK cycle after the DMPRE output pin on the GP2Lynx is asserted high.
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5.1.2.2
Isochronous Packet Transmit Without Automatic Header Insertion
In this mode, both the packet header and data payload is loaded through the data-mover port. This mode is sometimes called isochronous packet transmit with manual header insertion. This is because the header quadlet is not preloaded into the header0 register via the microcontroller interface. Instead, it is inserted manually into the data stream at the same time as the rest of the packet. The following steps further illustrate the process: Step 1: Step 2: Step 3: Step 4: Isochronous header information (only one header quadlet in this case) is fetched into the header0 register at 38h through the data-mover port. Header quadlet is forwarded to the transmitter of the link core. Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link core. Isochronous packet is sent to the 1394 bus through the Phy.
CFR REGISTER
Step 1 (Header Fetched) Header0 Register at 38h Step 2 LINK CORE Step 4 Transmitter Step 3 (Packet Data) Step 1 (Header Supplied) Step 3 (Packet Data) Packet Sent to 1394 Bus Through the Phy
DataMover Port
Receiver
Figure 5-8. Isochronous Transmit Without Auto Header Insertion
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Data-Mover Port Interface
5.1.3 Asynchronous Receive
In both the asynchronous receive modes, the packet header information is always loaded into the header registers in the CFR. In quadlet receive mode, the first three header quadlets are loaded into the header0 register at 38h, header1 register at 3Ch, and header2 register at 40h, respectively. In block receive mode, an additional step is performed, loading the fourth header quadlet received into the header3 register at 44h. The trailer quadlet always is loaded into the trailer register at 48h.
5.1.3.1
Asynchronous Packet Receive With Automatic Header and Trailer Removal
Asynchronous packet is received through the receiver logic of the link core The packet headers are stripped from the packet and loaded into the header registers: a) If in quadlet receive mode, the three header quadlets are loaded into the header0-header2 registers. b) If in block receive mode, the four header quadlets are loaded into the header0-header3 registers.
Step 1: Step 2:
Step 3: Step 4:
Packet data (payload only) is routed directly to the DM port without any buffering. Trailer quadlet is loaded into the trailer register at 48h.
CFR REGISTER Quadlet#0 Quadlet#1 Quadlet#2 Quadlet#3 Step 2 Trailer Register at 48h Step 4 LINK CORE
Header0 Register at 38h Loaded Only in Block Receive Header1 Register at 3Ch Header2 Register at 40h Header3 Register at 42h
Transmitter
Step 1 DataMover Port Step 3 (Packet Data) Receiver Packet Received From 1394 Bus Through the Phy
Figure 5-9. Asynchronous Receive Without Header and Trailer Removal
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5.1.3.2
Asynchronous Packet Receive With Headers and Trailer
Asynchronous packet is received through the receiver logic of the link core. The header quadlets are loaded into their respective header registers and routed to the DM port without any buffering. Packet data is routed directly to the DM port (no buffering performed). Trailer quadlet is loaded into the trailer register at 48h and routed to the DM port.
CFR REGISTER
Step 1: Step 2: Step 3: Step 4:
Header0 Register at 38h Loaded Only in Block Receive Header1 Register at 3Ch Header2 Register at 40h Header3 Register at 42h
Quadlet#0 Quadlet#1 Quadlet#2 Quadlet#3 Step 2
Trailer Register at 48h
Step 4 LINK CORE
Transmitter
DataMover Port
Step 4 (Trailer Quadlet) Step 3 (Packet Data) Step 2 (Header Quadlet)
Step 1 Receiver Packet Received From 1394 Bus Through the Phy
Figure 5-10. Asynchronous Receive With Headers and Trailer
5.1.4 Asynchronous Transmit
There are two ways (modes of operation) to transmit asynchronous data through the data mover: * * Asynchronous packet transmit with automatic header insertion Asynchronous packet transmit without automatic header insertion
The difference between the two modes lies in the mechanism with which the header information is inserted into the data stream. However, in both cases, the header information is always loaded into the link core transmitter from the header registers starting with the CFR at 38h. There are no trailers for transmitted packets.
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5.1.4.1
Asynchronous Packet Transmit With Automatic Header Insertion
In this mode, the header information is first loaded into the header0-header3 registers through the microcontroller interface. The headers subsequently are inserted automatically into the data once the data mover starts streaming data through to the link core transmitter logic. The following steps further illustrate the process: Step 1: Asynchronous header quadlets (3 quadlets in quadlet mode and 4 quadlets in block mode) are loaded into the header0-header3 registers through a write operation from the microcontroller interface. Loading each header quadlet requires a single write operation. Step 2: Header quadlets are forwarded to the transmitter of the link core. Step 3: Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link core. Step 4: Asynchronous packet is sent to the 1394 bus through the Phy. NOTE: The data coming through the data-mover port is typically supplied by an external fast memory block (i.e., FIFO, DRAM). This external memory logic can begin transmitting data through to the data-mover port exactly one DMCLK cycle after the DMPRE output pin on the GP2Lynx is asserted high.
CFR REGISTER
Header0 Register at 38h Step 1 Write Header Quadlets MicroStep 1 controller Headers Interface Loaded Header1 Register at 3Ch Header2 Register at 40h Header3 Register at 42h
Quadlet#0 Quadlet#1 Quadlet#2 Quadlet#3 Step 2
Loaded Only in Block Transmit
LINK CORE Step 4 Transmitter Step 3 Packet Sent to 1394 Bus Through the Phy
Step 3 (Packet Data)
DataMover Port
Receiver
Figure 5-11. Asynchronous Transmit With Auto Header Insertion
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5.1.4.2
Asynchronous Packet Transmit Without Automatic Header Insertion
In this mode, the packet headers and data information are loaded through the data-mover port. This mode is sometimes called asynchronous packet transmit with manual header insertion. This is because the header quadlets are not preloaded into the header registers via the microcontroller interface. Instead, they are inserted manually into the data stream at the same time as the rest of the packet. The following steps further illustrate the process: Step 1: Asynchronous header quadlets (3 quadlets in quadlet mode and 4 quadlets in block mode) are fetched into the header registers through the data-mover port. Step 2: The header quadlets are then forwarded to the transmitter of the link core. Step 3: Packet data (payload only) is transmitted through the data mover directly to the transmitter of the link core. Step 4: Asynchronous packet is sent to the 1394 bus through the Phy.
CFR REGISTER
Header0 Register at 38h Header1 Register at 3Ch Step 1 (Headers Fetched) Header2 Register at 40h Header3 Register at 42h
Quadlet#0 Quadlet#1 Quadlet#2 Quadlet#3 LINK CORE Step 2 Step 4 Transmitter
Step 3 (Packet Data) Step 1 (Headers Supplied) Step 3 (Packet Data) DataMover Port Receiver
Packet Sent to 1394 Bus Through the Phy
Figure 5-12. Asynchronous Transmit Without Auto Header Insertion
5.2
Data-Mover Modes of Operation
The data-mover (DM) port in the GP2Lynx is meant to handle an external memory interface that supplies or accepts large data packets. The port can be configured to either transmit or receive data packets. The data can be either asynchronous or isochronous packets. All traffic through the data mover is synchronous to the rising edge of DMCLK. DMCLK is an output signal at 24.576 MHz. The data mover operates by setting bits within the DM control register at 04h. The data mover has eight modes of operation which are specified by the DMASYNC, DMHDR, and DMRX bits in the DM control register at 04h. Table 5-1 shows all the DM modes of operation.
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Table 5-1. Modes of Operation
DMASYNC 0 0 0 0 1 1 1 1 DMHDR 0 0 1 1 0 0 1 1 DMRX 0 1 0 1 0 1 0 1 MODE OF OPERATION Isochronous packet transmit with auto header insertion Isochronous packet receive with auto header and trailer removal Isochronous packet transmit without auto header insertion Isochronous packet receive with header and trailer Asynchronous packet transmit with auto header insertion Asynchronous packet receive with auto header and trailer removal Asynchronous packet transmit without auto header insertion Asynchronous packet receive with headers and trailer
5.2.1 Isochronous Transmit With Automatic Header Insertion
Upon receiving a high on DMREADY, the following sequence of operations is performed: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: DMDONE is asserted low (deactivated) at the next DMCLK cycle. The data mover takes the header that has been loaded into the header0 register at 38h and requests the link core to transmit the data onto the 1394 bus. The link core fetches the header from the header0 register. DMPRE pulses for one DMCLK cycle before the first data quadlet is accepted by GP2Lynx from the external device. The data mover then begins to fetch the data payload by asserting DMRW high. When the link core has fetched the last data quadlet, the data mover checks the number of channels specified in the CHNLCNT field in the DM control register at 04h to verify whether a data packet has been sent on each isochronous channel. If all channels have been sent, the data mover waits for a subaction gap to occur before asserting DMDONE high to indicate the end of the cycle. Otherwise the data mover provides the header in the next header register and then begins fetching the data payload until all channels are complete. A data packet must be sent on each active isochronous channel.
The timing diagrams in Figure 5-13 through Figure 5-15 illustrate this mode of operation at different transmit speeds. For simplification, these diagrams show three quadlets of data payload.
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-13. Isochronous Transmit With Auto Header Insertion at 400 Mbps
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-14. Isochronous Transmit With Auto Header Insertion at 200 Mbps
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DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-15. Isochronous Transmit With Auto Header Insertion at 100 Mbps
5.2.2 Isochronous Transmit Without Automatic Header Insertion
Upon receiving a high on DMREADY, the following sequence of operations is performed: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: DMDONE is driven low (deactivated) at the next DMCLK cycle. DMPRE pulses for one DMCLK cycle before the first header quadlet is is accepted from lthe external device. The data mover fetches the header by asserting DMRW high. The data mover then loads the header into the header0 register and requests the data to be transmitted out on the 1394 bus by the link core. The link fetches the header from the header0 register. DMPRE pulses for one DMCLK cycle before the first data quadlet is is accepted from the external device. The data mover then begins to fetch the data payload by asserting DMRW high. When the link core has fetched the last data quadlet, the data mover checks the number of channels specified in the CHNLCNT field in the DM control register to verify whether a data packet has been sent on each isochronous channel. If all channels have been sent, the data mover waits for a subaction gap to occur before asserting DMDONE high to indicate the end of the cycle. Otherwise the data mover provides the header in the next header register and then begins fetching the data payload until all channels are complete. A data packet must be sent on each active isochronous channel.
Figure 5-16 shows the timing diagram for this mode at a data transmit rate of 400 Mbps. The dashed sections indicate repetitive behavior (when the payload is more than two quadlets long).
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-16. Isochronous Transmit Without Auto Header Insertion
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Data-Mover Port Interface
5.2.3 Isochronous Packet Receive With Automatic Header and Trailer Removal
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of operations is performed: Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE is asserted high for one DMCLK cycle. After the header is sent through, DMDONE is asserted high for one DMCLK cycle. DMRW is then asserted high as the data payload comes through. After all data has been transmitted on the DMD[0:15] lines, DMRW is asserted low and the trailer quadlet then comes out on the DMD[0:15] lines.
Step 2: Step 3:
PKTFLAG is never asserted high in this mode. Figure 5-17 shows the timing diagram for this mode at 400 Mbps. Figure 5-17 shows the case where DMPRE is asserted high for one DMCLK cycle to indicate that the sync bits of the received isochronous header match the contents of the ISYNCRCVN field.
DMCLK DMRW DMD[0:15] PKTFLAG DMDONE DMPRE
Header Quadlet Trailer Quadlet
Figure 5-17. Isochronous Receive With Automatic Header and Trailer Removal
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5.2.4 Isochronous Packet Receive With Header and Trailer
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence of operations is performed: Step 1: The packet router control logic routes the packet to the data mover. If the sync bit field in the header quadlet matches a bit pattern in the ISYNCRCVN field of the isochronous port register at 18h, DMPRE is asserted high for one DMCLK cycle. At the same time, DMDONE is asserted high for one DMCLK cycle. This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only asserted high when the header quadlet is being received. After all the data payload has been transmitted on the DMD[0:15] lines, PKTFLAG is asserted high again as the trailer quadlet is being transmitted. Once the entire packet is transmitted, the DMRW line is asserted low.
Step 2: Step 3:
Figure 5-18 shows the timing diagram for this mode at 400 Mbps. Also, Figure 5-18 shows the case where DMPRE is asserted high for one DMCLK cycle to indicate that the sync bits of the received isochronous header matches the contents of the ISYNCRCVN field.
DMCLK DMRW DMD[0:15]
Header Quadlet Trailer Quadlet
PKTFLAG DMDONE DMPRE
Figure 5-18. Isochronous Receive With Header and Trailer Figure 5-19 shows the timing diagram at 200 Mbps when the received packet contains only one quadlet of payload.
DMCLK DMRW DMD[0:15]
0000 0000
Header Quadlet
Packet Payload Trailer Quadlet
PKTFLAG DMDONE DMPRE
Figure 5-19. Isochronous Receive With Header and Trailer at 200 Mbps
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5.2.5 Asynchronous Packet Transmit With Automatic Header Insertion
Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is performed: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: DMDONE is asserted low (deactivated) at the next DMCLK cycle. The data mover takes the headers that have been loaded into the header0-header3 registers and requests the link core to transmit the data onto the 1394 bus. The link core fetches the headers from the header0-header3 registers. DMPRE pulses for one DMCLK cycle before the first data quadlet is accepted from the external device on the DM port. The data mover then begin sto fetch the data payload by asserting DMRW high. When the link core has fetched the last data quadlet, the data mover waits until the destination node returns an ack_complete immediate response. If an ack_complete is not received, the data mover asserts DMERROR high and becomes disabled.
Figure 5-20, Figure 5-21, and Figure 5-22 show the timing diagram for this mode for the quadlet transmit and the block transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5-20. Figure 5-22 shows the block transmit case at 400 Mbps.
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-20. Asynchronous Quadlet Transmit With Automatic Header Insertion
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-21. Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-22. Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps
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5.2.6 Asynchronous Packet Transmit Without Automatic Header Insertion
Upon receiving a high signal on DMREADY from the external logic, the following sequence of operations is performed: Step 1: Step 2: Step 3: Step 4: Step 5: Step 6: Step 7: Step 8: DMDONE is asserted low (deactivated) at the next DMCLK cycle. DMPRE pulses for one DMCLK cycle before the header quadlets are accepted from the external device on the DM port. The data mover fetches the headers by asserting DMRW high. The data mover then loads the headers into the header0-header3 registers and requests the data to be transmitted out on the 1394 bus by the link core. The link fetches the headers. DMPRE pulsees for one DMCLK cycle before the first data quadlet is accepted from the external device on the DM port. The data mover then begins to fetch the data payload by asserting DMRW high. When the link core has fetched the last data quadlet, the data mover waits until the destination node returns an ack_complete immediate response. If an ack_complete is not received, the data mover asserts DMERROR high and becomes disabled.
Figure 5-23 and Figure 5-24 show the timing diagram for this mode for the quadlet transmit and the block transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5-24.
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Header Quadlets Data Quadlet
Figure 5-23. Asynchronous Quadlet Transmit Without Automatic Header Insertion at 400 Mbps
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Header Quadlets Data Quadlets
Figure 5-24. Asynchronous Block Transmit Without Automatic Header Insertion at 400 Mbps
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Data-Mover Port Interface
5.2.7 Asynchronous Packet Receive With Headers and Trailer
In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence of operations is performed: Step 1: Step 2: Step 3: The packet router control logic routes the packet to the data mover. At the same time, DMDONE is asserted high for one DMCLK cycle. This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only asserted high when the header quadlets are being received. After all the data payload has been received on the DMD[0:15] lines, PKTFLAG is asserted high again as the trailer quadlet is being received. Once the entire packet is received, the DMRW line is asserted low.
Figure 5-25 and Figure 5-26 show the timing diagram for this mode for the quadlet receive and the block receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5-26.
DMCLK DMRW DMD[0:15] PKTFLAG DMDONE
Figure 5-25. Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps
DMCLK DMRW DMD[0:15] PKTFLAG DMDONE
Figure 5-26. Asynchronous Block Receive With Headers and Trailer at 400 Mbps
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5.2.8 Asynchronous Packet Receive With Automatic Header and Trailer Removal
In this mode, when the link receives an asynchronous packet that is addressed to it, the following sequence of operations is performed: Step 1: Step 2: Step 3: The packet router control logic routes the packet to the data mover. After the headers are sent through, DMDONE is asserted high for one DMCLK cycle. DMRW is then asserted high as the data payload comes through. After all data has been received on the DMD[0:15] lines, DMRW is asserted low and the trailer quadlet then comes out on the DMD[0:15] lines.
Figure 5-27 and Figure 5-28 show the timing diagram for this mode for the quadlet receive and the block receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5-28.
DMCLK DMRW DMD[0:15] PKTFLAG DMDONE
Figure 5-27. Asynchronous Quadlet Receive With Automatic Header and Trailer Removal at 400 Mbps
DMCLK DMRW DMD[0:15] PKTFLAG DMDONE
Figure 5-28. Asynchronous Block Receive With Automatic Header and Trailer Removal at 400 Mbps
5.3
Data-Mover Byte Mode
In this mode the DMD lines are only 1 byte wide when the maximum speed is 200 Mbps. Only the DMD[0:7] bits are used for the data bus. DMERROR is asserted if transmission of a 400-Mbps packet is attempted.
5.4
Data-Mover Endian Swapping
In this mode the DMD[0:15] bytes are swapped. If the data mover is in byte mode, the least significant byte is fetched first (Figure 5-29). If the data mover is not in byte mode, the least significant word is fetched first and the byte order is then swapped (Figure 5-30).
DMCLK DMRW DMD[0:15]
01 02 03 04 A1 B2 C3 D4 A1B2C3D4 D4C3B2A1
NORM_LINK_DATA SWAP_LINK_DATA
01020304 04030201
Figure 5-29. Endian Swapping in Byte Mode
DMCLK DMRW DMD[0:15] NORM_LINK_DATA SWAP_LINK_DATA
0102 0304 A1B2 C3D4
Figure 5-30. Endian Swapping in Word Mode
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5.5
Data-Mover Handshake Mode
In this mode, when DMDONE is asserted high the data-mover port interface checks for DMREADY low as an acknowledge. This is equivalent to the mode used in the TSB12LV31 (GPLynx), as shown in Figure 5-31.
DMCLK DMRW DMD[0:15] DMREADY DMPRE DMDONE
Figure 5-31. Data-Mover Handshake Mode (GPLynx Mode)
5.6
Data-Mover Critical Timing
th0 tsu0 DMCLK tsu1 th1
td0 DMDONE
td1 DMRW td2 DMPRE
td3 DMERROR
td4 PKTFLAG DMREADY
td5 DMD[0:15]
XXXX DATA XXXX DATA
Figure 5-32. Clock-to-Output Timing With Respect to DMCLK Table 5-2. CLK-to-Output Timing With Respect to DMCLK
PARAMETER td0 td1 td2 td3 td4 td5 tsu0 tsu1 Setup time to DMCLK Delay time (DMCLK to Q) TERMINAL NAME DMDONE DMRW DMPRE DMERROR PKTFLAG DMD[0:15] DMREADY DMD[0:15] DMREADY DMD[0:15] MIN 1.75 1.75 1.75 1.5 1.75 0.5 14 14 1 0.75 ns ns MAX 8.5 7.5 14.5 11.5 8.5 9 ns UNIT
th0 Hold time from DMCLK th1 All timing parameters are referenced to the rising edge of DMCLK.
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FIFO Memory Access
6
FIFO Memory Access
The TSB12LV32 FIFO interfaces with the microcontroller, the CFR and the 1394 link layer controller (LLC). The FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each of 520 quadlets (2 Kbytes). The FIFO provides storage for transmit packets (ATF) and receive packets (GRF). When an asynchronous packet is confirmed into the ATF, the transmitter of the LLC requests the 1394 bus to send the asynchronous packet. When a received packet is confirmed into the GRF by the receiver of the LLC without any errors, interrupt RXGRFPKT in the interrupt register at 0Ch is triggered so the microcontroller interface can read the received data from the GRF. Access to all FIFO memories is fundamentally the same, only the address written to changes. Figure 6-1 shows the FIFO-address access map.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 50h 54h 58h 5Ch 60h 64h 68h ATF_First ATF_Continue ATF_Continue&Update ATF_Burst_Write GRF Data Reserved ATF_First_Update
Figure 6-1. TSB12LV32 Controller-FIFO-Access Address Map
6.1
General
The suffix _First in Figure 6-1 denotes an address that accesses the FIFO location where the first quadlet of a packet should be written to transmit the packet. The first quadlet is held in the FIFO until a quadlet is written to an Update address and the packet is transmitted. The suffix _Continue in Figure 6-1 denotes an address that accesses the FIFO location where the second through n-1 quadlets of a packet should be written, where n is the total number of quadlets in the packet. The second through n-1 quadlets are held in the FIFO until a quadlet is written to an Update address and the packet is transmitted. The suffix _Continue & Update in Figure 6-1 denotes an address that accesses the FIFO location where the last quadlet of a multiple (n) quadlet packet should be written so that the packet is confirmed for transmission.
6.2
ATF Access
The ATF consists of a 520 quadlet RAM, a write buffer, and control logic. The ATF write buffer is a four-quadlet buffer used to temporarily store asynchronous packet data from the microcontroller interface to facilitate burst writes. Asynchronous packets can also be transmitted through the data-mover port, however the ATF always has transmission priority and its data wil be sent first. The procedure for accessing the ATF for a quadlet write operation is accomplished in three successive steps. To ensure that an ATF underflow condition does not occur, loading of the ATF in the following manner is highly recommended:
First Quadlet of the Packet Successive (N-1) Quadlets of the Packet
* * *
Last (Nth) Quadlet of the Packet
Figure 6-2. Asynchronous Packet With N Quadlets (ATF Loading Operation)
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Each quadlet can be written into the ATF register on a byte (8-bit) boundary or word (16-bit) boundary. To write to the ATF in a byte fashion, the following steps should be followed: Step 1: Writing the first quadlet of the packet: a) Write the first 8 bits of the quadlet to ATF location 50h. b) Write the second 8-bits of the quadlet to ATF location 51h. c) Write the third 8 bits of the quadlet to ATF location 52h. d) Write the fourth 8-bits of the quadlet to ATF location 53h. The data is not yet confirmed for transmission. Writing the next (n-1) quadlets of the packet: a) Write the first 8-bits of each quadlet to ATF location 54h. b) Write the second 8 bits of each quadlet to ATF location 55h. c) Write the third 8 bits of each quadlet to ATF location 56h. d) Write the fourth 8 bits of each quadlet to ATF location 57h. The data is not yet confirmed for transmission. Last (Nth) quadlet of the packet: a) Write the first 8 bits of the quadlet to ATF location 58h. b) Write the second 8-bits of the quadlet to ATF location 59h. c) Write the third 8 bits of the quadlet to ATF location 5Ah. d) Write the fourth 8 bits of the quadlet to ATF location 5Bh. The data is now confirmed for transmission.
Step 2:
Step 3:
To write to the ATF in a word fashion, the following steps should be followed: Step 1: Writing the first quadlet of the packet: a) Write the first 16 bits of the quadlet to ATF location 50h. b) Write the second 16 bits of the quadlet to ATF location 52h. The data is not yet confirmed for transmission. Writing the next (n-1) quadlets of the packet: a) Write the first 16 bits of each quadlet to ATF location 54h. b) Write the second 16 bits of each quadlet to ATF location 56h. The data is not yet confirmed for transmission. Last (Nth) quadlet of the packet: a) Write the first 16 bits of the quadlet to ATF location 58h. b) Write the second 16 bits of the quadlet to ATF location 5Ah. The data is now confirmed for transmission.
Step 2:
Step 3:
All writes to the ATF must be quadlet aligned (i.e., only an even number of write accesses is allowed). If the first quadlet of a packet is not written to the ATF_First location, the transmitter enters a state denoted by an ATSTK interrupt in the interrupt register at 0Ch. An underflow of the ATF also causes an ATSTK interrupt. When this ATF_Stuck state is entered, no asynchronous packets can be sent until the ATF is cleared by way of the ATFCLR control bit (bit 0 in FIFO status CFR at 30h). Isochronous packets still can be sent while the ATF is in the ATF_Stuck state.
6.3
ATF Burst Access
It is possible to perform a burst write into the address location ATF_Continue at 54h, which allows multiple quadlets to load into ATF, but the data packet is not confirmed for transmission until an update address is written. It is not possible to perform a burst write into the address location ATF_Continue&Update at 58h, which loads the last quadlet of a packet into ATF and confirms the data for transmission. Burst write accesses to the address location 5Ch, or ATF_Burst_Write, can write the entire packet into the ATF from one address. The last quadlet written into ATF confirms the packet for transmission.
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FIFO Memory Access
To perform a burst write operation the microcontroller must continually drive MCS low. The TSB12LV32 loads MD0-MD15 to the ATF during each rising edge of BCLK while MCS is low. At the same time it asserts MCA (MCA is always one cycle behind MCS) low. The ATF_First_Update address location is optimized for transmitting zero-length isochronous packets or asynchronous stream packets. A zero-length packet contains no data payload, and only the packet header and header CRC are transmitted.
6.4
General-Receive FIFO (GRF)
The GRF contains a 520 quadlet RAM, a prefetch buffer and control logic. When the recevied paacket has been verified and the GRF RAM has enough space to hold the whole packet (CRCs not included), the hardware triggers a receive packet interrupt, RXGRFPKT, in the interrupt register at 0Ch and the GRF prefetch buffer automatically reads the data from the RAM. The GRF prefetch buffer is used to support the microinterface burst read operation. Microcontroller read access to the GRF is performed by a read from the address location 60h, GRF Data. The GRF accumulates self-ID packets upon 1394 bus reset. All quadlets of a self-ID packet are saved in the GRF after power up. TSB12LV32 hardware checks to ensure that the second quadlet is indeed the complement (logical inverse) of the first quadlet of the self-ID. If there are any errors associated with the self-ID process, a self-ID interrupt, SELFIDER, is generated in the interrupt register at 0Ch and the self-ID error code field, SIDERCODE, at 08h is updated to reflect the error(s). The option to check for the logical inverse of the self-ID in the second quadlet can be turned off by setting to 0 the FULLSID bit in the control register at 08h.
6.5
GRF Stored Data Format
Each quadlet in the GRF is internally 33 bits wide. The most significant bit (extra bit) is used to indicate whether it is a packet token or a regular received quadlet (received header CRC and data CRC are checked and not stored in GRF). This bit is called the CD bit, which value is reflected in bit 6 of the FIFO status register. If the CD bit is 1, the next quadlet read from the GRF is a packet token. If the CD bit is 0, the next quadlet read from the GRF is a regular received quadlet. A packet token is stored as the first quadlet for each received confirmed packet. The definition for a packet token is shown in Table 6-1. Bit 0 is most significant bit and bit 32 is the least significant bit. Table 6-1. Packet Token Definition
BITS 0 1-2 3-16 17-19 20-24 25-26 27-28
NAME CD RESERVED QUADLET_COUNT RESERVED ackCode RESERVED SPEED Reserved
DESCRIPTION CD bit is 1 for packet token. This bit should only be read from the FIFO status register at 30h. Expected quadlet count after packet token for this received packet Reserved If bit 20 is 0, bits[21:24] are used as the Ack code that is sent back to the transmitting node. If bit 20 is 1, it is an error condition and an error Ack code is sent to the transmitting node. Reserved The speed code for the received packet. 00 - 100 Mbps 01 - 200 Mbps 10 - 400 Mbps Reserved
29-32
RESERVED
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TSB12LV32 Data Formats
7
TSB12LV32 Data Formats
The data formats for transmission and reception of data are shown in the following sections. The transmit format describes the expected organization of data presented to the TSB12LV32 at the data-mover port or the microcontroller interface. The receive formats describe the data format that the TSB12LV32 presents to the data-mover port or the microcontroller interface.
7.1
Asynchronous Transmit/Receive (Microcontroller Interface/Data-Mover Port to/From TSB12LV32)
Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface or data-mover port to transmit asynchronous data packets. The general-receive FIFO (GRF) and the data-mover port can recieve asynchronous data packets and/or isochronous data packets. Data is received and transmitted in two basic formats. The first format is for quadlet packets, and the second format is for block packets. For transmission, the FIFO address accessed indicates the beginning, middle, and end of a packet. For receipt, the data length, which is found in the header of the packet, determines the number of bytes in a block packet.
7.1.1 Quadlet Transmit
The quadlet transmit formats are shown in Figure 7-1 and are described in Table 7-1. The first quadlet contains packet control information. The second and third quadlets contain the 64-bit, quadlet-aligned address for read and write requests and retry codes for read and write responses. The fourth quadlet is data used only for write requests and read responses. For read requests and write responses, the quadlet data field is omitted.
01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd destinationID desination OffsetLow quadlet data Quadlet-Transmit Format (Write Request) 01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd destinationID tLabel rCode rt tCode priority tLabel rt tCode priority
desination OffsetHigh
Quadlet-Transmit Format (Write Response) 01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd destinationID desination OffsetLow Quadlet-Transmit Format (Read Request) 01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd destinationID tLabel rCode rt tCode priority tLabel rt tCode priority
desination OffsetHigh
quadlet data Quadlet-Transmit Format (Read Response)
Figure 7-1. Quadlet Transmit Formats
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Table 7-1. Quadlet Transmit Format Functions
FIELD NAME spd tLabel rt tCode priority destinationID destination OffsetHigh, destination OffsetLow quadlet data rcode DESCRIPTION The Spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps, and 11 is undefined for this implementation. The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet. The rt field is the retry code for the current packet: 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB. The tCode field is the transaction code for the current packet (see Table 6-10 of the IEEE 1394-1995 standard). The priority field contains the priority level for the current packet. For cable implementation, the value of the bits must be zero (for backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard). The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node number that forms the destination node address of the current packet. The concatenation of these two fields addresses a quadlet in the destination node address space. This address must be quadlet aligned (modulo 4). For write requests and read responses, the quadlet data field holds the data to be transferred. For write responses and read requests, this field is not used and should not be written into the FIFO. Specifies the result of the read request transaction. The response codes that can be returned to the requesting agent are defined as follows: Response Code 0 1-3 4 5 6 7 8-Fh Name resp_complete reserved resp_conflict_error resp_data_error resp_type_error resp_address_error reserved Description Node successfully completed requested operation
Resource conflict detected by responding agent Request may be retried. Hardware error. Data not available Field within request packet header contains unsupported or invalid value. Address location within specified node not accessible
7.1.2 Block Transmit
The block-transmit format is shown in Figure 7-2 and is described in Table 7-2. The first quadlet contains packet-control information. The second and third quadlets contain the 64-bit address for write requests and read requests and a 4-bit rCode for read responses. The first 16 bits of the fourth quadlet contain the dataLength field. This is the number of bytes of data in the packet. The remaining 16 bits represent the extended_tCode field (see Table 6-11 of the IEEE 1394-1995 standard for more information on extended_tCodes). The block data for a block write request follows the extended_tCode; no block data is included in a block read request.
01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 spd destinationID destination OffsetLow dataLength block data extended_tCode tLabel rt tCode priority
destination OffsetHigh
Figure 7-2. Block Transmit Format
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Table 7-2. Block Transmit Format Functions
FIELD NAME spd tLabel rt tCode priority destinationID destination OffsetHigh, destination OffsetLow dataLength extended_tCode block data DESCRIPTION The Spd field indicates the speed at which the current packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps, and 11 is undefined for this implementation. The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet. The rt field is the retry code for the current packet: 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB. tCode is the transaction code for the current packet (see Table 6-10 of the IEEE 1394-1995 standard). The priority level for the current packet. For cable implementation, the value of the bits must be zero. For backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard. The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which the current packet is being sent. The concatenation of the destination OffsetHigh and the destination OffsetLow fields addresses a quadlet in the destination node address space. This address must be quadlet aligned (modulo 4). The upper 4 bits of the destination OffsetHigh field are used as the response code for lock-response packets and the remaining bits are reserved. The dataLength filed contains the number of bytes of data to be transmitted in the packet. The block extended_tCode to be performed on the data in the current packet (see Table 6-11 of the IEEE 1394-1995 standard). The block data field contains the data to be sent. If dataLength is 0, no data should be written into the FIFO for this field. Regardless of the destination or source alignment of the data, the first byte of the block must appear in byte 0 of the first quadlet.
7.1.3 Quadlet Receive
The quadlet-receive format through the FIFO (GRF) is shown in Figure 7-3 and is described in Table 7-3. The first quadlet (trailer) contains the packet-reception status that is added by the TSB12LV32. The first 16 bits of the second quadlet contain the destination node and bus ID, and the remaining 16 bits contain packet-control information. The first 16 bits of the third quadlet contain the node and bus ID of the source, and the remaining 16 bits of the third quadlet and the fourth quadlet contain the 48-bit, quadlet-aligned destination offset address. The last quadlet contains data that is used by write requests and read responses. For read requests and write responses, the quadlet data field is omitted. The quadlet-receive format through the DM is shown in Figure 7-4 and is described in Table 7-3. This format is similar to the quadlet receive format for the TSB12LV31(GPLynx). The first 16 bits of the first quadlet contain the destination node and bus ID, and the remaining 16 bits contain packet-control information. The first 16 bits of the second quadlet contain the node and bus ID of the source, and the remaining 16 bits of the second and third quadlets contain the 48-bit, quadlet-aligned destination offset address for read requests and write requests, but contain the 4-bit rCode for read responses and write responses. The fourth quadlet contains data that is used by write requests and read responses. For read requests and write responses, the quadlet data field is omitted. The last quadlet (trailer) contains the packet-reception status that is added by the TSB12LV32.
01 00 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 0 tLabel ackCode rt 00 spd 00 0 0
numofQuadlets destinationID sourceID
tCode
priority
destination OffsetHigh destination OffsetLow
quadlet data (write requests and read responses only, omitted for write responses and read requests)
Figure 7-3. GRF Quadlet-Receive Format
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01
2
345
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tLabel rt tCode priority
destinationID sourceID
destination OffsetHigh destination OffsetLow
quadlet data (write requests and read responses only, omitted for write responses and read requests) 00 numofQuadlets 00 0 ackCode 0 0 spd 00 0 0
Figure 7-4. Data-Mover Quadlet-Receive Format Table 7-3. Quadlet Receive Format Functions
FIELD NAME numofQuadlets ackCode spd destinationID tLabel rt tCode priority sourceID destination OffsetHigh, destination OffsetLow DESCRIPTION Total number of quadlets in the current packet (payload and header quadlets only). This 5-bit field holds the acknowledge code sent by the receiver for the current packet (see Table 6-13 in the draft standard). The Spd field indicates the speed at which the current packet was sent. 00 = 100 Mbps, 01 =200 Mbps, 10 = 400 Mbps, and 11 is undefined for this implementation. The destinationID field contains the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which the current packet is being sent. The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet. The rt field is the retry code for the current packet: 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB. The tCode field is the transaction code for the current packet (see Table 6-10 of the IEEE 1394-1995 standard). The priority field contains the priority level for the current packet. For cable implementation, the value of the bits must be zero (for backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard). The sourceID field contains the node ID of the sender of the current packet. The concatenation of the destination OffsetHigh and the destination OffsetLow fields addresses a quadlet in the destination node address space. This address must be quadlet aligned (modulo 4). (The upper four bits of the destination OffsetHigh field are used as the response code for lock-response packets, and the remaining bits are reserved.) For write requests and read responses, the quadlet data field holds the transferred data. For write responses and read requests, this field is not present.
quadlet data
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7.1.4 Block Receive
The block receive format through the GRF is shown in Figure 7-5 and is described in Table 7-4. The first packet contains packet reception status that is added by the TSB12LV32. The first 16 bits of the second quadlet contain the node and bus ID of the destination node, and the last 16 bits contain packet control information. The first 16 bits of the third quadlet contain the node and bus ID of the source node, and the last 16 bits of the third quadlet and all of the fourth quadlet contain the 48-bit, quadlet aligned destination offset address for write requests and read requests, and a 4-bit rCode for read responses. All remaining quadlets contain data that is used only for write requests and read responses. For block read requests, the data field is omitted.
01 00 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 0 tLabel ackCode rt 0 0 spd tCode 00 0 0
numofQuadlets destinationID sourceID
priority
destination OffsetHigh destination OffsetLow
dataLength block data
extended_tCode
Figure 7-5. GRF Block-Receive Format The block receive format through the data mover is shown in Figure 7-6 and is described in Table 7-4. The first 16 bits of the first quadlet contain the node ID and bus ID of the destination node, and the last 16 bits contain packet control information. The first 16 bits of the second quadlet contain the node ID and bus ID of the source node, and the last 16 bits of the second quadlet and all of the third quadlet contain the 48-bit, quadlet aligned destination offset addressfor write requests and read requests, and a 4-bit rCode for read responses. All remaining quadlets, except for the last one, contain data that is used only for write requests and read responses. For block read requests, the data field is omitted. The last quadlet contains packet-reception status. The block receive format through the data mover is shown in Figure 7-6.
01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tLabel rt tCode priority
destinationID sourceID
destination OffsetHigh destination OffsetLow
dataLength block data (if any) 00 numofQuadlets 00 0
extended_tCode
ackCode
00
spd
00
0
0
Figure 7-6. Data-Mover Block-Receive Format
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Table 7-4. Block Receive Format Functions
FIELD NAME numofQuadlets ackCode destinationID tLabel rt tCode priority sourceID destination OffsetHigh, destination OffsetLow dataLength DESCRIPTION Total number of quadlets in the current packet (payload and header quadlets only) This 5-bit field holds the acknowledge code sent by the receiver for the current packet. The destinationID field is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which the current packet is being sent. The tLabel field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This field is used to pair up a response packet with its corresponding request packet. The rt field contains the retry code for the current packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB. The tCode field is the transaction code for the current packet (see Table 6-10 of the IEEE-1394-1995 standard). The priority field contains the priority level for the current packet. For cable implementation, the value of the bits must be zero (for backplane implementation, see clauses 5.4.1.3 and 5.4.2.1 of the IEEE-1394-1995 standard). The sourceID field contains the node ID of the sender of the current packet. The concatenation of the destination OffsetHigh and the destination OffsetLow fields addresses a quadlet in the destination node address space. This address must be quadlet aligned (modulo 4). The upper 4 bits of the destination OffsetHigh field are used as the response code for lock-response packets and the remaining bits are reserved. For write request, read responses, and locks, the dataLength field indicates the number of bytes being transferred. For read requests, the dataLength field indicates the number of bytes of data to be read. A write-response packet does not use this field. Note that the number of bytes does not include the header, only the bytes of data. The extended_tCode field contains the block extended_tCode to be performed on the data in the current packet (see Table 6-11 of the IEEE 1394-1995 standard). The block data field contains any data being transferred for the current packet. Regardless of the destination address or memory alignment, the first byte of the data appears in byte 0 of the first quadlet of this field. The last quadlet of the field is padded with zeros out to four bytes, if necessary. The spd field indicates the speed at which the current packet was sent. 00 = 100 Mbps, 01 = 200 Mbps, 10 = 400 Mbs, and 11 is undefined for this implementation.
extended_tCode block data
spd
7.2
Isochronous Transmit (Data-Mover Port to TSB12LV32)
The format of the isochronous transmit packet is shown in Figure 7-7 and is described in Table 7-5. The data for each channel must be presented to the data-mover port in this format in the order that packets are to be sent. The transmitter sends any packets available at the isochronous transmit interface immediately following reception or transmission of the cycle-start message. The speed at which the current packet is sent is determined by the speed field in the DM control register (bits 22-23). There is no FIFO in the TSB12LV32 that supports isochronous transmit.
01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TAG chanNum tCode sy
dataLength
isochronous data
Figure 7-7. Isochronous Transmit Format
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Table 7-5. Isochronous Transmit Functions
FIELD NAME dataLength TAG chanNum tCode sy isochronous data DESCRIPTION The dataLength field indicates the number of bytes in the current packet. The TAG field indicates the format of data carried by the isochronous packet (00 = formatted, 01-11 are reserved). The chanNum field carries the channel number with which the current data is associated. The transaction code for the current packet (tCode = Ah). The sy field carries the transaction layer-specific synchronization bits. The isochronous data field contains the data to be sent with the current packet. The first byte of data must appear in byte 0 of the first quadlet of this field. If the last quadlet does not contain four bytes of data, the unused bytes should be padded with zeros.
7.2.1 Isochronous Receive (TSB12LV32 to Microcontroller Interface/Data-Mover Port)
The format of the isochronous receive data through the DM is shown in Figure 7-8 and is described in Table 7-6. The data length, which is found in the header of the packet, determines the number of bytes in an isochronous packet. The final packet after the isochronous data contains packet reception information. For iscohronous receive through the general receive FIFO, the quadlet containing packet reception information (trailer) is inserted as the first quadlet in the receive data, as shown in Figure 7-8.
01 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TAG chanNum tCode (A) sy
dataLength
isochronous data 00 numofQuadlets 00 0 errCode 00 spd 00 0 0
Figure 7-8. Data-Mover Isochronous Receive Format
01 00
2
345
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000 TAG isochronous data errCode chanNum 0 0 spd 00 sy 0 0
numofQuadlets dataLength
tCode (A)
Figure 7-9. GRF Isochronous Receive Format Table 7-6. Isochronous Receive Functions
FIELD NAME dataLength TAG chanNum tCode sy isochronous data spd numofQuadlets errCode DESCRIPTION The dataLength field indicates the number of bytes in the current packet. The TAG field indicates the format of data carried by isochronous packet (00 = formatted, 01-11 are reserved). The chanNum field contains the channel number with which this data is associated. The tCode field carries the transaction code for the current packet (tCode = Ah). The sy field carries the transaction layer-specific synchronization bits. The isochronous data field has the data to be sent with the current packet. The first byte of data must appear in byte 0 of the first quadlet of this field. The last quadlet should be padded with zeros. The spd field indicates the speed at which the current packet was sent. Total number of quadlets in the current packet (payload and header quadlets only). The errCode field indicates whether the current packet has been received correctly. The possibilities are Complete, DataErr, or CRCErr, and have the same encoding as the corresponding acknowledge codes.
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7.3
Phy Configuration
The format of the Phy configuration packet is shown in Figure 7-10 and is described in Table 7-7. The Phy configuration packet transmit contains two quadlets, which are loaded into the ATF. The first quadlet is written to address 50h. The second quadlet is written to address 58h. The 00E0h in the first quadlet (bits 16-31) tells the TSB12LV32 that this quadlet is the Phy configuration packet. The 00E0h is then replaced with 0000h before the packet is transmitted to the Phy interface.
01 00 2 345 root_ID 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RT gap_cnt 0 0 00 00 tcode = 00E0 00111 000 00
Logical inverse of first 16 bits of first quadlet
1
1
11
11
111
1
1
111
11
Figure 7-10. Phy Configuration Packet Format The Phy configuration packet can perform the following functions: * * Set the gap count field of all nodes on the bus to a new value. The gap count, if set intelligently, can optimize bus performance. Force a particular node to be the bus root after the next bus reset.
It is not valid to transmit a Phy configuration packet with both the R bit and T bit set to zero. This would cause the packet to be interpreted as an extended Phy packet. Table 7-7. Phy Configuration Packet Functions
FIELD NAME 00 root_ID R T gap_cnt The 00 field is the Phy configuration packet identifier. The root_ID field is the physical_ID of the node to have its force_root bit set (only meaningful when R is set). When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit of all other nodes are cleared. When R is cleared, root_ID is ignored. When T is set, the PHY_CONFIGURATION.gap_count field of all the nodes is set to the value in the gap_cnt field. The gap_cnt field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This value goes into effect immediately upon receipt and remains valid after the next bus reset. After the second reset, gap_cnt is set to 63h unless a new Phy configuration packet is received. DESCRIPTION
The format of a received Phy-configuration packet is shown in Figure 7-11 and is described in Table 7-8. When PHY_PKT_ENA (bit 3 of the control register at 08h) is set, all Phy packets are received in the GRF. One HDRERR interrupt is generated for every Phy packet received.
01 00 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 numofQuadlets 0 0 0 ackCode 0 0 spd 00 00
Phy configuration quadlet Logical inverse of the Phy configuration quadlet
Figure 7-11. Receive Phy Configuration Packet Format Table 7-8. Receive Phy Configuration Packet
FIELD NAME numofQuadlets ackCode spd DESCRIPTION Total number of quadlets in the packet. This field is equal to 2 in this case. This 5-bit field holds the acknowledge code sent by the receiver for the current packet. In this case, the ackCode is equal to 1 (ack_complete). The spd field indicates the speed at which the current packet was sent. In this case, the spd field is equal to 00 (S100).
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7.3.1 Extended Phy Packets
7.3.1.1 Ping Packets
The reception of a Phy ping packet causes the node identified by Phy_ID to transmit Self-ID packet(s) that reflect the current configuration and status of the Phy. The ping packet provides a method of measuring the round-trip delay of packets between two nodes on the bus that are farthest from one another in terms of cable hops. The format of this packet is shown in Figure 7-12 and described in Table 7-9.
transmitted first 00 Phy_ID 00 type (0) 0 0 00 00 00 0 00 0 0 000 00
Logical inverse of the first quadlet transmitted last
Figure 7-12. Ping Packet Format Table 7-9. Ping Packet Fields
FIELD NAME Phy_ID type DESCRIPTION Physical node identifier of the destination of this packet Extended Phy packet type (zero identifies ping packet)
7.3.1.2
Remote Access Packets
The remote access packet provides a method for a node to access the Phy registers of another node on the bus. The reception of a remote access packet causes the node identified by the Phy_ID field to read the selected Phy register and subsequntly return a remote reply packet that contains the current value of the Phy register. The format of this packet is shown in Figure 7-13 and described in Table 7-10.
transmitted first 00 Phy_ID 00 type (8) 000 port 000 1 1 1 00 cmnd
Logical inverse of the first quadlet transmitted last
Figure 7-13. Remote Access Packet Format Table 7-10. Remote Access Packet Fields
FIELD NAME Phy_ID type port cmnd DESCRIPTION Physical node identifier of the destination of this packet Extended Phy packet type (8 identifies command packet) This field selects one of the Phy ports Command: 0 = NOP (No operation) 1 = Transmit TX_DISABLE_NOTIFY, then disable port 2 = Initiate suspend (i.e., become a suspend initiator) 4 = Clear the port's Fault bit to zero 5 = Enable port 6 = Resume port
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7.3.1.3
Remote Command Packets
The remote command packet provides a method for one node to issue a number of Phy-specific commands to the selected port within the target Phy. The reception of a remote command packet requests the node identified by the Phy_ID field to perform the operation specified in the cmnd field and subsequently return a remote confirmation packet. The format of this packet is shown in Figure 7-14 and described in Table 7-11.
transmitted first 00 Phy_ID 00 type (8) 0 00 port 0 00 1 1 1 00 cmnd
Logical inverse of the first quadlet transmitted last
Figure 7-14. Remote Command Packet Format Table 7-11. Remote Command Packet Fields
FIELD NAME Phy_ID type port cmnd DESCRIPTION Physical node identifier of the destination of this packet Extended Phy packet type (8 identifies command packet) This field selects one of the Phy ports Command: 0 = NOP (No operation) 1 = Transmit TX_DISABLE_NOTIFY, then disable port 2 = Initiate suspend (i.e., become a suspend initiator) 4 = Clear the port's Fault bit to zero 5 = Enable port 6 = Resume port
7.3.1.4
Resume Packets
The resume packet is a broadcast packet to all the Phys on the bus. It commands all suspended ports on the bus to resume normal operation. The reception of the resume packet causes any node to commence resume operations for all Phy ports that are both connected and suspended. A resume packet requires no reply. The format of this packet is shown in Figure 7-15 and described in Table 7-12.
transmitted first 00 Phy_ID 00 type (F16) 0 00 0 00 0 0 11 1 0 0 000
Logical inverse of the first quadlet transmitted last
Figure 7-15. Resume Packet Format Table 7-12. Resume Packet Fields
FIELD NAME Phy_ID type DESCRIPTION Physical node identifier of the source of this packet Extended Phy packet type (F identifies resume packet)
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7.4
Receive Self-ID Packet
Based on the settings of the RXSID and FULLSID bits in the control register at 08h, the self-ID packets can be either ignored or received into the GRF. See Table 7-13. Table 7-13. GRF Receive Self-ID Setup Using Control Register Bits (RXSID and FULLSID)
RXSID (bit 1) 0 1 1
FULLSID (bit 2) X 0 1 Self-ID packets are not received by the link.
OPERATION
Only the data quadlet (first quadlet) of the self-ID packets is received into the GRF. Both the data quadlet (first quadlet) and the logical inverse quadlet (second quadlet) of all self-ID packets are received into the GRF.
Figure 7-16 and Figure 7-17 show the format of a received self-ID packet. For completeness, the figures assume the cable Phy on the bus implements the maximum number of ports allowed by the 1394a-2000 specification (16). Both figures show one received self-ID packet. The contents are described in Table 7-14.
01 00 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LPS_RESET LPS_RESET
numofQuadlets
0
0
0
ackCode
0
0
spd
00
Self-ID data quadlet #0 Logical inverse of the self-ID quadlet #0 Self-ID data quadlet #1 Logical inverse of the self-ID quadlet #1 Self-ID data quadlet #2 Logical inverse of the self-ID quadlet #2
Figure 7-16. Receive Self-ID Packet Format (RXSID = 1, FULLSID = 1)
Figure 7-17 shows the format of the received self-ID packet when the FULLSID is cleared. In this case, only the first quadlet of each self-ID packet is received in the GRF.
01 0 0 2 345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 numofQuadlets 0 0 0 ackCode 0 0 spd 00
LPS_OFF
Self-ID data quadlet #0 Self-ID data quadlet #1 Self-ID data quadlet #2
Figure 7-17. Receive Self-ID Packet Format (RXSID = 1, FULLSID = 0) Table 7-14. Receive Self-ID Function
FIELD NAME Self-ID data quadlet Logical inverse of the self-ID quadlet ACK First 32-bits of the first self-ID packet Second 32-bits of the first self-ID packet When the ACK field is set (0001), the data in the self-ID packet is correct. When ACK is not equal to 0001, the data in the self-ID packet is incorrect. DESCRIPTION
LPS_OFF
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The cable Phy sends one to three self-ID packets at the base rate (100 Mbps) during the self-ID phase of arbitration or in response to a ping packet. The number of self-ID packets sent depends on the number of ports. Figure 7-18, Figure 7-19, and Figure 7-20 show the format of the cable Phy self-ID packets. Inside the GRF, the first received quadlet of a self-ID packet is always the header quadlet shown first in Figure 7-17 or Figure 7-18.
01 10 2 345 Phy_ID 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0L gap_cnt sp rsv c pwr p0 p1 p2 im
Logical inverse of first quadlet
Figure 7-18. Phy Self-ID Packet #0 Format
01 10
2
345 Phy_ID
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 n(0) rsv p3 p4 p5 p6 p7 p8 p9 p10 rm
Logical inverse of first quadlet
Figure 7-19. Phy Self-ID Packet #1 Format
01 10
2
345 Phy_ID
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 n(1) rsv p11 p12 p13 p14 p15 reserved
Logical inverse of first quadlet
Figure 7-20. Phy Self-ID Packet #2 Format
When there is only one node (i.e., one Phy/link pair) on the bus, following a bus reset, the GRF contains only the header quadlet. Example: If there are three 1394a-2000 compliant nodes on the bus, each with a Phy containing three or fewer ports, the GRF of any one of the links is shown below. The FULLSID bit is assumed to be set in this example.
GRF CONTENTS Header Self-ID1 Self-ID1 (inverse) Self-ID2 Self-ID2 (inverse) Self-ID3 Self-ID3 (inverse) 0000_0000_ACK DESCRIPTION Header quadlet for self-ID Phy packet Self_ID quadlet for Phy #1 Logical inverse quadlet for self_ID of Phy #1 Self_ID quadlet for Phy #2 Logical inverse quadlet for self_ID of Phy #2 Self_ID quadlet for Phy #3 Logical inverse quadlet for self_ID of Phy #3 Trailing acknowledgement quadlet
GRF contents (following a bus reset) with three nodes on the bus
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TSB12LV32 Data Formats
Table 7-15. Phy Self-ID Packet Fields
FIELD NAME 10 L gap_cnt sp The 10 field is the self-ID packet identifier. If set, this node has an active link and transaction layers. The gap_cnt field contains the current value for the current node PHY_CONFIGURATION.gap_count field. The sp field contains the Phy speed capability. The code is: 00 01 10 11 c pwr 98.304 Mbps 98.304 Mbps and 196.608 Mbps 98.304 Mbps, 196.608 Mbps, and 393.216 Mbps Extended speed capabilities reported in Phy register 3 DESCRIPTION
If set and the link_active flag is set, this node is contender for the bus or isochronous resource manager as described in clause 8.4.2 of IEEE Std 1394-1995. Power consumption and source characteristics: 000 001 010 011 100 101 110 111 Node does not need power and does not repeat power. Node is self-powered and provides a minimum of 15 W to the bus. Node is self-powered and provides a minimum of 30 W to the bus. Node is self-powered and provides a minimum of 45 W to the bus. Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the link. Reserved for future standaraization. Node is powered from the bus and is using up to 3 W. An additional 3 W is needed to enable the link. Node is powered from the bus and is using up to 3 W. An additional 7 W is needed to enable the link. Not present on the current Phy Not connected to any other Phy Connected to the parent node
p0-p15
The p0-p15 field indicates the port connection status. The code is: 00 01 10 11
i m n
Connected to the child node If set, this node initiated the current bus reset (i.e., it started sending a bus_reset signal before it received one). If set, another self-ID packet for this node immediately follows (i.e., if this bit is set and the next Self-ID packet received has a different Phy_ID, the self-ID packet was lost). Extended self-ID packet sequence number
rsv Reserved and set to all zeros The link is enabled by the link-on Phy packet described in clause 7.5.2 of the IEEE 1394.a-2000 specification; this packet can also enable application layers. There is no way to ensure that exactly one node has this bit set. More than one node can be requesting a bus reset at the same time.
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8
TSB12LV32/Phy Interface
This section provides an overview of the digital interface between a TSB12LV32 and a physical layer device (Phy). The information that follows can be used as a guide through the process of connecting the TSB12LV32 to a 1394 Phy. The part numbers referenced, the TSB41LV03A and the TSB12LV32, represent the Texas Instruments implementation of the Phy (TSB41LV03A) and link (TSB12LV32) layers of the IEEE 1394-1995 and 1394a-2000 standards. The specific details of how the TSB41LV03A device operates are not discussed in this document. Only those parts that relate to the TSB12LV32 Phy interface are mentioned.
8.1
Principles of Operation
The TSB12LV32 is designed to operate with a Texas Instruments physical-layer device. The following paragraphs describe the operation of the Phy-LLC interface assuming a TSB41LV03A Phy. The TSB41LV03A is an IEEE 1394a-2000 three-port cable transceiver/arbiter Phy capable of 400-Mbps speeds. The interface to the Phy consists of the SCLK, CTL0-CTL1, D0-D7, LREQ, LPS, LINKON, and DIRECT terminals on the TSB12LV32, as shown in Figure 8-1. See TSB12LV32 (GP2Lynx)/TSB41LV03 Reference Schematic application report, TI literature number SLLA044, for a detailed description of the electrical interface between the TSB12LV32 and TSB41LV03.
TSB12LV32 Link-Layer Controller SCLK CTL[0:1] D[0:7] LREQ LPS LINKON DIRECT DIRECT ISO TSB41LV03A Physical-Layer Device SYSCLK CTL[0:1] D[0:7] LREQ LPS C/LKON ISO
Phy-LLC Interface
Figure 8-1. Phy-LLC Interface The SYSCLK from the Phy terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to, and sampled on, the rising edge of SYSCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the TSB41LV03A and TSB12LV32. The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control information, or packet data between the devices. The TSB41LV03A supports S100, S200, and S400 data transfers over the D0-D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0-D3 terminals are used; and in S400 operation all D0-D7 terminals are used for data transfer. When the TSB41LV03A is in control of the D0-D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the TSB12LV32 is in control of the D0-D7 bus, unused Dn terminals are ignored by the TSB41LV03A.
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The LREQ terminal is controlled by the TSB12LV32 to send serial service requests to the Phy in order to request access to the serial bus for packet transmission, read or write Phy registers, or control arbitration acceleration. The LPS and LINKON terminals are used for power management of the Phy and TSB12LV32. The LPS terminal indicates the power status of the TSB12LV32, and can be used to reset the Phy-LLC interface or to disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the TSB12LV32 and to indicate an interrupt to the TSB12LV32 when either LPS is inactive or the Phy register LCtrl bit is zero. The TSB41LV03A normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The TSB12LV32 is allowed to drive these buses only after the TSB12LV32 has been granted permission to do so by the Phy. There are four operations that can occur on the Phy-LLC interface: link service request, status transfer, data transmit, and data receive. The TSB12LV32 issues a service request to read or write a Phy register, to request the Phy to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration. The Phy can initiate a status transfer either autonomously or in response to a register read request from the TSB12LV32. The Phy initiates a receive operation whenever a packet is received from the serial bus. The Phy initiates a transmit operation after winning control of the serial bus following a bus request by the TSB12LV32. The transmit operation is initiated when the Phy grants control of the interface to the TSB12LV32. The encoding of the CTL0-CTL1 bus is shown in Table 8-1 and Table 8-2. Table 8-1. CTL Encoding When the Phy Has Control of the Bus
CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Status Receive Grant No activity (this is the default mode) Status information is being sent from the Phy to the TSB12LV32. An incoming packet is being sent from the Phy to the TSB12LV32. The TSB12LV32 has been given control of the bus to send an outgoing packet. DESCRIPTION
Table 8-2. CTL Encoding When the TSB12LV32 Has Control of the Bus
CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Hold Transmit Reserved DESCRIPTION The TSB12LV32 releases the bus (transmission has been completed). The TSB12LV32 is holding the bus while data is being prepared for transmission, or indicating that another packet is to be transmitted (concatenated) without arbitrating. An outgoing packet is being sent from the TSB12LV32 to the Phy. Reserved
8.2
TSB12LV32 Service Request
To request access to the bus, to read or write a Phy register, or to control arbitration acceleration, the TSB12LV32 sends a serial bit stream on the LREQ terminal as shown in Figure 8-2.
LR0 LR1 LR2 LR3
......
LR(n-2)
LR(n-1)
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.
Figure 8-2. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 8-3.
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Table 8-3. Request Stream Bit Length
REQUEST TYPE Bus request Read register request Write register request Acceleration control request NUMBER OF BITS 7 or 8 9 17 6
Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 8-4. Table 8-4. Request Type Encoding
LR1-LR3 000 001 010 011 100 101 110 111 NAME ImmReq IsoReq PriReq FairReq RdReg WrReg AccelCtl Reserved DESCRIPTION Immediate bus request. Upon detection of idle, the Phy takes control of the bus immediately without arbitration. Isochronous bus request. Upon detection of idle, the Phy arbitrates for the bus without waiting for a subaction gap. Priority bus request. The Phy arbitrates for the bus after a subaction gap, ignores the fair protocol. Fair bus request. The Phy arbitrates for the bus after a subaction gap, follows the fair protocol. The Phy returns the specified register contents through a status transfer. Write to the specified register Enable or disable asynchronous arbitration acceleration Reserved
For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 8-5. Table 8-5. Bus Request
BIT(S) 0 1-3 4-6 7 NAME Start bit Request type Request speed Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) Indicates the type of bus request (see Table 8-4) Indicates the speed at which the Phy sends the data for this request (see Table 8-6) for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, this bit can be omitted.
The 3-bit request speed field used in bus requests is shown in Table 8-6. Table 8-6. Bus Request Speed Encoding
LR4-LR6 000 010 100 All others DATA RATE S100 S200 S400 Invalid
NOTE: The TSB41LV03A accepts a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the TSB41LV03A ignores any data presented by the TSB12LV32 and transmits a null packet. For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 8-7. Table 8-7. Read Register Request
BIT(S) 0 1-3 4-7 8 NAME Start bit Request type Address Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) A 100 indicating this is a read register request. Identifies the address of the Phy register to be read Indicates the end of the transfer (always 0)
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For a write register request the length of the LREQ bit stream is 17 bits as shown in Table 8-8. Table 8-8. Write Register Request
BIT(S) 0 1-3 4-7 8-15 16 NAME Start bit Request type Address Data Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) A 101 indicating this is a write register request Identifies the address of the Phy register to be written to Gives the data that is to be written to the specified register address Indicates the end of the transfer (always 0)
For an acceleration control request the length of the LREQ bit stream is 6 bits as shown in Table 8-9. Table 8-9. Acceleration Control Request
BIT(S) 0 1-3 4 5 NAME Start bit Request type Control StopbBit DESCRIPTION Indicates the beginning of the transfer (always 1) A 110 indicating this is a acceleration control request Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0. Indicates the end of the transfer (always 0)
For fair or priority access, the TSB12LV32 sends the bus request (FairReq or PriReq) at least one clock after the Phy-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the Phy, then any pending fair or priority request is lost (cleared). Additionally, the Phy ignores any fair or priority requests if the receive state is asserted while the TSB12LV32 is sending the request. The TSB12LV32 can then reissue the request one clock after the next interface idle. The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or transmitting a cycle start message, the TSB12LV32 can issue an isochronous bus request (IsoReq). The Phy clears an isochronous request only when the serial bus has been won. To send an acknowledge packet, the TSB12LV32 must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the Phy immediately grants control of the bus to the TSB12LV32. The TSB12LV32 sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the TSB12LV32 does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the TSB12LV32 must not use this grant to send another type of packet. After the interface is released the TSB12LV32 can proceed with another request. The TSB12LV32 can make only one bus request at a time. Once the TSB12LV32 issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the Phy indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the TSB12LV32 granted control). The Phy ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the Phy loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the Phy returns the contents of the addressed register to the TSB12LV32 at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the Phy continues to attempt the transfer of the requested register until it is successful. A write or read register request can be made at any time, including while a bus request is pending. Once a read register request is made, the Phy ignores further read register requests until the register contents are successfully transferred to the TSB12LV32. A bus reset does not clear a pending read register request. The TSB41LV03A includes several arbitration acceleration enhancements, which allow the Phy to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in Phy register 5 is set.
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The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the TSB12LV32 to temporarily enable or disable the arbitration acceleration enhancements of the TSB41LV03A during the asynchronous period. The TSB12LV32 typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the enhancements when it receives a cycle start message. The acceleration control request can be made at any time, however, and is immediately serviced by the Phy. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the EAA bit is set.
8.3
Status Transfer
A status transfer is initiated by the Phy when there is status information to be transferred to the TSB12LV32. The Phy waits until the interface is idle before starting the transfer. The transfer is initiated by the Phy asserting status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The Phy maintains CTL = status for the duration of the status transfer. The Phy can prematurely end a status transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The Phy continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The Phy normally sends just the first four bits of status to the TSB12LV32. These bits are status flags that are needed by the TSB12LV32 state machines. The Phy sends an entire 16-bit status packet to the TSB12LV32 after a read register request, or when the Phy has pertinent information to send to the TSB12LV32 or transaction layers. The only defined condition where the Phy automatically sends a register to the TSB12LV32 is after self-ID, when the Phy sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the TSB12LV32 immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. The definition of the bits in the status transfer are shown in Table 8-10 and the timing is shown in Figure 8-3. Table 8-10. Status Bits
BIT(S) 0 1 2 3 4-7 8-15
NAME Arbitration reset gap Subaction gap Bus reset Interrupt Address Data
DESCRIPTION Indicates that the Phy has detected that the bus has been idle for an arbitration reset gap time (as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV32 in the busy/retry state machine. Indicates that the Phy has detected that the bus has been idle for a subaction gap time (as defined in IEEE Std 1394-1995). This bit is used by the TSB12LV32 to detect the completion of an isochronous cycle. Indicates that the Phy has entered the start of the bus reset state. Indicates that a Phy interrupt event has occurred. An interrupt event can be a configuration time-out, cable-power voltage falling too low, a state time-out, or a port status change. This field holds the address of the Phy register whose contents are being transferred to the TSB12LV32. This field holds the register contents.
SYSCLK (a) CTL[0:1] 00 01 (b) 00
D[0:1]
00
S[0:1]
S[14:15]
00
Figure 8-3. Status Transfer Timing
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The sequence of events for a status transfer is as follows: * Status transfer initiated. The Phy indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is to be sent in addition to any status information. Status transfer terminated. The Phy normally terminates a status transfer by asserting idle on the CTL lines. The Phy can also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a receive operation. The Phy shall assert at least one cycle of idle between consecutive status transfers.
*
8.4
Receive Operation
Whenever the Phy detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The Phy indicates the start of a packet by placing the speed code (encoded as shown in Table 8-11 on the D terminals, followed by packet data. The Phy holds the CTL terminals in the receive state until the last symbol of the packet has been transferred. The Phy indicates the end of packet data by asserting idle on the CTL terminals. All received packets are transferred to the TSB12LV32. Note that the speed code is part of the Phy-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. It is possible for the Phy to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving Phy, or whenever the TSB12LV32 immediately releases the bus without transmitting any data. In this case, the Phy asserts receive on the CTL terminals with the data-on indication (all 1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases, the TSB41LV03A sends at least one data-on indication before sending the speed code or terminating the receive operation. The TSB41LV03A also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the TSB12LV32. This packet is transferred to the TSB12LV32 just as any other received self-ID packet.
SYSCLK (a) CTL[0:1] 00 01 10 (b) D[0:7] XX FF (Data-On) (c) SPD (d) d0 dn 00 (e) 00
Figure 8-4. Normal Packet Reception Timing The sequence of events for a normal packet reception is as follows: * Receive operation initiated. The Phy indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status transfer operation that is in progress so that the CTL lines can change from status to receive without an intervening idle. Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more cycles preceding the speed-code. Speed-code. The Phy indicates the speed of the received packet by asserting a speed-code on the D lines for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle for which the D lines are not the data-on code. If the speed-code is invalid, or indicates a speed higher than that which the link is capable of handling, the link ignores the subsequent data.
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* *
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* *
Receive data. Following the data-on indication (if any) and the speed-code, the Phy asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. Receive operation terminated. The Phy terminates the receive operation by asserting idle on the CTL lines. The Phy asserts at least one cycle of idle following a receive operation.
SYSCLK (a) CTL[0:1] 00 01 10 (b) D[0:7] XX FF (Data-On) (c) SPD (d) d0 dn 00 (e) 00
Figure 8-5. Null Packet Reception Timing The sequence of events for a null packet reception is as follows: * Receive operation initiated. The Phy indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status transfer operation that is in progress so that the CTL lines can change from status to receive without an intervening idle. Data-on indication. The Phy asserts the data-on indication code on the D lines for one or more cycles. Receive operation terminated. The Phy terminates the receive operation by asserting idle on the CTL lines. The Phy asserts at least one cycle of idle following a receive operation. Table 8-11. Receive Speed Codes
D0-D7 00XX XXXX 0100 XXXX 0101 0000 1YYY YYYY DATA RATE S100 S200 S400 Data-on indication
* *
NOTE: X = Output as 0 by Phy, ignored by TSB12LV32 Y = Output as 1 by Phy, ignored by TSB12LV3
8.5
Transmit Operation
When the TSB12LV32 issues a bus request through the LREQ terminal, the Phy arbitrates to gain control of the bus. If the Phy wins arbitration for the serial bus, the Phy-LLC interface bus is granted to the TSB12LV32 by asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The TSB12LV32 then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless the TSB12LV32 immediately releases the interface, the TSB12LV32 can assert the idle state for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the TSB12LV32 to retain control of the bus while it prepares data for transmission. The TSB12LV32 can assert hold for zero or more clock cycles (i.e., the TSB12LV32 need not assert hold before transmit). The Phy asserts data-prefix on the serial bus during this time. When the TSB12LV32 is ready to send data, the TSB12LV32 asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The TSB12LV32 then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and placing its CTL and D terminals in high impedance. The Phy then regains control of the interface bus.
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The hold state asserted at the end of packet transmission indicates to the Phy that the TSB12LV32 requests to send another packet (concatenated packet) without releasing the serial bus. The Phy responds to this concatenation request by waiting the required minimum packet separation time and then asserting grant as before. This function can be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (because the speed of the packets is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of Phy register 5 is set), the TSB12LV32 must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 8-11. After sending the last packet for the current bus ownership, the TSB12LV32 releases the bus by asserting idle on the CTL terminals for two clock cycles. The Phy begins asserting idle on the CTL terminals one clock after sampling idle from the link. Note that whenever the D and CTL terminals change direction between the Phy and the TSB12LV32, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals.
SYSCLK (a) CTL[0:1] 00 11 00 (b) 00 (c) 01 (d) 10 (e) 01 00 (f) D[0:7] 00 00 d0 dn SPD 00 00 00 00 (g) 00
Link Controls CTL and D Phy CTL and D Outputs Are High Impedance NOTE: SPD = Speed code, see Table 8-11, d0-dn = Packet data
Figure 8-6. Normal Packet Transmission Timing The sequence of events for a normal packet transmission is as follows: * Transmit operation initiated. The Phy asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link can transmit a packet. The Phy releases control of the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle. Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of transmit. These hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
* *
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8.6
TSB12LV32/Phy Interface Critical Timing
tsu2 tsu3 SCLK tsu1 tsu0 th2 th3 th0 th1
td0 LREQ
CYCLEIN
CONTNDR
td1 CTL[0:1] X CONTROL X CONTROL
td2 D[0:7] XX DATA XX DATA
Figure 8-7. Critical Timing for the TSB12LV32/Phy Interface Table 8-12. TSB12LV32/Phy Interface Timing
PARAMETER td0 td1 td2 tsu0 tsu1 tsu2 tsu3 th0 th1 th2 Hold time from SCLK Setup time to SCLK TERMINAL NAME LREQ Delay time (SCLK to Q) CTL[0:1] D[0:7] CYCLEIN CONTNDR CTL[0:1] D[0:7] CYCLEIN CONTNDR CTL[0:1] MIN 3 3 3.5 2 3 3 3 2 2 0 0 MAX 21 21 21 UNIT ns ns ns ns ns ns ns ns ns ns ns
th3 D[0:7] All timing parameters are referenced to the rising edge of SCLK on the TSB12LV32 side.
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Electrical Characteristics
9
9.1
Electrical Characteristics
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Supply voltage range, VCC5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC5V + 0.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC5V + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air temperature range: TSB12LV32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TSB12LV32I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This applies to external input and bidirectional buffers. For 5-V tolerant terminals, use VI > VCC5V. 2. This applies to external output and bidirectional buffers. For 5-V tolerant terminals, use VI > VCC5V. DISSIPATION RATING TABLE PACKAGE PZ TA 25C 25 C POWER RATING 1500 mW DERATING FACTOR ABOVE TA = 25C 16.9 mW/C TA = 70C 70 C POWER RATING 739.5 mW TA = 85C 85 C POWER RATING 486 mW
9.2
Recommended Operating Conditions
MIN NOM 3.3 4.5 MAX 3.6 5.5 VCC5V VCC VCC5V VCC5V VCC5V 0.8 0.7 25 25 25 70 85 V ns C UNIT V V V V 3 3 0 0 TSB12LV32, RESET 2.6 2.0 2.2 0 0 0 TSB12LV32 0 -40 TSB12LV32, other inputs TSB12LV32I TSB12LV32
Supply voltage, VCC Supply voltage, VCC5V Input voltage, VI Output voltage, VO High-level input voltage, VIH
V
Low-level input voltage, VIL Input transition time, tf and tr (10% to 90%) Operating free-air temperature, TA
TSB12LV32I
TSB12LV32I
Virtual junction temperature, TJC 0 25 115 C This applies to external output buffers. The junction temperatures listed reflect simulation conditions. The absolute maximum junction temperature is 150C. The customer is responsible for verifying the junction temperature.
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
93
Electrical Characteristics
9.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS IOH = - 8 mA IOL = 8 mA VI = VIL VI = VIH 10 MIN VCC-0.6 0.5 -20 20 20 TYP MAX UNIT V V A A A A High-level output voltage Low-level output voltage Low-level input current High-level input current
VOH VOL IIL IIH
IOZ High-impedance output current VO = VCC or GND ICC(Q) Static supply current IO = 0 All typical characteristics are measured at VCC = 3.3 V and TA = 25C.
94
TSB12LV32, TSB12LV32I
SLLS336B--August 2003
Mechanical Information
10
Mechanical Information
The TSB12LV32 is packaged in a high-performance 100-pin PZ package. The following shows the mechanical dimensions of the PZ package.
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
0,50 75 51 0,27 0,17 0,08 M
76
50
100
26 0,13 NOM 1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0-7 Gage Plane 25
0,75 0,45 Seating Plane
1,60 MAX
0,08 4040149 / B 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
SLLS336B--August 2003
TSB12LV32, TSB12LV32I
95
Mechanical Information
96
TSB12LV32, TSB12LV32I
SLLS336B--August 2003

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