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| Features * * * * * * * * * * * * High performance ULC family suitable for large-sized CPLDs and FPGAs From 46K gates up to 780K gates supported From 18 Kbit to 390 Kbit DPRAM 100% compatible with Xilinx or Altera Pin counts to over 976 pins Any pin-out matched due to limited number of dedicated pads Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA Low quiescent current: 0.3 nA/gate Available in commercial and industrial grades 0.35 m Drawn CMOS, 3 and 4 Metal Layers Library Optimised for Synthesis, Floor Plan & Automatic Test Pattern Generation (ATPG) High Speed Performances: - 150 ps Typical Gate Delay @3.3V - Typical 600 MHz Toggle Frequency @3.3V - Typical 360 MHz Toggle Frequency @2.5V High System Frequency Skew Control: - Clock Tree Synthesis Software Low Power Consumption: - 0.25 W/Gate/ MHz @3.3V - 0.18 W/Gate/ MHz @2.5V Power on Reset Standard 2, 4, 6, 8,10, 12 and 18mA I/Os CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core Thick oxide matrices allowing 5V tolerance * * * * * * * 0.35 m ULC Series with Embedded DPRAM UA1E Preliminary * Description The UA1 series of ULCs is well suited for conversion of large sized CPLDs and FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from 46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks. Devices are implemented in high-performance CMOS technology with 0.35m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing. Conversion to the UA1 series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1 series has a very low standby consumption of 0.3nA/gate typically commercial temperature, which would yield a standby current of 42A on a 144,000 gates design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. Rev. A - 17-Dec-01 1 The UA1 series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available if required. The UA1 series is designed to allow conversion of high performance 3.3V devices as well as 2.5V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption. Array Organization Table 1. Matrices Part Number USD700 USD600 USD484 USD432 USD352 USD312 USD256 USD228 USD208 USD160 Max Pads 700 600 484 432 352 312 256 228 208 160 KGates 780 625 445 374 244 150 124 98 89 46 DPRAM Kbits 390 290 187 144 94 72 48 38 32 18 Architecture The basic element of the UA1 family is called a cell. One cell can typically implement between one to four FPGA gates. Cells are located contiguously throughout the core of the device, with routing resources provided in three to four metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. In order to improve noise immunity within the device, separate VDD and V SS busses are provided for the internal cells and the I/O cells. I/O buffer interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator could be located close to each buffer. Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen option. 36mA achievable, using 2 pads. I/O Options 2 UAE1 Rev. A - 17-Dec-01 UAE1 Slew Rate Controlled Output Buffer In this mode, the p- and n-output transistors commands are delayed, so that they are never set "ON" simultaneously, resulting in a low switching current and low noise. These buffers are dedicated to very high load drive. 2.5V Compatibility The UA1 series of ULC's is fully capable of supporting high-performance operation at 2.5V or 3.3V. The performance specifications of any given ULC design however, must be explicitly specified as 2.5V, 3.3V or both. The speed and density of the UA1 technology cause large switching current spikes, for example when: * * 16 high current output buffers switch simultaneously, or 10% of the 700 000 gates are switching within a window of 1ns. Power Supply and Noise Protection Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the setting time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the UA1 core matrix, several mechanisms have been implemented inside the UA1 arrays. Two types of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O buffers switching protection Three features are implemented to limit the noise generated by the switching current: * * * The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed. Matrix switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: * * Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the V DD supply of the matrix to the external world via the output buffers. * 3 Rev. A - 17-Dec-01 Electrical Characteristics Absolute Maximum Ratings Operating Temperature Commercial..........................................................0 to 70C Industrial...............................................................-40 to 85C Max Supply Core Voltage (VDD)..........................3.6V Max Supply Periphery Voltage (VDD5).................3.6V Input Voltage (VIN)V DD.............................................+0.5V 5V Tolerant/Compliant VDD5................................+0.5V Storage Temperature...........................................-65 to 150C Operating Ambient Temperature.......................-55 to 125C 4 UAE1 Rev. A - 17-Dec-01 UAE1 DC Characteristics 2.5V Symbol TA VDD IIH Parameter Operating Temperature Supply Voltage High level input current Specified at VDD = +2.5V + 5% Buffer All All CMOS PCI Min -40 2.3 2.5 Typ Max +85 2.7 10 10 -10 A VIN = VSS,VDD = VDD (max) Unit C V A VIN = VDD,VDD = VDD (max) Conditions IIL Low Level input current CMOS PCI IOZ High-Impedance State Output Current Output short-circuit current All -10 10 A VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) IOS PO11 PO11 9 6 0.7VDD 0.475VDD 0.7VDD 1.5 0.3VDD 0.325VDD 1.0 0.5 0.7VDD 0.9VDD 0.4 0.1VDD 0.3VDD mA VIH High-level Input Voltage CMOS PCI CMOS Schmitt V VIL Low-Level Input Voltage CMOS PCI CMOS Schmitt V Vhys VOH Hysteresis High-Level output voltage CMOS Schmitt PO11 PCI V V IOH = 1.4mA,VDD = VDD (min) IOH = -500A VOL Low-Level output voltage PO11 PCI V IOL = 1.4mA,VDD = VDD (min) IOL = 1.5mA 5 Rev. A - 17-Dec-01 3.3V Symbol TA VDD IIH Parameter Operating Temperature Supply Voltage High level input current Specified at VDD = +3.3V + 5% Buffer All All CMOS PCI Min -40 3.0 3.3 Typ Max +85 3.6 10 10 -10 A VIN = VSS,VDD = VDD (max) Unit C V A VIN = VDD,VDD = VDD (max) Conditions IIL Low Level input current CMOS PCI IOZ High-Impedance State Output Current Output short-circuit current All -10 10 A VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) IOS PO11 PO11 14 -9 2.0 0.475VDD 2.0 1.7 0.8 0.325VDD 1.1 0.6 0.7VDD 0.9VDD 0.4 0.1VDD 0.8 mA VIH High-level Input Voltage CMOS, LVTTL PCI CMOS Schmitt V VIL Low-Level Input Voltage CMOS PCI CMOS/TTL-level Schmitt V Vhys VOH Hysteresis High-Level output voltage TTL-level Schmitt PO11 PCI V V IOH = 2mA,VDD = VDD (min) IOH = -500A VOL Low-Level output voltage PO11 PCI V IOL = 2mA,VDD = VDD (min) IOL = 1.5mA 6 UAE1 Rev. A - 17-Dec-01 UAE1 5V Symbol TA VDD VDD5 IIH Parameter Operating Temperature Supply Voltage Supply Voltage High level input current Specified at VDD = +5V +/- 5% Buffer All 5V Tolerant 5V Compliant CMOS PCI IIL Low Level input current CMOS PCI IOZ High-Impedance State Output Current Output short-circuit current All -10 10 A VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD,VDD = VDD (max) VOUT = VSS,VDD = VDD (max) -10 Min -55 3.0 4.5 3.3 5.0 Typ Max +125 3.6 5.5 10 10 A VIN = VSS,VDD = VDD (max) Unit C V V A VIN = VDD,VDD = VDD (max) Conditions IOS PO11V PO11V 8 -7 2.0 0.475VDD 2.0 5.0 5.0 1.7 0.5VDD 0.8 0.325VDD 1.1 0.6 0.7VDD 0.7VDD5 0.5 0.5 0.8 5.5 5.5 mA VIH High-level Input Voltage PICV, PICV5 PCI CMOS/TTL-level Schmitt V VIL Low-Level Input Voltage PICV, PICV5 PCI CMOS/TTL-level Schmitt V Vhys VOH Hysteresis High-Level output voltage TTL-level Schmitt PO11V PO11V5 V V IOH = -1.7mA IOH = -1.7mA VOL Low-Level output voltage PO11V PO11V5 V IOL = 1.7mA I/O Buffer Symbol C C IN Parameter Capacitance, Input Buffer (Die) Capacitance, Output Buffer (Die) Capacitance, Bidirectional Typ 2.4 5.6 6.6 Unit pF pF pF Conditions 3.3V 3.3V 3.3V OUT C I/O 7 Rev. A - 17-Dec-01 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 436-4270 FAX (408) 436-4314 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 436-4270 FAX (408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-28-19-60 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-32-43 FAX (33) 4-76-58-33-20 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-64-21 FAX (33) 4-42-53-62-88 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-015 FAX (44) 1355-242-743 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel, the Atmel logo and combinations thereof and others contained herein are trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. |
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