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19-0524; Rev 1; 8/06
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
General Description
The MAX9471/MAX9472 multipurpose clock generators are ideal for consumer and communication applications. The MAX9471/MAX9472 feature two buffered phase-locked loop (PLL) outputs that can be independently set from 4MHz to 200MHz. These devices also provide one (MAX9472) or two (MAX9471) buffered outputs of the reference clock. The MAX9471 outputs a set of MPEG/AC3 audio and video frequencies most commonly used in consumer applications. The MAX9472 outputs a set of common audio frequencies. These frequencies are selected through an I2C interface (MAX9471) or by setting the three-level FS pins. The MAX9471/MAX9472 feature a one-time-programmable (OTP) ROM, allowing one-time programming of the two PLL outputs. The MAX9471/MAX9472 include two basic configurations. In one configuration, the OTP ROM sets PLL1 output to any frequency between 4MHz to 200MHz, and the I2C interface (MAX9471) or programmable pins set the PLL2 output frequency to a set of audio and video frequencies. In the other configuration, the OTP ROM sets both PLL1 and PLL2 frequencies to fixed values between 4MHz to 200MHz. In both cases, the reference output is available, but the OTP ROM can disable it. The OTP ROM on the MAX9471/MAX9472 is factory set based on the customer requirements. Contact the factory for samples with preferred frequencies. The devices operate from a 3.3V supply and are specified over the -40C to +85C extended temperature range. The MAX9471 is available in a 20-pin TQFN package. The MAX9472 is available in a 14-pin TSSOP package.
Features
5MHz to 50MHz Input Clock Reference Crystal or Input-Clock-Based Reference Two Fractional-N Feedback PLLs (4MHz to 200MHz) with Buffered Outputs Two Buffered Outputs of Reference Clock OTP for Factory-Preset PLL Frequencies Available (Contact Factory) Programmable Through I2C Interface or ThreeLevel Logic Pins for Video or Audio Clocks Low-RMS Jitter PLL (14ps for 45MHz) Integrated VCXO with 200ppm Tuning Range Available in 20-Pin TQFN and 14-Pin TSSOP Packages +3.3V Supply -40C to +85C Temperature Range
Ordering Information
PART MAX9471ETP+** MAX9472EUD+** TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 14 TSSOP PKG CODE U14-2
20 TQFN-EP* T2055-5
*EP = Exposed pad. **Marking is for samples only. Contact factory for ordering information. +Denotes lead-free package.
Pin Configurations
Digital TVs Communication Systems Data Networking Systems Set-Top Boxes Home Entertainment Centers Multimedia PCs
VDD X2 X1 FSO/SCL FS1/SDA 16 17 18 19 20 1 2 3 4 5
TOP VIEW
15
14
13
12
11
GND
VDD
VDD
FS2
Applications
PD
10 9
GND I.C. CLK4 CLK3 CLK2
MAX9471
8 7 6
Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
+
VDDA
TUNE
GND
TQFN (5mm x 5mm) Pin Configurations continued at end of data sheet. 1
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AGND
CLK1
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V VDDA to AGND ......................................................-0.3V to +4.0V AGND to GND ......................................................-0.3V to +0.3V All Other Pins to GND ..................................-0.3V to VDD + 0.3V Short-Circuit Duration (all LVCMOS outputs)..............................................Continuous ESD Protection (Human Body Model)..................................2kV Continuous Power Dissipation (TA = +70C) 20-Pin TQFN (derate 21.3mW/C above +70C) .......2758mW 14-Pin TSSOP (derate 9.1mW/C above +70C) ......796.8mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V and TA = -40C to +85C. Typical values at VDD = VDDA = 3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Input High Level Input Low Level Input Current High Level Input Current Low Level Input High Level Input Low Level Input Open Level Input Current SYMBOL VIH1 VIL1 IIH1 IIL1 VIH2 VIL2 VIO2 IIL2, IIH2 VIL2 = 0 or VIH2 = VDD 1.27 -10 0.7 x VDD 0.3 x VDD -1 ISINK = 4mA (Note 3) VDD 0.6 0.4 3.0 3.0 CLK1 at 125MHz and CLK2 at 74.1758MHz; all outputs not loaded PD = low 12 60 3.6 3.6 8.4 +1 0.4 VIN = VDD VIN = 0 -20 2.5 0.8 2.10 +10 CONDITIONS MIN 2.0 0 TYP MAX VDD 0.8 20 UNITS V V A A V V V A
LVCMOS INPUTS (PD, X1 as a reference INPUT CLK)
THREE-LEVEL INPUTS (FS0, FS1, FS2, as FS2 = open)
SERIAL INTERFACE (SCL, SDA) (Note 2) (MAX9471) Input High Level Input Low Level Input-Leakage Current Low-Level Output Input Capacitance CLOCK OUTPUTS (CLK_) Output High Level Output Low Level POWER SUPPLIES Digital Power-Supply Voltage Analog Power-Supply Voltage Total Current for Digital and Analog Supplies Total Power-Down Current VDD VDDA IDC IPD V V mA A VOH VOL IOH = -4mA IOL = 4mA V V VIH VIL IIH, IIL VOL CI V V A V pF
2
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Multiple-Output Clock Generators with Dual PLLs and OTP
AC ELECTRICAL CHARACTERISTICS
(VDD = VDDA = +3.0V to +3.6V, TA = -40C to +25C. Typical values are at VDD = VDDA = 3.3V, TA = +25C with fXTL = 27MHz, unless otherwise noted.) (Note 3)
PARAMETER OUTPUT CLOCKS (CLK1, CLK2) Minimum Frequency Range Maximum Frequency Range Clock Rise Time Clock Fall Time Duty Cycle Output Period Jitter JP fOUT fOUT tR tF fIN = 5MHz to 50MHz fIN = 5MHz to 50MHz, CL < 5pF 20% to 80% of VDD, CL = 10pF, fOUT = 74.1758MHz (Figure 5) 80% to 20% of VDD, CL = 10pF, fOUT = 74.1758MHz (Figure 5) fOUT = 74.1758MHz, CL = 10pF 125MHz, CL = 5pF, fIN = 27MHz 74.1758MHz, CL = 10pF, fIN = 27MHz SDA from low to high, fOUT = 71.1758MHz, fIN = 13MHz (Figure 6) (Figure 6) 42 4 133 200 1.4 1.2 50 26.3 33.6 RMSps 58 MHz MHz ns ns % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9471/MAX9472
Soft Power-On Time Hard Power-On Time VCXO CLOCKS (CLK3, CLK4) Crystal Frequency Crystal Accuracy Tuning Voltage Range VCXO Tuning Range TUNE Input Impedance Output CLK Accuracy Output Duty Cycle Output Period Jitter Output Rise Time Output Fall Time
tFST tPO1 fXTL VTUNE
1 15 27 30 0.0 3.0 200 95 50 40 50 36 1.4 1.4 60
ms ms MHz ppm V ppm k ppm % RMSps ns ns
VTUNE = 0 to 3V, C1 = C2 = 4.0pF ZTUNE VTUNE = 1.5V, C1 = C2 = 4.0pF CL = 10pF load, CLK3 CL = 10pF tR tF 20% to 80% of VDD (Figure 5), CL = 10pF 80% to 20% of VDD (Figure 5), CL = 10pF
150
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3
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
SERIAL-INTERFACE TIMING CHARACTERISTICS (MAX9471)
(VDD = VDDA = +3.3V, TA = -40C to +85C, unless otherwise noted.) (Note 1, Figure 2)
PARAMETER Serial Clock Bus Free Time Between STOP and START Conditions Hold Time, Repeated START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock Low Period SCL Clock High Period Rise Time of SDA and SCL, Receiving Fall Time of SDA and SCL, Receiving Fall Time of SDA, Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line SYMBOL fSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tSU,DAT tLOW tHIGH tR tF tF,TX tSP Cb (Notes 3, 5) (Notes 3, 5) (Notes 3, 6) (Notes 3, 7) (Note 3) (Note 4) 1.3 0.6 0.6 0.6 15 100 1.3 0.7 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0 300 300 250 50 400 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s ns ns s s ns ns ns ns pF
Note 1: All parameters are tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 2: No high-output level is specified, only the output resistance to the bus. Pullup resistors on the bus provide the high-level voltage. Note 3: Guaranteed by design. Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 5: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VDD and 0.7 x VDD. Note 6: Bus sink current is less than 6mA. Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
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Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
Typical Operating Characteristics
(VDD = VDDA = +3.3V, TA = +25C, fXTL = 27MHz, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9471/2 toc01
RISE TIME vs. TEMPERATURE
MAX9471/2 toc02
FALL TIME vs. TEMPERATURE
CL = 10pF fXTAL = 27MHz fCLK1 = 66MHz
MAX9471/2 toc03
20
fCLK1 = 125MHz fCLK2 = 74.1758MHz
2.2
16 SUPPLY CURRENT (mA)
1.8 RISE TIME (ns)
CL = 10pF fXTAL = 27MHz fCLK1 = 66MHz
2.2
1.8 FALL TIME (ns)
12
1.4
1.4
8
1.0
1.0
4
0.6
0.6
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0.2 -40 -15 10 35 60 85 TEMPERATURE (C)
0.2 -40 -15 10 35 60 85 TEMPERATURE (C)
JITTER vs. TEMPERATURE
35 30 JITTER (ps) 25 20 15 10 5 0 -40 -15 10 35 60 85 fCLK1 = 66MHz fCLK1 = 33MHz CLK1 1V/div CL = 10pF fXTAL = 27MHz
MAX9471/2 toc04
33MHz OUTPUT
MAX9471/2 toc05
66MHz OUTPUT
MAX9471/2 toc06
40
CLK1 1V/div
10ns/div
10ns/div
TEMPERATURE (C)
125MHz CLK OUTPUT
MAX9471/2 toc07
DUTY CYCLE vs. TEMPERATURE
MAX9471/2 toc08
VCXO TUNING RANGE vs. VCXO ACCURACY
fIN = 27MHz fOUT = 45MHz 4pF 5pF 100 0 -100 -200 -300 6pF
MAX9741/2 toc09
55
CL = 10pF fXTAL = 27MHz
300 200 VCXO ACCURACY (PPM)
53 DUTY CYCLE (%)
CLK1 1V/div
51 fCLK1 = 33MHz 49
47
fCLK1 = 66MHz
45 4ns/div -40 -15 10 35 60 85 TEMPERATURE (C)
0
0.5
1.0
1.5
2.0
2.5
3.0
VCXO TUNING RANGE (V)
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5
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
Typical Operating Circuit/Block Diagram
+3.3V 0.1F VDDA* X1 27MHz C1 VCXO C2 X2 TUNE FS0/SCL SERIAL INTERFACE FS1/SDA FS2* CLK3 AGND* CLK4* GND OTP PLL2 CLK2 PLL1 CLK1 VDD +3.3V 0.1F x 3
MAX9471 MAX9472
VDD VDD*
*MAX9471 ONLY.
Pin Description
PIN MAX9471 1 2 3 4, 10, 11 5 6 7 8 9 12, 13, 16 14 15 17 18 19 20 -- -- EP MAX9472 5 -- -- 6, 10, 11 7 8 9 -- -- 4, 12 -- 13 14 1 -- -- 2 3 -- NAME TUNE VDDA AGND GND CLK1 CLK2 CLK3 CLK4 I.C. VDD FS2 PD X2 X1 FS0/SCL FS1/SDA FS1 FS0 EP FUNCTION VCXO Tune Voltage Input. If using a reference clock input, connect TUNE to VDD. Analog Power Supply. Bypass to GND with a 0.1F capacitor. Analog Ground Ground Output Clock 1. PLL1 buffered output. Output Clock 2. PLL2 buffered output. Output Clock 3. VCXO buffered output. Output Clock 4. VCXO buffered output. Internally Connected. Leave unconnected. Power Supply. Bypass to GND with a 0.1F capacitor. Function Select 2 Active-Low, Power-Down Input. Pull high for normal operation, drive PD low to place MAX9471/MAX9472 in power-down mode. Crystal Connection 2. Leave open if using a reference clock. Crystal Connection 1 or Reference Clock Input Function Select 0/Serial Clock. Set FS2 high to place the device in I2C mode (see Table 1). Function Select 1/Serial Data. Set FS2 high to place the device in I2C mode (see Table 1). Function Select 1 Function Select 0 Exposed Pad (MAX9471 only). Connect EP to GND.
6
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Multiple-Output Clock Generators with Dual PLLs and OTP
Detailed Description
The MAX9471/MAX9472 have two programmable fractional-N feedback PLLs so that almost any frequencies between 4MHz to 200MHz can be generated. The MAX9471 provides four outputs: two for the PLLs and two for the reference clock. The MAX9472 provides three outputs: two for the PLLs and one for the reference clock. The crystal frequency can be between 5MHz and 30MHz. The internal VCXO has a fine-tuning range of 200ppm. Choosing different C1 and C2 capacitors allows flexibility for centering the various crystals. See theTypical Operating Characteristics for an example. To use the MAX9471/MAX9472 as a synthesizer with an input reference clock, connect the input clock to X1 and TUNE to VDD, and leave X2 unconnected. This configuration is for applications where the micro tuning is not needed, and there is a system reference clock available.
MAX9471/MAX9472
One-Time Programmable Memory
The MAX9471/MAX9472 feature a factory-configurable, OTP memory for nonvolatile applications allowing for simple and permanent clock generation. Contact the factory for presetting the MAX9471/MAX9472 to requested frequencies. Using OTP, the MAX9471/MAX9472 can be configured to two different configurations. One configuration is to have PLL1 set to any frequency between 4MHz to 200MHz and select the PLL2's frequency by I 2 C (MAX9471) or programmable pins. The second configuration is to preset the frequencies in PLL1 and PLL2 to fixed values between 4MHz to 200MHz. In both cases, the reference output is available, but it can be disabled by OTP. At power-up, all the outputs are enabled.
Power-Down
Driving PD low places the MAX9471/MAX9472 in power-down mode. PD overrides all other functions, setting all outputs to high impedance and shutting down the two PLLs. Every output has an 80k (typ) internal pulldown resistor.
Voltage-Controlled Crystal Oscillator (VCXO)
The MAX9471/MAX9472s' internal VCXO produces a reference clock for the PLLs used to generate the output clocks. The oscillator uses a crystal clock as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a range of 200ppm. The tuning voltage VTUNE can vary from 0V to 3V as shown in Figure 1. The crystal should be AT cut and oscillate on its fundamental mode with 30ppm accuracy. The crystal shunt capacitor should be less than 10pF, including board parasitic capacitance. To achieve up to 200ppm pullability, the crystal-loading capacitance should be less than 14pF. The VCXO is a free-running oscillator. It starts oscillating with an internal POR signal and can be disabled by PD. VCXO settles at approximately 5ms at power-on and 10s at a change of the VTUNE voltage.
Frequency Selection of CLK2 Output
The OTP ROM can set PLL2's output to be selectable from a group of frequencies that are common for MPEG video and audio applications. The frequency selection can be done by the FS_ inputs or through the I2C interface (MAX9471). For the MAX9471, pull FS2 high (Table 1) to select the PLL2 frequency through the I2C interface. Otherwise, the frequencies are selected according to Table 2. For the MAX9471, Table 3 shows the mappings for I2C programming.
Serial Interface (MAX9471)
27.0054
VCXO OUTPUT FREQUENCY (MHz)
+200ppm
27.00
The MAX9471 can be programmed through a 2-wire, I2C-compatible serial interface. The device is activated after power-up and FS2 = high. The device operates as a slave that sends and receives data through clock line SCL and data line SDA for bidirectional communication with the master. A master (typically a microcontroller) initiates all data transfers to and from the MAX9471 and
-200ppm
Table 1. Mode Selection by FS2 (MAX9471 Only)
FS2 MODE Pin programmable I2C enabled
3V VTUNE
26.9946 0
Low or open High
Figure 1. VCXO Tuning Range for a 27MHz Crystal
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7
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
Table 2. MAX9471/MAX9472 Frequency Selection at CLK2
FS2 Open Open Open Open Open Open Open Open Open Low Low Low Low Low Low Low High FS1 Open Open Open Low Low Low High High High Open Open Open High Low Low Low X FS0 Open Low High High Open Low High Open Low High Open Low High Low High Open X FREQUENCY (MHz) 4.096 6.144 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 9.216 16.9344 18.4320 33.8688 36.864 74.1758241 74.25 54.054 Disable three-level pins and enable I2C AUDIO FREQUENCIES 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Table 3. MAX9471 I2C Frequency Selection at CLK2 (FS2 = High)
A4 A3 A2 0 0 1 1 0 0 1 1 0 0 1 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 FREQUENCY (MHz) 4.096 6.144 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 9.216 16.9344 18.4320 33.8688 36.864 74.1758241 74.25 54.054 AUDIO FREQUENCIES
VIDEO FREQUENCIES
0 0 VIDEO FREQUENCIES 0 1 1 1 0 1
*MAX9472 can be programmed to FS2 = open settings only.
SDA tSU, DAT tLOW SCL tHIGH tHD, STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tSU, STO tBUF
Figure 2. I 2C Timing Diagram
generates the SCL clock that synchronizes the data transfer. The SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7k, is required on SDA. The SCL line operates only as an
8
input. A pullup resistor, typically 4.7k, is required on SCL if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain SCL output. Figure 2 is the I2C timing diagram.
_______________________________________________________________________________________
Multiple-Output Clock Generators with Dual PLLs and OTP
Device Address
The default I2C address for the MAX9471 is factory set to 1100111. Contact factory for different addresses. START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. The active master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3). Data Transfer and ACK Following the START condition, each SCL clock pulse transfers 1 bit. Between a START and a STOP, multiple bits are transferred on the 2-wire bus. The first 7 bits are for the device address. Bit 8 indicates the writing (low) or reading (high) operation (R/W). Bit 9 is the ACK for the address and operation type. The next 8 bits (bit 10 to bit 17) form the content byte. The next bit, bit 18, is the ACK for the content byte. The master always transfers the first 8 bits (address + R/W). The slave (MAX9471) may receive a content byte from the bus or transfer a content byte to the bus. The ACK bits are transmitted by the address or content recipient. A lowACK bit indicates a successful transfer; otherwise, a high-ACK bit indicates an unsuccessful transfer. More content bytes can be continuously transferred until the master sends a STOP. For the MAX9471 data writing, after the 9 bits with the slave ID, R/W, and ACK, 1 data byte is sent to the MAX9471 from the master. Figure 4 shows the structure of the data transfer. Figure 5 shows CLK_ rise and fall times.
MAX9471/MAX9472
SDA
SCL
S START CONDITION
P STOP CONDITION
Figure 3. START and STOP Diagram
MASTER-WRITE DATA STRUCTURE S SLAVE ADDRESS W A A DATA A A P
MASTER-READ DATA STRUCTURE S SLAVE ADDRESS R A A DATA A A P
MASTER TRANSFERS TO SLAVE
A = ACK; A = 0: SUCCESSFUL, A = 1: UNSUCCESSFUL S = START CONDITION P = STOP CONDITION
SLAVE TRANSFERS TO MASTER
Figure 4. Serial-Interface Data Structure
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9
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
tR CLK_ 20% 80% 80%
tF
20%
RISE AND FALL TIME MEASURES BETWEEN 20% AND 80%.
Figure 5. CLK_ Rise and Fall Times
VDD
2.2V
t
STOP PULSE AFTER WRITING STOP EDGE
SDA (MAX9471)
CLK1 OR CLK2 tPO1 tFST
CLK3 OR CLK4 tPO2
Figure 6. VCXO and PLL Timing Diagram
10
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Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
Applications Information
Crystal Selection
When using a crystal with the MAX9471/MAX9472s' internal oscillator, connect the crystal to X1 and X2. Choose an AT-cut crystal that oscillates on its fundamental mode with 30ppm and loading capacitance less than 14pF. To achieve a wide VCXO tuning range, select a crystal with motional capacitance greater than 7fF and connect 6pF or less shunt capacitors at X1 and X2 to ground. When the VCXO is used as an oscillator, select both shunt capacitors to be approximately 13pF. The optimal shunt capacitors for achieving minimum frequency offset can be determined experimentally.
TOP VIEW
X1 1 FS1 2 FS0 3 VDD 4 TUNE 5 GND 6 CLK1 7
Pin Configurations (continued)
+
14 X2 13 PD 12 VDD
MAX9472
11 GND 10 GND 9 8 CLK3 CLK2
Board Layout Considerations and Bypassing
The MAX9471/MAX9472s' oscillator frequencies make proper layout important to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock output. Return GND to the highest quality ground available. Bypass each VDD and VDDA with a 0.1F capacitor, placed as close as possible to the device. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs.
TSSOP
Chip Information
PROCESS: CMOS
______________________________________________________________________________________
11
Multiple-Output Clock Generators with Dual PLLs and OTP MAX9471/MAX9472
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
12
______________________________________________________________________________________
Multiple-Output Clock Generators with Dual PLLs and OTP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX9471/MAX9472
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
G
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2006 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.

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