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| INTEGRATED CIRCUITS DATA SHEET TDA1373H General Digital Input (GDIN) Product specification Supersedes data of 1995 Aug 28 File under Integrated Circuits, IC01 1996 Jul 17 Philips Semiconductors Product specification General Digital Input (GDIN) FEATURES * Four operating modes: - Sample Rate Conversion (SRC) mode - AD/DA mode - SLAVE-VCO mode - SLAVE-VCXO mode * Full digital sample rate conversion over a wide range of input sample rates * Fast and automatic detection and locking to the input sample rate with continuous tracking * Digital Phase-Locked Loop (PLL) with adaptive bandwidth which removes jitter on the digital audio input * Audio outputs (soft) muted during loop acquisition * Full linear phase processing based on all-FIR filtering * Integrated full digital IEC 958 demodulator for digital input signals (AES/EBU or SPDIF format) with intelligent error handling * Extended input sample frequency range * IEC 958 Channel Status (CS) and User Channel (UC) outputs * On-chip CS and/or UC demodulation and buffering (consumer and professional format) * Dedicated subcode processing for Compact Disc (CD) * Final output quantization to 16, 18 or 20 bits with optional in-audio-band noise shaping * Bitstream input and output for coupling with 1-bit analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) * * I2S I2S and Japanese serial input formats supported for SRC and DAC functions and Japanese serial output formats supported for SRC and ADC functions * 5 V power supply TDA1373H * 0.7 m double metal Complementary Metal Oxide Semiconductor (CMOS) * SRC THD + N: - -113 dB over the 0 to 20 kHz band (1 kHz, 20 bits input and output) (see Fig.3) - -95 dB over the 0 to 20 kHz band (1 kHz, 16 bits input and output) * Pass band ripple smaller than 0.004 dB for up-sampling and down-sampling filters * Stop band suppression: - selectable between 70 dB and 50 dB for 64x up-sampling filters - 80 dB for 128x down-sampling filters * Microcontroller operated and stand-alone mode. APPLICATIONS * Professional audio equipment for: - mixing - recording - editing - broadcasting * CD-Recordable (CD-R) * Digital Speaker Systems (DSS) * Digital Compact Cassette recorders (DCC) * Digital Audio Tape (DAT) and MD recorders * Digital amplifiers * Jitter killers. * I2S and Japanese 4x oversampled serial output available for SRC and ADC functions * 8-bit digital gain/attenuation control * Switchable Digital Signal Processor (DSP)-interface (I2S input and output) for additional audio processing * Additional clock outputs available at 768, 384, 256 and 128fso * 3-line serial microcontroller interface, compatible with the Philips CD I.C. protocol (HCL) 1996 Jul 17 2 Philips Semiconductors Product specification General Digital Input (GDIN) GENERAL DESCRIPTION The TDA1373H is a General Digital Input (GDIN) device for audio signals which is able to perform a high-quality sample rate conversion of digital audio signals (SRC mode). The device reads several serial input formats and signals in the IEC 958 digital audio format (also known as AES/EBU or SPDIF signals). For this purpose a full Audio Digital Input Circuit (ADIC) is present in the device. An internal digital PLL results in extensive jitter removal from incoming digital audio signals without any analog loop electronics. The standard 20 bit output word length can be limited to 16 or 18 bits by means of `in-audio-band noise shaping'. TDA1373H The GDIN digital filters can also be reused for Bitstream ADC and DAC conversion (AD/DA mode). The internal digital PLL can be reconfigured to operate the GDIN in a slave mode, where the output sample frequency of the device is locked to the incoming sample rate (SLAVE-VCO and SLAVE-VCXO modes). The combination of an ADIC function, sample rate conversion and Bitstream ADC and DAC results in a device with a highly versatile functionality and large replacement value in consumer and professional audio sets. QUICK REFERENCE DATA All inputs and outputs CMOS compatible; unless otherwise specified. SYMBOL Supply VDD IDD(tot) Ptot supply voltage total supply current total power dissipation fso > 44.1 kHz fso 44.1 kHz fso = 44.1 kHz fso = 44.1 kHz fso = 49 kHz; VDD = 5.5 V IEC 958 input DI1S (high-sensitivity IEC input) Vi(p-p) AC input voltage (peak-to-peak value) 0.2 - VDD V 4.75 4.5 - - - 5 5 155 775 1030 5.5 5.5 - - - V V mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Clock and timing fso(max) Temperature Tamb operating ambient temperature 0 70 C maximum output sample frequency VDD = 4.75 V 49 55 - kHz ORDERING INFORMATION TYPE NUMBER TDA1373H PACKAGE NAME QFP64 DESCRIPTION Plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION SOT319-1 1996 Jul 17 3 Philips Semiconductors Product specification General Digital Input (GDIN) BLOCK DIAGRAM TDA1373H VDDD VDDD VDDD BS 52 34 CUS 36 CEN 35 CL LD DA 47 45 46 V V SSA4 DDA4 XTLO CLI 23 768f so CLO1 CLO2 CLO3 CLO4 27 384f so 28 30 256f so 128f so 25 31 handbook, full pagewidth VDDD 7 VDDD 11 32 VDDD 39 14 XTLI 21 19 20 22 MU EM LOCK SA DI1D DI1O DI1S VDDA1 VSSA1 44 37 48 43 62 63 DI1 1 3 2 DATA SLICER ADIC (IEC 958 DECODER) U PV C WS PO USER CHANNEL EXTRACTION MICROCONTROLLER INTERFACE/ STAND-ALONE CONTROL CRYSTAL OSCILLATOR CLOCK SHOP MM1 CHANNEL STATUS EXTRACTION GENERAL CONTROL 64f so DI2 PHASE DETECTOR LOOP FILTER HOLD MM0 VCO FSL FIFO AND GAIN 4x UPSAMPLING 16 x UPSAMPLING VARIABLE HOLD 10 DO2 I2 S OUT 16 6 DO2D DO2W DO2C TST1 TST2 RST AIL AIR 42 41 38 4 5 stereo FOS DI2 AOS ATTENUATOR HOLD BITSTREAM DIGITAL FILTER INS DNI 32 x DOWNSAMPLING 4x DOWNSAMPLING IN-BAND NOISE SHAPER 50 DSO DO1D IS OUT 2 49 51 DO1W DO1C 9 15 DAC OUTPUT 18 AOL1 AOR1 CLD TDA1373H I 2S OUT 55 56 54 I 2S IN 57 59 60 8 12 VSSD 13 VSSD 17 VSSD 24 VSSD 26 VSSD 29 VSSD 33 VSSD 40 VSSD 53 VSSD 58 VSSD 61 VSSD 64 MLC334 - 2 FOD FOC FOW DI2D DI2W DI2C VSSD VSSD Switches MM1 and MM0 are controlled indirectly via the mode selection. All other switches can be controlled directly by the user. Fig.1 Block diagram. 1996 Jul 17 4 Philips Semiconductors Product specification General Digital Input (GDIN) PINNING SYMBOL DI1S VSSA1 VDDA1 AIL AIR DO2C VDDD VSSD AOL1 DO2D VDDD VSSD VSSD VDDD AOR1 DO2W VSSD CLD VDDA4 VSSA4 XTLI XTLO CLI VSSD FSL VSSD CLO1 CLO2 VSSD CLO3 CLO4 VDDD VSSD BS CEN CUS EM PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 DESCRIPTION IEC 958 digital audio input `S' (200 mV peak-to-peak value) IEC 958 slicer analog ground IEC 958 slicer analog supply voltage Bitstream audio input left Bitstream audio input right serial digital audio output 2; bit clock output (192fso) digital supply voltage; note 1 digital ground; note 2 Bitstream audio output left DLO = 0; serial digital audio output 2; data; DLO = 1; Bitstream audio output left inverted (AOL1); note 3 digital supply voltage; note 1 digital ground; note 2 digital ground; note 2 digital supply voltage; note 1 Bitstream audio output right DLO = 0; serial digital audio output 2; word select output (4fso); DLO = 1; Bitstream audio output right inverted (AOR1); note 3 digital ground; note 2 Bitstream DAC clock (192 or 128fso) oscillator analog supply voltage oscillator analog ground crystal input 768fso crystal output external VCO input (SLAVE-VCO mode only) digital ground; note 2 SA = 0 (microcontroller operated) external VCO output (slave modes only); SA = 1 (stand-alone control) DI11 control line; note 4 digital ground; note 2 clock output 768fso clock output 384fso digital ground; note 2 clock output 256fso clock output 128fso; digital supply voltage; note 1 digital ground; note 2 block sync; channel status/user channel/CD subcode data enable; channel status/user channel/CD subcode data bit; channel status/user channel/CD subcode IEC 958 source pre-emphasis flag TDA1373H TYPE E036A E038A E037A HPP01 HPP01 OPF40 - - OPF40 OPF40 - - - - OPF40 OPF40 - OPF43 E037A E038A OSX01 OSX01 HPP01 - HOF21 - OPF40 OPF40 - OPF40 OPF40 - - OPF40 OPF40 OPF40 OPF20 1996 Jul 17 5 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SYMBOL RST VDDD VSSD TST2 TST1 SA MU LD DA CL LOCK DO1W DO1D DO1C VDDD VSSD FOW FOD FOC DI2D VSSD DI2W DI2C VSSD DI1D DI1O VSSD Notes PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DESCRIPTION power-on reset input (active LOW) digital supply voltage; note 1 digital ground; note 2 test pin 2 (LOW for normal operation) test pin 1 (LOW for normal operation) Stand-alone/microcontroller operated selection; SA = 1 for stand-alone operation mute flag (active HIGH) SA = 0 (microcontroller operated) microcontroller interface; load (read/write); SA = 1 (stand-alone control) NSD control line; note 4 SA = 0 (microcontroller operated) microcontroller interface (data); SA = 1 (stand-alone control) DI2 control line; note 4 SA = 0 (microcontroller operated) microcontroller interface (clock); SA = 1 (stand-alone control) QU1/QU0 control line; note 4 ADIC lock flag (active HIGH) serial digital audio output 1; word select input/output (fso) serial digital audio output 1; data serial digital audio output 1; bit clock input/output (48fso) digital supply voltage; note 1 digital ground; note 2 serial digital audio feature output; word select serial digital audio feature output; data serial digital audio feature output; bit clock (64fso) serial digital audio input 2; data digital ground; note 2 serial digital audio input 2; word select serial digital audio input 2; bit clock output digital ground; note 2 SA = 0 (microcontroller operated) IEC 958 digital audio input `D' (CMOS level); SA = 1 (stand-alone control) MSO control line; note 4 IEC 958 digital audio input `O' (CMOS level) digital ground; note 2 TYPE HPP07 - - HPP01 HPP01 HPP01 OPF40 HPP01 HOF41 HPP01 OPF40 HOF41 OPF43 HOF41 - - OPF43 OPF43 OPF43 HPP01 - HOF21 HOF21 - HPP01 HPP01 - 1. All VDDD pins are internally connected. 2. All VSSD pins are internally connected. 3. DLO is a command flag from register 4 (see Section "Command registers"). 4. SA is the stand-alone/microcontroller operated pin (pin 43). DI11, NSD, DI2, QU1, QU0 and MS0 are command flags to control the operation of the device. For more information see Section "Controlling the GDIN". 1996 Jul 17 6 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H handbook, full pagewidth DI1S V SSA1 V DDA1 AIL AIR DO2C V DDD V SSD AOL1 1 2 3 4 5 6 7 8 9 52 V DDD 51 DO1C 50 DO1D 49 DO1W 48 LOCK 47 CL 46 DA 45 LD 44 MU 43 SA 42 TST1 41 TST2 40 V SSD 39 V DDD 38 RST 37 EM 36 CUS 35 CEN 34 BS 33 V SSD VDDD 32 MLB955 - 2 64 V SSD 58 V SSD DO2D 10 V DDD 11 V SSD 12 V SSD 13 V DDD 14 AOR1 15 DO2W 16 V SSD 17 CLD 18 V DDA4 19 V SSA4 20 XTLI 21 XTLO 22 CLI 23 VSSD 24 TDA1373H FSL 25 V SSD 26 CLO1 27 CLO2 28 V SSD 29 CLO3 30 Fig.2 Pin configuration. 1996 Jul 17 7 CLO4 31 53 V SSD 61 VSSD 59 DI2W 63 DI1O 54 FOW 60 DI2C 57 DI2D 62 DI1D 55 FOD 56 FOC Philips Semiconductors Product specification General Digital Input (GDIN) FUNCTIONAL DESCRIPTION Operating modes SAMPLE RATE CONVERSION (SRC) MODE The output sample rate is determined by a crystal and can be chosen up to 49 kHz. The range of input sample rates for a given output sample rate is given in Table 1. A pitch variation (`Varispeed') of 12% around the nominal input sample rate can be tracked. TDA1373H Data path (see Fig.4) The input signal at sample frequency fsi comes in via one of the DI1 inputs (IEC 958) or via the serial input DI2X. The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. The actual sample rate conversion takes place in the variable hold block. The down-sampling filters decimate the sample frequency to fso and after in-band noise shaping, the output signal is present at serial output DO1. Additionally the converted signal is available at the `analog' Bitstream outputs AOL, AOR and at the serial digital output DO2 (4fso). Table 1 Input sample rates OUTPUT SAMPLE RATE (kHz) 48 44.1 32 I2S INPUT (kHz) 0.3 to 1.7fso 13 to 83 12 to 76 9 to 55 IEC 958 INPUT (kHz) 0.35 to 1.45fso 16 to 68 15 to 62 12 to 45 MLB956 handbook, full pagewidth 60 THD N (dB) 80 100 120 140 160 10 10 2 10 3 10 4 f (Hz) 10 5 Measurement done with `Audio Precision'. SRC mode; 48 to 44.1 kHz; 20-bit output. Fig.3 Total harmonic distortion plus noise as a function of frequency. 1996 Jul 17 8 digital input f si digital output fso 2 Product specification TDA1373H Fig.4 Standard data path in the SRC mode. handbook, full pagewidth 1996 Jul 17 AES/EBU or I S TDA1373H IS BITSTREAM DAC e.g. TDA1547 analog output 2 Philips Semiconductors 768f so FSL BS CEN CUS EM LOCK XTLO XTLI CLI TST1 TST2 DO1C DNI 32 x AND 4 x DOWNSAMPLING IN-BAND NOISE SHAPER INS DSO DO1D DO1W DO2C DI1S DI2 FIFO & GAIN 4 x AND 16 x UP-SAMPLING VARIABLE HOLD General Digital Input (GDIN) DI1 FOS DI1O ADIC (IEC 958 DECODER) DI1D TDA1373H DO2D DO2 DO2W AOS HOLD AOL BITSTREAM DIGITAL FILTER AOR FOC FOD FOW MLC335 AIL 9 DIGITAL PLL CS AND UC EXTRACTION MU SA RST CLO1 CLO2 CLO3 CLO4 CLD AIR DI2C CLOCK SHOP DI2D MICROCONTROLLER INTERFACE DI2W GENERAL CONTROL CL LD DA Main path. Example of additional path. Philips Semiconductors Product specification General Digital Input (GDIN) SLAVE-VCO AND SLAVE-VCXO MODES In the SLAVE-VCO and SLAVE-VCXO modes, the GDIN can pass an exact copy of the incoming samples to the output, e.g. for storage on a digital medium such as CD-R. The output sample rate tracks any input sample rate within the frequency range of the external VC(X)O (fso = fsi). In the SLAVE-VCO mode a pitch variation of 12.5% around the nominal sample frequency can be tolerated. AD/DA MODE TDA1373H In this mode, the GDIN supports an economic realization of analog-to-digital and digital-to-analog conversion, in accordance with the Bitstream principle. This requires a Bitstream sigma-delta modulator and a Bitstream DAC, since the up-sampling and down-sampling filters of the sample rate convertor are reused. ADC and DAC can be simultaneously performed. Data path (see Fig.5) The signal at input sample frequency fsi comes in via one of the DI1 inputs (IEC 958). The ADIC signal passes through the FIFO/GAIN block and can be fed through the IN-BAND NOISE SHAPER to the serial output DO1. Additionally, the signal is present at DO2 (4fso) and at the Bitstream outputs AOL and AOR. Exact copies for digital use (e.g. write to a disk) from the input signal can be retrieved at output FO (this signal might be affected by jitter since it has not passed through the FIFO/GAIN block). By means of data path switch DSO, this direct output of the ADIC block can also be fed to output DO1. Note that in this event the DO1 serial format becomes equal to the FO format (see Table 3). Data path DA conversion (see Fig.6) The signal at sample frequency fso comes in via serial input DI2X or via one of the DI1 inputs (IEC 958). The signal passes through the FIFO/GAIN part and is interpolated in the up-sampling filters. A Bitstream digital filter converts this signal into a Bitstream signal at outputs AOL and AOR, after which it can be filtered by a Bitstream DAC like the TDA1547. Data path AD conversion (see Fig.6) The Bitstream signal from the sigma-delta modulator enters the GDIN at inputs AIL and AIR. The down-sampling filters decimate this signal to fso and after in-band noise shaping (selectable), the output signal is present at serial output DO1. 1996 Jul 17 10 digital output f si TDA1373H BITSTREAM DAC e.g.TDA1547 analog output IS 2 Product specification TDA1373H Fig.5 Standard data path in the SLAVE-VCO and SLAVE-VCXO modes. handbook, full pagewidth 1996 Jul 17 digital input f si AES/EBU or I2 S VCO digital output f si IS BITSTREAM DAC e.g.TDA1547 analog output 2 Philips Semiconductors digital input f si AES/EBU or I2 S TDA1373H 768fso General Digital Input (GDIN) FSL BS CEN CUS EM LOCK XTLO XTLI CLI TST1 TST2 DO1C FOS DNI VARIABLE HOLD 32 x AND 4 x DOWNSAMPLING INS DI1S DI2 FIFO & GAIN 4 x AND 16 x UP-SAMPLING DI1 DSO IN-BAND NOISE SHAPER DO1D DO1W DO2C 11 TDA1373H AOS HOLD DIGITAL PLL CS AND UC EXTRACTION MU SA RST CLO1 CLO2 DI1O ADIC (IEC 958 DECODER) DI1D DO2D DO2 DO2W AOL BITSTREAM DIGITAL FILTER AOR FOC FOD FOW MLC336 AIL AIR DI2C CLOCK SHOP DI2D MICROCONTROLLER INTERFACE DI2W GENERAL CONTROL CL LD DA CLO3 CLO4 CLD Main path. Example of additional path. Product specification TDA1373H Fig.6 Standard data paths in the AD/DA mode. handbook, full pagewidth 1996 Jul 17 digital output fso TDA1373H IS BITSTREAM DAC e.g. TDA1547 analog output 2 Philips Semiconductors analog input digital input fso AES/EBU or I S 768fso 2 BITSTREAM ADC e.g. SAA7360 FSL BS CEN CUS EM LOCK XTLO XTLI CLI TST1 TST2 General Digital Input (GDIN) DA IN DI1S DNI 32 x AND 4 x DOWNSAMPLING IN-BAND NOISE SHAPER INS DI2 FIFO & GAIN 4 x AND 16 x UP-SAMPLING VARIABLE HOLD DO1C DSO AD OUT DO1D DO1W DO2C FOS DI1 DI1O ADIC (IEC 958 DECODER) DI1D TDA1373H DO2D DO2 DO2W AOS HOLD AOL DA OUT AOR FOC FOD FOW MLC337 12 DIGITAL PLL CS AND UC EXTRACTION MU SA RST CLO1 CLO2 AIL AD IN AIR BITSTREAM DIGITAL FILTER DI2C CLOCK SHOP DI2D MICROCONTROLLER INTERFACE DI2W GENERAL CONTROL CL LD DA CLO3 CLO4 CLD Main path. Example of additional path. Philips Semiconductors Product specification General Digital Input (GDIN) Description of functional blocks IEC 958 AUDIO DIGITAL INPUT CIRCUIT The TDA1373H has three IEC 958 inputs: 1. DI1S. 2. DI1O. 3. DI1D. DI1S accepts IEC 958 line signals (minimum 200 mV peak-to-peak value and maximum 5 V peak-to-peak value), DI1O and DI1D accept only CMOS level signals. The input sample rate range that can be handled depends on the output sample frequency (fso) of the device. The maximum useful word length of the incoming samples is 20 bits. The internal ADIC retrieves the stereo audio samples, the V, U, C and P data bits, the ADIC word clock and the bit clock from the selected IEC 958 input signal. The digital Table 2 Error concealment in the IEC 958 decoder ERROR Validity (V-bit) error Parity (P-bit) error Number of data bits 32 Missing pre-amble(s) Extra pre-amble(s) More than 4 pre-ambles missing or extra mute output; restart Table 3 Serial input and output formats (see note 1) fWS fsi 4fso DO1 DO2 FO Note 1. S = slave; M = master. fso 4fso fsi fBCK 128fsi 192fso 48fso 128fso 192fso 64fso I2S S M M S M M JAPANES JAPANESE JAPANESE 3-STATE E 16-BIT 18-BIT 20-BIT S S M - M - S S M - M - S S - - - no no yes no yes DI2 ACTION DATA pass sample repeat last correct sample TDA1373H ADIC locks in less than 1 ms for a 44.1 kHz input signal. During this lock-in time the word clock is stopped and the audio bits are muted. The validity flag (VA), pre-emphasis flag and pin (EM), lock flag (LCK) and lock pin (LOCK) are available to check the status of the ADIC. This validity flag is an OR-ing of the incoming validity (V) bit and the own error detection of the ADIC. The actions which take place in case of detected errors are listed in Table 2. SERIAL DIGITAL INPUTS DI2W, DI2D AND DI2C The serial digital input DI2 can be used as standard input instead of the DI1 IEC 958 input or can be used together with the FO-output to switch a DSP IC in the input data path. A third possibility is to use DI2 as direct input to the GDIN Bitstream digital filter. In that case the DI2 input signal should be 4x oversampled externally. The serial formats supported are shown in Fig.7 and Table 3. ACTION WORD CLOCK no action stop ADIC word clock INPUT OUTPUT DI2 CONTROL BITS DI2, DI21 and DI22 DO1S, DO11 and DO12 DO2, DO21 and DO22 FO and FO1 1996 Jul 17 13 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H handbook, full pagewidth RIGHT WS (W) tr t HB RIGHT LEFT t LB tf t hWS t suWS LEFT BCK (C) t suDAT t hDAT TBCK DATA (D) LSB MSB DATA LSB MSB LSB MSB BCK WS LEFT RIGHT a. LEFT WS (W) tr t HB RIGHT t LB tf t hWS t suWS BCK (C) t suDAT t hDAT TBCK DATA (D) LSB MSB DATA MSB LSB MSB LSB BCK WS LEFT RIGHT MLB960 a. I2S input format. b. Japanese input format. b. Fig.7 Timing diagram for the serial input and output formats. 1996 Jul 17 14 Philips Semiconductors Product specification General Digital Input (GDIN) SERIAL DIGITAL OUTPUTS DO1W, DO1D AND DO1C Depending on the operating mode and data path switching, DO1 can contain the output of the in-band noise shaper or can be directly connected to the output of the internal ADIC. The supported serial formats and modes of this interface are given in Table 3. In case the GDIN goes out-of-lock the output data is muted and if the output is configured as master transmitter, the word clock slips half a word clock period. If this is undesirable, use the serial output as a slave transmitter. SERIAL DIGITAL OUTPUTS DO2W, DO2D AND DO2C The additional digital audio output DO2 operates at 4fso. DO2 can contain data of the up-sampling (not in SRC mode) or down-sampling filters. The formats supported are shown in Table 3. SERIAL FEATURE OUTPUTS FOW, FOD AND FOC The internal ADIC output is directly available in I2S format at this output. This makes it possible to switch a DSP TDA1373H featuring IC in the data path before SRC (at fsi). See Table 3 for the formats supported. BITSTREAM INPUTS AIL AND AIR The Bitstream input receives data at 128fso from a 1-bit sigma-delta modulator. Possible Bitstream inputs at 64fso are held twice. The timing diagram for the Bitstream inputs and outputs is given in Fig.8. BITSTREAM OUTPUTS AOL1 AND AOR1 The Bitstream output generates a 128 (SRC and SLAVE modes) or 192 (AD/DA mode) times oversampled Bitstream and can be connected to a Bitstream DAC (e.g. TDA1547) for high-quality DAC. It is also possible to get the inverted Bitstream signals on the complementary Bitstream outputs AOL1 (pin DO2D) and AOR1 (pin DO2W) by setting the DLO control bit. By using a simple low-pass filter, this symmetrical Bitstream output can be used to make an inexpensive analog monitor output. In that event the serial digital output DO2 cannot be used. handbook, full pagewidth FOC, CLO4 and DO2C CLOCK t d1 AIL and AIR DATA Tcy tf tr t CL CLD CLOCK t CH t d2 t d3 AOL1, AOL2, AOR1 and AOR2 DATA V DD 1 V 1.0 V MLB961 Fig.8 Timing diagram for the Bitstream inputs and outputs. 1996 Jul 17 15 Philips Semiconductors Product specification General Digital Input (GDIN) FIRST-IN FIRST-OUT (FIFO) The incoming samples are buffered in a FIFO. The depth of this FIFO determines the transients that can be allowed in the input frequency, as they may occur during pitch control. The FIFO has a depth of 8 samples, which makes GDIN support a tracking speed of up to 4 kHz/ms. FIFO overflow detection is provided to detect out-of-lock situations. GAIN CONTROL At the begin of the data path, the signal level can be controlled over a gain/attenuation range from 2 to 0 with a step size of 2E-7. This gain control can be used for volume control, gain correction and fade-in or fade-out. For normal operation, the gain level should be set to 1-2E-7 (-0.068 dB) to avoid pass band ripple clipping in the digital filters. Whenever a new gain value is set, the gain level is increased or decreased by one step per input sample until the new entered value is reached. Setting the MMU control bit forces the GDIN to start a soft muting. The gain is decreased, by one step per input sample, to zero. Clearing the MMU bit will increase the gain back to its original value. Only those outputs, for which the signal passes through the `gain control' part, are muted. 64x UP-SAMPLING FILTER A 64x (4x and 16x) oversampling filter is incorporated in the GDIN for the SRC process. This filter can also be used Table 4 SS 0 1 Filter characteristics 64x up-sampling filter PASS BAND 0 to 0.45351fsi 0 to 0.46875fsi 0.004 dB 0.004 dB STOP BAND 0.54648fsi to 1fsi 0.53125fsi to 1fsi VARIABLE HOLD TDA1373H as the up-sampling filter for a Bitstream digital-to-analog conversion in the AD/DA mode, in combination with the Bitstream digital filter and Bitstream DAC (e.g. TDA1547). Two filter characteristics can be chosen by the control bit SS (see Table 4). The 50 dB stop band suppression mode is especially suited for 32 kHz input sources like Digital Satellite Radio (DSR), where a very narrow transition band is required to obtain 0 to 15 kHz pass band. In SRC mode, the variable hold is the interface between the 64x up-sampling filters (64fsi) and the 128x down-sampling filters (128fso). In SLAVE and AD/DA modes, the variable hold holds each sample twice from 64fsi to 128fsi (fsi = fso). 128x DOWN-SAMPLING FILTER (see Fig.10) After SRC, a 128x (32x + 4x) down-sampling filter decimates the signal to fso. In the AD/DA mode, this filter is used as the ADC down-sampling filter for a Bitstream sigma-delta modulator. The stop band suppression is 80 dB from 0.54648fso (e.g. 24.1 kHz at fso = 44.1 kHz). -70 dB -50 dB 1996 Jul 17 16 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H 0 stop band suppression (dB) 20 MLB962 handbook, full pagewidth 40 60 80 100 0 20 40 60 80 f (kHz) 100 SS = 0; 70 dB stop band suppression. Fig.9 Filter characteristic 64x up-sampling filter. 0 stop band suppression (dB) 20 MLB963 handbook, full pagewidth 40 60 80 100 0 20 40 60 80 f (kHz) 100 Fig.10 Filter characteristic 128x down-sampling filter. 1996 Jul 17 17 Philips Semiconductors Product specification General Digital Input (GDIN) IN-BAND NOISE SHAPING (INS) The standard 20-bit output word length can be reduced to 16 or 18 bits to match digital consumer equipment. Normally 16 bit output re-quantization at audio-band sample rates drops the signal-to-noise ratio (S/N) inevitably to 95 dB, because of the re-quantization noise at -98 dB. It is possible however to shape the re-quantization noise in a psycho-acoustical way. This reduces the re-quantization noise at the frequencies where the human ear is most sensitive and stores the bulk of re-quantization noise at high frequencies, where the human ear is quite insensitive. The In-band Noise Shaping function (to 16 or 18 bits) results in a subjective quality improvement of about 2 bits below the actual quantization level. It is also possible to re-quantize the 20 bit output to 16 bits without noise shaping but by a simple rounding operation. Table 5 gives an overview of the 4 possible settings. Table 5 QU1 0 0 1 1 Note 1. INS = In-band Noise Shaping. BITSTREAM DIGITAL FILTER The Bitstream digital filter generates a Bitstream signal which should be filtered by a Bitstream DAC (e.g. TDA1547) to become a high-quality analog signal. The input for this block can be selected from the output of the up-sample path or directly from serial input DI2. In this case, the input signal applied to DI2 should be externally oversampled to 4fso and further oversampling will be carried out by the hold function. The Bitstream signal has a frequency of 128fso (SRC and SLAVE modes) or 192fso (AD/DA mode). To prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit NSD. DIGITAL PLL The digital PLL controls the variable hold function which steers the actual SRC process. An adaptive loop filter 1996 Jul 17 18 Selectable output word lengths QU0 0 1 0 1 20 bit 16 bit INS(1) 18 bit INS(1) WORD LENGTH 16 bit (rounded) TDA1373H allows fast locking to the input frequency and a small bandwidth during steady-state. At start-up, the bandwidth of the 3-step digital loop filter is gradually reduced to 0.5 Hz. A difference frequency of 1 Hz is reached within 512 input samples (10 ms at 44.1 kHz), which allows to start the SRC. At this moment the outputs are de-muted, indicated at pin MU and status flag MUT. The FIFO position is continuously monitored to control the adaptive loop filter. The loop filter switches back to a fast state when the FIFO tends to drift, e.g. during pitch control on the input signal. It is possible to fix the loop filter in one of the three states. In the adaptive mode, the actual state can be monitored by the microcontroller (ST1 and ST0). In SRC mode, the microcontroller can retrieve the exact input sample frequency via the status registers STS3 and STS4. Table 6 LC1 0 0 1 1 PLL operation modes LC0 0 1 0 1 PLL OPERATION adaptive state 1 fixed state 2 fixed state 3 fixed PLL BANDWIDTH (Hz) 500, 50 or 0.5 500 50 0.5 In both SLAVE modes, a pulse modulated signal at pin FSL is present to control the external VC(X)O. In SLAVE-VCO mode, CLI is the clock input of the GDIN and in SLAVE-VCXO mode XTLI is the clock input. An external 1000 Hz low-pass filter retrieves the control voltage for the VC(X)O. To get the loop characteristics as described above, the centre frequency of the VCO should be at 1 V 2 DD and the sensitivity should be: 768f so ( c ) g v = ------------------------ Hz/V. 1 -- V DD 2 The maximum VCO frequency range is: (768 x 0.3)fso(c) < 768fsi (=fso) < (768 x 1.7)fso(c) (49 kHz). IEC 958 CHANNEL STATUS AND USER CHANNEL EXTRACTOR (CUP) The internal ADIC retrieves also the Channel Status (CS) and User Channel (UC) bits from the IEC 958 signal. The C/U processing function block can be programmed for 4 different functions (see Table 7). Philips Semiconductors Product specification General Digital Input (GDIN) Table 7 SM1 0 0 1 0 Note 1. X = don't care. The extracted or decoded information can be read in three ways: * From the internal RAM buffer by a microcontroller (see Section "The RAM buffer") * At the output pins CUS, BS and CEN (see Fig.11) * In status registers STS5 and STS6 (permanent 16 `consumer mode' C-bits, see Table 9). During CD subcode Q extraction, a 16-bit CRC is done over the Q-channel (CRC flag). This flag is only meaningful when the ADIC is locked (LCK flag). THE RAM BUFFER A double RAM buffer is present in the device. While reading one buffer, the other buffer is filled with the new incoming data. The RAM buffer can be read in two ways: 1. Interrupt protocol (UIP = 0). 2. User request protocol (UIP = 1). Overview of selectable CUP functions SM0 1 1 0 0 LR(1) 0 1 X X CUP FUNCTION extract full C-block left (192 bits/block) extract full C-block right (192 bits/block) extract full U-block (384 bits/block) decode CD-Subcode Q-information (80 bits/CD frame) from U-bits TDA1373H RAM BUFFER 80H to 97H 80H to 97H 80H to AFH 80H to 89H Interrupt protocol (UIP = 0) A C-block, a U-block or CD Subcode frame is read in the time between two Block Sync (output pin BS) pulses, which can be used as the interrupt for a microcontroller. At a sample rate of 44.1 kHz, the microcontroller must be 192 able to read a C-block or U-block within --------------- = 4.35 ms. 44100 CD Subcode frames are received at a data rate of 75 Hz or 13.3 ms/frame. User request protocol (UIP = 1) The microcontroller requests for a C, U and CD-Q block or frame, which will then become available at the next block preamble, indicated by BS. The information is not updated until the next user request, which means the microcontroller can take any time to read the information. The CD Subcode CRC check flag always shows the CRC over the last received CD Subcode Q frame and is not stored with the present Q frame in the buffer. Figure 12 shows the user request read procedure. 1996 Jul 17 19 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H handbook, full pagewidth TcyBS BS t suBC t hBC CEN t suCC t hCC LEFT CS0 or UC0 t LCEN RIGHT CS0 or UC1 LEFT CS191 or UC382 t cyCEN RIGHT CS191 or UC 383 CUS a. BS t HBS(CD) t suBC(CD) TcyBS(CD) CEN t suCC(CD) t hCC(CD) t HCEN(CD) CUS Q1 R1 S1 t cyCEN Q98 Q1 R1 S1 MLB964 b. a. Channel Status (CS) or User Channel (UC) extraction. b. CD subcode demodulation. Fig.11 Timing of the CUS, CEN and BS output pins. 1996 Jul 17 20 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H handbook, full pagewidth Block Sync or CD subcode frame sync (BS) Buffer Contents Valid (BCV) OK, buffer valid Set Buffer Free (SBF) request to read (hold buffer) microcontroller data communication (LD, CL, DA) MLB965 set buffer free again start to read buffer buffer completely read Fig.12 C, U and CD-Q user request procedure. THE MICROCONTROLLER INTERFACE/ STAND-ALONE CONTROL BLOCK If pin SA is LOW, a microcontroller controls and monitors the operation of the GDIN and reads C, U and CD-Q information. A 3-line bidirectional serial interface with data (DA), load (LD) and clock (CL) line is present. For both a write and read operation the microcontroller generates the clock and load signals. A single byte is written by setting the LD signal active HIGH during transmission of the serial data. At the rising edge of the serial clock, the GDIN clocks in the serial data. At the end of the 8-bit data word a `load pulse' should be given to enable the internal serial-to-parallel conversion. Write operations are always two-byte operations. First, the register address is sent to the GDIN, then the corresponding data is send (see Fig.13): 1. Write Address. 2. Write Data byte. A single byte read-operation is initialized by pulling LD LOW. When the serial clock is started, the GDIN will transmit serial data on the DA line. The information is read by the microcontroller at the rising edges of the clock CL. Read operations are at least two-byte operations with multi-byte reads possible. The address is sent to the GDIN and then one or more bytes are read from the GDIN with each additional byte coming from an incrementally higher address: 1. Write Address. 2. Read Data byte. 3. Read Data byte. 4. Read Data byte. 5. Etc. Multi-read operations continue to cycle through the given Register Address Range until the read operation is completed. If pin SA is HIGH, the GDIN can operate without an external microcontroller. In this event, only the SRC mode and the AD/DA mode can be selected. A number of pins are reconfigured to control some of the internal switches of the device. For more information see Chapter "Pinning" and Section "Controlling the GDIN". 1996 Jul 17 21 Philips Semiconductors Product specification General Digital Input (GDIN) Table 8 TDA1373H memory map REGISTER NAME CMD1 to CMD6 STS1 to STS6 RAM buffer; C-block RAM buffer; U-block RAM buffer; CD-Q frame status; read read read read TDA1373H REGISTER ADDRESS RANGE 00H to 05H 40H to 45H 80H to 97H 80H to AFH 80H to 89H TYPE command; read/write handbook, full pagewidth Tcy t HCL CL t LCL t hLC LD t hDC t LD1 t suLC t suDC DA 7 0 7 0 a. CL t HLD LD t hDC t suDC 0 MLB966 t suLC DA 7 0 7 b. a. A complete write operation. b. A complete read operation. Fig.13 Timing for the microcontroller read and write operations. 1996 Jul 17 22 Philips Semiconductors Product specification General Digital Input (GDIN) Controlling the GDIN MICROCONTROLLER OPERATED TDA1373H Status registers Table 9 Status registers BIT 7 6 5 4 3 2 1 0 STS2 (41H) GDIN status information 7 6 5 4 3 2 and 1 0 STS3 (42H) STS4 (43H) STS5 AES/EBU channel status (44H)(6) 7 to 0 7 to 0 7 and 6 5 and 4 3 2 1 0 STS6 AES/EBU channel status (45H)(6) 7 6 5 4 3 2 1 0 Notes 1. Only valid when the internal ADIC is in lock (bit 3 of register STS1; LCK = 1). FLAG - - - - LCK CRC VA BCV - - - - - ST1 and ST0 MUT LF15 to LF8 LF7 to LF0 CA1 and CA0 FS1 and FS0 EM CPY AN CPF CAT7 CAT6 CAT5 CAT4 CAT3 CAT2 CAT1 CAT0(7) DESCRIPTION reserved reserved reserved reserved internal ADIC lock status CD-Q channel; CRC validity bit(2) RAM buffer contents reserved reserved reserved reserved reserved PLL operating mute status(4) LF15 to LF0: input sample rate(5) clock accuracy input sample rate pre-emphasis copyright protection audio or data status(3) check(1) - - - - 0 = not locked; 1 = locked 0 = OK; 1 = error 0 = valid; 1 = not valid 0 = valid; 1 = not valid - - - - - 00 = reserved; 01 = state 1; 10 = state 2; 11 = state 3 0 = mute OFF; 1 = mute ON fsi = fso x (1 - (0.75 x LF15 to LF0)) 00 = level 2; 01 = level 1; 10 = level 3; 11 = reserved 00 = 44.1 kHz; 01 = reserved; 10 = 48 kHz; 11 = 32 kHz 0 = OFF; 1 = ON 0 = YES; 1 = NO 0 = audio; 1 = data EXPLANATION REGISTER STS1 (40H) GDIN status information consumer or professional use 0 = consumer; 1 = professional CAT7 to CAT0: category code some examples: 00000000 = general 10000000 = CD 1100001L = DCC 1100000L = DAT 0100100L = mixer 0101100L = SRC 1001000L = MD 1996 Jul 17 23 Philips Semiconductors Product specification General Digital Input (GDIN) 2. VA = IEC 958 V-bit or ADIC error detector. 3. Only valid when the digital PLL works in adaptive mode. 4. After approximately 512 stereo input samples (approximately 10 ms when fsi = 44.1 kHz). 5. Only valid in SRC mode. LF15 to LF0 are in two's complement notation. TDA1373H 6. Only valid when IEC 958 input format is consumer (bit 0 of register STS5; CPF = 0). When the input format is professional (CPF = 1) the STS5 and STS6 registers contain the first 16 bits of C-block. 7. Generation status (L-bit). Command registers Table 10 Command registers REGISTER CMD1 (00H) ADIC control BIT 7 and 6 5 4 3 and 2 1 0 CMD2 (01H) loop and mode control 7 6 5 and 4 FLAG DI12 and DI11 UIP SBF SM1 and SM0 LRS DBA - - LC1 and LC0 DESCRIPTION ADIC input selector user interface protocol set internal RAM buffer free channel decoding C-block left/right selector RAM buffer mode reserved reserved PLL control; note 1 EXPLANATION 00 = DI1S; 01 = DI1O; 10 = DI1D; 11 = reserved 0 = interrupt; 1 = user requirement 0 = hold buffer; 1 = set buffer free 00 = CD-Q; 01 = C-block; 10 = U-block; 11 = reserved 0 = left; 1 = right 0 = normal; 1 = test - - 00 = adaptive; 01 = state 1 fixed; 10 = state 2 fixed; 11 = state 3 fixed 00 = SRC mode; 01 = AD/DA mode; 10 = SLAVE-VCXO mode; 11 = SLAVE-VCO mode 0 = 3-state; 1 = enabled 0 = no reset; 1 = reset 0 = INS; 1 = ADIC - 0 = ADIC; 1 = 128x filter 0 = FOW, FOD and FOC; 1 = DI2W, DI2D and DI2C 0 = variable hold; 1 = AIL/AIR 0 = output 128x down; 1 = output FIFO/GAIN 0 = variable hold; 1 = DI2W, DI2D and DI2C 0 = 128x down; 1 = 64x up 3 and 2 MS1 and MS0 mode selector; notes 1 and 2 1 0 CMD3 (02H) data path(5) 7 6 5 4 3 2 1 0 RTR MRS DSO - FOS DI2 DNI INS AOS DO2 enable 3-state outputs; note 3 reset (hardware reset); note 4 DO1 output selector reserved FO output selector FIFO input selector input selector 128x filter In-band Noise Shaper input selector Bitstream digital filter input selector DO2 output selector 1996 Jul 17 24 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H REGISTER CMD4 (03H) control BIT 7 6 5 4 and 3 2 1 0 FLAG - - MMU QU1 and QU0 NSD DLO SSP DI22 and DI21 DESCRIPTION reserved reserved soft mute function; note 7 in-band noise shaper dither Bitstream digital filter; note 8 symmetrical Bitstream output - - EXPLANATION 0 = OFF; 1 = ON 00 = 16-bit; 01 = 20-bit; 10 = 16-bit INS; 11 = 18-bit INS 0 = OFF; 1 = ON 0 = OFF; 1 = ON stop band suppression 64x filter; 0 = 70 dB; 1 = 50 dB note 9 serial format DI2 input 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = Japanese 20-bit 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = reserved 00 = I2S; 01 = Japanese 16-bit; 10 = Japanese 18-bit; 11 = 3-stated 0 = master; 1 = slave 0 = I2S; 1 = 3-stated some examples: 11111111 = x2 (maximum) 10000000 = x1 01111111 = x0.992 00000001 = x0.0078 CMD5 (04H) input/output formats 7 and 6 5 and 4 DO22 and DO21 DO12 and DO11 DO1M FOT GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 serial format DO2 output 3 and 2 serial format DO1 output 1 0 CMD6 (05H) 7 6 5 4 3 2 1 0 Notes DO1 master/slave selector FO output 3-state selector GAIN7 to GAIN0: gain of the GCM block(10); maximum = 2; step = 1128 1. In the SLAVE-VCXO mode, the PLL should be fixed in state 2 until locked. 2. A mode change will always invoke a restart of the GDIN. 3. At power-on the DO1 and FO outputs are `3-state' to avoid I2S bus conflicts. This bit overrides the serial I/O control bits. 4. A MRS or hardware reset clears all command registers, also the MRS flag itself. 5. See Section "Data path switching" for possible settings of the data path switches in the different modes. 6. Set all reserved flags to 0. 7. Setting MMU starts a soft-mute from current gain value to 0 by 1128 per input sample. Clearing MMU starts the inverse process from 0 to current gain value. 8. To prevent idle patterns in the audio band, it is strongly advised to add out-of-band dither by setting control bit NSD. 9. Set this bit for 32 kHz input sources. 10. Use `01111111' for normal operation to avoid pass band ripple clipping. 1996 Jul 17 25 Philips Semiconductors Product specification General Digital Input (GDIN) Data path switching TDA1373H All data path switches are freely controllable, although not all combinations make sense in the different operating modes. Table 11 shows the preferred settings of the CMD3 control register. Table 11 Preferred settings of the CMD3 control register REGISTER CMD3 (02H) data path BIT 7 6 5 4 3 2 1 0 Notes 1. Level 0 or 1 indicates to set the flag in this position. A = application dependent. 2. When the output of the internal ADIC is fed directly to DO1 or FO, the serial output format is I2S, the word select jitters (by one 384fso clock cycle) and the number of bit clocks per word select is not fixed. STAND-ALONE CONTROL When pin SA is HIGH, the GDIN operates under stand-alone control. Some basic settings can be controlled in this event by changing the level at the control pins. Table 12 shows which command bits are pin-controllable during stand-alone operation. The command bits which are not pin-controllable are automatically set to their appropriate value in accordance with the selected mode (SRC or AD/DA). All control bits not shown get the value 0 in the event of stand-alone control. Table 12 Command registers REGISTER CMD1 (00H) ADIC control CMD2 (01H) loop and mode control FLAG DI11 MS0 RTR CMD3 (02H) data path DI2 DNI CMD4 (03H) control CMD6 (05H) Notes 1. When the device operates in stand-alone control, only the SRC mode and AD/DA mode are available. 2. This means that all 3-state outputs are permanently enabled during stand-alone operation. QU0/QU1 NSD GAIN PIN FSL DI1D - DA - CL LD - DESCRIPTION ADIC input selector mode selector; note 1 enable 3-state outputs; note 2 FIFO input selector input selector 128x filter in-band noise shaper dither Bitstream digital gain of the FIFO/GAIN block EXPLANATION 0 = DI1S; 1 = DI1O 0 = SRC mode; 1 = AD/DA mode RTR is always 1 in stand-alone mode 0 = FOW, FOD and FOC; 1 = DI2W, DI2D and DI2C SRC mode = 0: variable hold; AD/DA mode = 1: AIL/AIR 0 = 20 bit; 1 = 16 bit INS 0 = OFF; 1 = ON gain = 01111111 = x0.992 FLAG DSO - FOS DI2 DNI - AOS DO2 DATA PATH SWITCH DO1 output selector; note 2 reserved FO output selector; note 2 FIFO input selector input selector 128x filter reserved AOL and AOR output selector DO2 output selector SRC(1) 0 - A A 0 - A 0 SLAVE(1) A - A A 1 - A A AD/DA(1) A - A A 1 - A A 1996 Jul 17 26 Philips Semiconductors Product specification General Digital Input (GDIN) LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD IDD Vi Ii(max) Io(max) Ptot Tstg Tamb Ves PARAMETER supply voltage supply current input voltage maximum input current maximum output current total power dissipation storage temperature operating ambient temperature electrostatic handling HBM; note 1 MM; note 2 Notes 1. Human Body Model (HBM): C = 100 pF; R = 1.5 k; 3 zaps positive and 3 zaps negative. 2. Machine Model (MM): C = 200 pF; L = 2.5 H; R = 25 ; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 46 CONDITIONS - -0.5 - - - -65 0 -3000 -300 MIN. -0.5 - - - - - 1030 - - - - TYP. TDA1373H MAX. +6.5 200 VDD + 0.5 10 10 - +150 +70 +3000 +300 V UNIT mA V mA mA mW C C V V UNIT K/W 1996 Jul 17 27 Philips Semiconductors Product specification General Digital Input (GDIN) CHARACTERISTICS VDD = 5 V 10%; Tamb = 0 to +70 C; CL = 50 pF; unless otherwise specified. SYMBOL Supply VDD IDDD IDDA1 IDDA4 Ptot Iq(tot) supply voltage digital supply current analog supply current IEC 958 data slicer analog supply current clock oscillator total power dissipation total quiescent supply current fso = 44.1 kHz Tamb = 25 C; note 2 -0.5 - - - - - - 148 0.65 4 775 - PARAMETER CONDITIONS MIN. TYP. TDA1373H MAX. UNIT 6.5 180 1 6 - 10 V mA mA mA mW A DC characteristics INPUT PINS TYPE HPP01 (AIL, AIR, CLI, TST2, TST1, SA, LD, CL, DI2D, DI1D AND DI1O) VIL VIH IIL VIL VIH Vhys IIL VIL VIH Ii LOW level input voltage HIGH level input voltage input leakage current - 0.7VDD - - 0.8VDD - - - 0.7VDD - - - - - - 0.33VDD - - - - 0.3VDD - 1.0 V V A V V V A V V mA INPUT PIN TYPE HPP07 (SCHMITT-TRIGGER; RST) LOW level input voltage HIGH level input voltage hysteresis voltage input leakage current 0.2VDD - - 1.0 INPUT PIN DI1S (IEC 958 INPUT) LOW level input voltage HIGH level input voltage input current 0.3VDD - 1.9 OUTPUT PINS TYPE OPF40 (DO2C, AOL1, DO2D, AOR1, DO2W, CLO1, CLO2, CLO3, CLO4, BS, CEN, CUS, MU AND LOCK; 4 mA OUTPUTS) VOL VOH VOL VOH VOL VOH IOZ LOW level output voltage HIGH level output voltage - VDD - 0.5 - VDD - 0.5 - VDD - 0.5 - - - - - - - - 0.5 - 0.5 - 0.5 - 5.0 V V OUTPUT PIN TYPE OPF20 (EM; 2 mA OUTPUT) LOW level output voltage HIGH level output voltage V V OUTPUT PINS TYPE OPF43 (CLD, DO1D, FOW, FOD AND FOC; 4 mA 3-STATE OUTPUTS) LOW level output voltage HIGH level output voltage 3-state leakage current V V A 1996 Jul 17 28 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SYMBOL PARAMETER CONDITIONS - MIN. - - - - - - - - - - TYP. MAX. UNIT INPUT/OUTPUT PINS TYPE HOF21 (FSL, DI2W AND DI2C; 2 mA OUTPUTS) VIL VIH IOZ VOL VOH VIL VIH IOZ VOL VOH LOW level input voltage HIGH level input voltage 3-state leakage current LOW level output voltage HIGH level output voltage 0.3VDD - 5.0 0.5 - 0.3VDD - 5.0 0.5 - V V A V V 0.7VDD - - VDD - 0.5 - 0.7VDD - - VDD - 0.5 INPUT/OUTPUT PINS TYPE HOF41 (DA, DO1W AND DO1C; 4 mA OUTPUTS) LOW level input voltage HIGH level input voltage 3-state leakage current LOW level output voltage HIGH level output voltage V V A V V Characteristics per block and pin; note 1 INPUT PINS TYPE HPP01 AND HPP07 Ci tr tf tr tf gm ZO IIL CI CO VIL VIH Vi(p-p) Ci input capacitance rise time (unless otherwise specified) fall time (unless otherwise specified) - - - - - 0.007821 405 - - - - 0.7VDD 0.2 - 10 - - 5 5 - - - 3.1 - - - - 25 - Tcy Tcy 10 10 pF ns ns OUTPUT PINS TYPE OPF40 AND OPF43 rise time (unless otherwise specified) fall time (unless otherwise specified) ns ns CRYSTAL OSCILLATOR mutual conductance output impedance input leakage current input capacitance output capacitance LOW level input voltage HIGH level input voltage 0.03913 3200 1.0 - 18 0.3VDD - VDD - mA/V A pF pF V V IEC 958 INTERFACE (FOR TIMING SEE SECTION 13 OF REFERENCE 1 IN CHAPTER "References") AC input voltage (peak-to-peak value) input capacitance V pF 1996 Jul 17 29 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SYMBOL PARAMETER CONDITIONS - - Tcy 0 Tcy 0 see Table 3 - Tcy Tcy - - MIN. - - - - - - TYP. MAX. UNIT SERIAL INPUT INTERFACES (see Fig.7) tr tf tsuDAT thDAT tsuWS thWS TBCK tHB tLB tr tf tsuDAT thDAT tsuWS thWS TBCK tHB tLB td1 rise time (unless otherwise specified) fall time (unless otherwise specified) set-up time data (D) to clock (C) hold time data (D) to clock (C) set-up time word select (W) to clock (C) hold time word select (W) to clock (C) clock period time bit clock HIGH time bit clock LOW time 25 25 - - - - - - - 10 10 - - - - - - - 100 ns ns ns ns ns ns ns ns ns 1/fBCK - - - - - - - - 1/fBCK - - - SERIAL OUTPUT INTERFACES rise time (unless otherwise specified) fall time (unless otherwise specified) set-up time data (D) to clock (C) hold time data (D) to clock (C) set-up time word select (W) to clock (C) hold time word select (W) to clock (C) clock period time bit clock HIGH time bit clock LOW time see Table 3 ns ns ns ns ns ns ns ns ns 0.5tBCK Tcy 0.5tBCK Tcy - 0.4tBCK 0.4tBCK - BITSTREAM INPUTS AIL AND AIR (see Fig.8) delay time after HIGH-to-LOW clock transition ns BITSTREAM OUTPUTS AOL1, AOR1 AND CLD (see Fig.8) tr tf tsu th tr tf tCH tCL data output rise time data output fall time data output set-up time data output hold time clock output rise time clock output fall time clock output HIGH time clock output LOW time - - 0 25 - - 40 40 10 10 - - 5 5 - - 15 15 - - 10 10 - - ns ns ns ns ns ns ns ns 1996 Jul 17 30 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - TYP. - - - - - - - - - - - - - MAX. UNIT MICROCONTROLLER INTERFACE (see Fig.13) TcyCL tHCL tLCL tsuLC thLC tLD1 TcyLD thLC tLD2 tsuDC thDC tsuDC thDC CL cycle time CL HIGH time CL LOW time set-up time LD to CL hold time LD to CL write pulse period LD LD cycle time hold time LD to CL read enable LD pulse period set-up time DA to CL hold time DA to CL set-up time DA to CL hold time DA to CL write operation write operation read operation read operation read operation read operation write operation write operation 6Tcy 3Tcy 3Tcy 9Tcy 3Tcy 3Tcy 3Tcy 3Tcy 6Tcy Tcy 3Tcy Tcy 3Tcy ns ns ns ns ns ns ns ns ns ns ns ns ns OUTPUT PINS CUS, CEN AND BS (see Fig.11) Channel status or channel mode TcyBS tCEN tLCEN tsuBC thBC tsuCC thCC TcyBS(CD) tHBS(CD) tCEN tHCEN(CD) tsuBSCEN tsuCC(CD) thCC(CD) BS cycle time - - 1.5 1.5 8 1.5 8 - - - - 8 1.5 8 1 192 x ---f si 1 2fsi - - - - - - - - - - - - - - ms s s s s s s ms s s ms s s s CEN enable time CEN LOW time set-up time BS to CEN hold time BS to CEN set-up time CUS to CEN hold time CUS to CEN - - - - - 13.3 408 136 1 2fsi CD-Q subcode demodulation mode frame sync BS cycle time frame sync BS HIGH time CEN enable time CEN enable HIGH time set-up time BS to CEN set-up time CUS to CEN hold time CUS to CEN - - - 1996 Jul 17 31 Philips Semiconductors Product specification General Digital Input (GDIN) TDA1373H SYMBOL RESET tPWRES tiRES Notes PARAMETER CONDITIONS MIN. - - TYP. - MAX. UNIT reset pulse width internal reset time after reset pulse 10Tcy - ns ns 40Tcy 1. Most timing specifications are referenced to the system clock Tcy = 1384fso. 2. The (IDD) quiescent current is checked on as much active gate area as possible, therefore outputs are chosen reference. Each output is IDD tested in HIGH and LOW state. The minimum number of test vectors on which IDD quiescent current is tested is 2 and the maximum is N + 1 (N = number of outputs). These test vectors also define fixed conditions in the core. IDD quiescent current test is not allowed on test vectors which may result in additional quiescent current caused by pull-up/down resistors, I/Os, internal bus-structures, etc. In total this IDD quiescent current test contributes highly to the (functional) fault coverage. QUALITY SPECIFICATION * General quality in accordance with "SNW-FQ-611 part E" and can be found in the "Quality Reference Handbook" (order number 9398 510 63011). REFERENCES 1. "Digital audio interface", first edition 1989-03 International standard "IEC 958". 2. "I2S bus specification", release 2-86, Philips Export B.V. (order number 9398 332 10011). 1996 Jul 17 32 Product specification TDA1373H Fig.14 Test diagram for the TDA1373H. handbook, full pagewidth 1996 Jul 17 JP1 Y1 100 k 1 nF C16 22 pF 2.2 H 768f s C17 22 pF L5 C1 4 3 2 1 R2 C2 100 nF 38 RST VCC JP2 ground VDDA4 VSSA4 VSSD VSSD FSL DO2D DO2W DO2C DO1D 50 49 51 9 AOL1 AOR1 CLO VDDD VDDD VDDD VDDD 15 18 7 32 39 52 C10 26 29 58 61 64 100 nF C11 100 nF C9 100 nF C8 100 nF 6 16 R8 10 k 10 R7 10 k 25 17 24 20 19 BS CUS CEN LOCK CL LD DA XTLI XTLO CLI CLO1 CLO2 CLO3 CLO4 R9 4.7 34 36 35 48 47 45 46 21 22 23 27 28 30 31 C5 100 nF TEST DIAGRAM VCC Philips Semiconductors R3 10 k C7 10 F 44 MU 37 EM 43 SA 63 DI1O General Digital Input (GDIN) 62 J1 RCA C3 100 nF DI1D 1 DI1S C4 100 pF R1 75 VCC R4 3 4.7 VDDA1 2 33 DO1W DO1C FOD FOW FOC DI2D DI2W DI2C VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD VSSD 55 54 56 57 59 60 8 33 40 53 6V VCC R5 C21 47 F C18 100 nF VSSA1 TDA1373H C6 47 F DO1D 6 V DO1W DO1C DI2D DI2W DI2C AIL AIR AOL1 DO2D AOL2 AOR1 DO2W AOR2 CLD XTIN SDA 11 VDDD 4.7 R6 14 VCC VDDD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 IN 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 supply voltage 4.7 C19 100 nF 12 VSSD 6V C23 47 F 13 VSSD 4 AIL C14 47 F 6V C15 47 F 6V L1 L2 L3 C12 47 F 6V C13 47 F 6V L4 VCC VCC 5 AIR 6V C22 47 F C20 100 nF 42 TST1 41 TST2 V CC V CC MLB967 - 1 Philips Semiconductors Product specification General Digital Input (GDIN) PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height TDA1373H SOT319-1 c y X 51 52 33 32 ZE A e E HE A A2 A1 Q (A 3) Lp L detail X wM pin 1 index bp 64 1 wM D HD ZD B vM B 19 vM A 20 e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.50 0.35 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.43 1.23 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1996 Jul 17 34 Philips Semiconductors Product specification General Digital Input (GDIN) SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. TDA1373H If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1996 Jul 17 35 Philips Semiconductors Product specification General Digital Input (GDIN) DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA1373H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jul 17 36 Philips Semiconductors Product specification General Digital Input (GDIN) NOTES TDA1373H 1996 Jul 17 37 Philips Semiconductors Product specification General Digital Input (GDIN) NOTES TDA1373H 1996 Jul 17 38 Philips Semiconductors Product specification General Digital Input (GDIN) NOTES TDA1373H 1996 Jul 17 39 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996 Internet: http://www.semiconductors.philips.com/ps/ (1) TDA1373H_3 June 26, 1996 11:51 am SCA50 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 517021/50/03/pp40 Date of release: 1996 Jul 17 Document order number: 9397 750 00927 |
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