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THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
NJ88C25 NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
DS3280-1.3
NJ88C25
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
The NJ88C25 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable `M' counter, 7-bit programmable `A' counter, latched and buffered Band 0 and Band 1 outputs and the necessary control and latch circuitry for accepting and latching the input data. Data is presented serially under external control from a suitable microprocessor. Although 30 bits of data are initially required to program all counters, subsequent updating can be abbreviated to 19 bits, when only the `A', `M' and `B' counters require changing. The NJ88C25 is intended to be used in conjunction with a twomodulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser.
PDA PDB FV LD FIN VSS VDD BAND 0 OSC IN 1 2 3 4 18 17 16 15 CH RB MC CAP ENABLE CLOCK DATA BAND 1 OSC OUT
5 NJ88C25 14 6 7 8 9 13 12 11 10
FEATURES s Low Power Consumption
DG18, DP18, MP18
Fig.1 Pin connections - top view
s High Performance Sample and Hold Phase Detector s Serial Input with Fast Update Feature
ORDERING INFORMATION
NJ88C25 KA DG Ceramic DIL Package NJ88C25 KA DP Plastic DIL Package NJ88C25 KA MP Miniature Plastic DIL Package
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS: 20*5V to 7V Input voltage Open drain output, pins 3 and 4: 7V All other pins: VSS20*3V to VDD10*3V Storage temperature: 265C to 1150C (DG package) 255C to 1125C (DP and MP packages)
RB 17 CAP 15 CH 18
OSC IN OSC OUT
9 10
REFERENCE COUNTER (11BITS)
42
fr
SAMPLE/HOLD PHASE DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8 12 DATA 14 ENABLE 13 `B' REGISTER FREQUENCY/ PHASE DETECTOR 2
`R' REGISTER
fV
PDB
CLOCK
`M' REGISTER
`A' REGISTER
4 VSS 3
LOCK DETECT (LD)
LATCH 6 BAND 0 BAND 1 FIN 8 11 5
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
FV
`M' COUNTER (10 BITS)
`A' COUNTER (7 BITS)
VSS
CONTROL LOGIC VDD VSS 7 6
16
MODULUS CONTROL OUTPUT (MC)
Fig.2 Block diagram
NJ88C25
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated: VDD-VSS=2*7V to 5*5V. Temperature range = -30C to +70C DC Characteristics Value Characteristic Min. Supply current Typ. 5*5 0*7 3*7 Max. mA mA mA fosc, fFIN = 20MHz fosc, fFIN = 1MHz fosc, fFIN = 10MHz Units Conditions
OUTPUTS Modulus Control (MC), BAND 1 and BAND 2 High level Low level Lock Detect (LD) and FV Low level Open drain pull-up voltage PDB High level Low level 3-state leakage current AC Characteristics
VDD20*4 0*4 0*4 7*0 4*6 0*4 0*1
V V V V V V A
ISOURCE = 1mA ISINK = 1mA ISINK = 4mA
ISOURCE = 4mA ISINK = 4mA
Value Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES (see note 5) Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times Positive threshold Negative threshold Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programming capacitor, CAP Output resistance, PDA 200 20 30 0*5 0*5 0*2 0*2 0*2 0*2 0*2 3 50 Typ. Max. mV RMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, ns See note 2 Units Conditions
tCH
2 500 5 1 1 5
ns k nF nF k
NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5s. 4. The inputs to the device should be at logic `0' when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and FIN inputs. 5. Clock to enable set-up time (tES) is variable, dependent on fOSC. It needs to be specified in terms of fOSC, clock high time (tCH) and clock low time (tCL) and must meet the following conditions: 431/fOSC2

s s s s s s s V V
All timing periods are referenced to the negative transition of the clock waveform. See note 5 TTL compatible, see note 1
See note 3

0 to 5V square wave
NJ88C25
PIN DESCRIPTIONS
Pin no. 1 Name PDA Description Analog output from the sample and hold phase comparator for use as a `fine' error signal. Voltage increases as fv (the output from the `M' counter) phase lead increases; voltage decreases as fr (the output from the reference counter) phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the system is in lock. Three-state output from the phase/frequency detector for use as a `coarse' error signal. fv. fr or fv leading: positive pulses with respect to the bias point VBIAS fv , fr or fr leading: negative pulses with respect to the bias point VBIAS fv = fr and phase error within PDA window: high impedance. This pin is an open drain output from the `M' counter. An open-drain lock detect output at low level when phase error is within PDA window (in lock); high impedance at all other times. The input to the main counters. It is normally driven from a prescaler, which may be AC-coupled or, when a full logic swing is available, may be DC-coupled. Negative supply (ground). Positive supply (normally 5V)
2
PDB
3 4 5 6 7 9,10
FV LD FIN VSS VDD
OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. The addition of a 220 resistor between OSC OUT and the crystal will improve stability. An external reference signal may, alternatively, be applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled. The program range of the reference counter is 3 to 2047 , with the total division ratio being twice the programmed number. BAND 0/1 DATA Two latch outputs, providing an output of the data from the `B' register. Information on this input is transferred to the internal data latches during the appropriate data read time slot. DATA is high for a `1' and low for a `0'. There are four data words which control the NJ88C25; MSB is first in the order: `A' (7 bits), `M' (10 bits), ]B' (2 bits) and `R' (11 bits). Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock transitions have been received when the ENABLE line goes low (i.e., only `B',`M' and `A' will have been clocked in), then the `R' counter latch will remain unchanged and only `M' and `A' will be transferred from the input shift register to the counter latches. This will protect the `R' counter from being corrupted by any glitches on the clock line after only `B', `M' and `A' have been loaded. If 30 negative transitions have been counted, then the `R' counter will be loaded with the new data. When ENABLE is low, the DATA and CLOCK inputs are disabled internally. As soon as ENABLE is high, the DATA and CLOCK inputs are enabled and data may be clocked into the device. The data is transferred from the input shift register to the counter latches on the negative transition of the ENABLE input and both inputs to the phase detector are synchronised to each other. This pin allows an external capacitor to be connected in parallel with the internal ramp capacitor and allows further programming of the device. (This capacitor is connected from CAP to VSS). Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning of a count cycle and will remain low until the `A' counter completes its cycle. MC then goes high and remains high until the `M' counter completes its cycle, at which point both `A' and `M' counters are reset. This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler values. The program range of the `A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including 4128/129. The programming range of the `M' counter is 8-1023 and, for correct operation, M>A. Where every possible channel is required, the minimum total division ratio N should be: N>P 22P. An external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS. An external hold capacitor should be connected between this pin and VSS.
8, 11 12
13
CLOCK
14
ENABLE
15 16
CAP MC
17 18
RB CH
3
NJ88C25
2*0 VDD = 5V OSC IN, FIN = 0V TO 5V SQUARE WAVE SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1*5 8 7 6 5 4 3 2 TOTAL SUPPLY CURRENT IS THE SUM OF THAT DUE TO FIN AND OSC IN 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 8 9 10 1 VDD = 5V FIN = LOW FREQUENCY 0V TO 5V SQUARE WAVE
OSC IN 1*0 FIN 0*5
10MHz
1MHz
0*2
0*4
0*6 0*8 1*0 1*2 INPUT LEVEL (V RMS)
1*4
1*6
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
PROGRAMMING Reference Divider Chain
The comparison frequency depends upon the crystal oscillator frequency and the division ratio of th `R' counter, which can be programmed in the range 3 to 2047, and a fixed divide by two stage. fosc R= 23fcomp where fosc = oscillator frequency, fcomp = comparison frequency, R = `R' counter ratio For example, where the crystal frequency = 10MHz and a channel spacing comparison frequency of 12*5kHz is required, The division ratio N = MP1A, where M is the ratio of the `M' counter in the range 8 to 1023 and A is the ratio of the `A' counter in the range 0 to 127. Note that M>A and N = fVCO fcomp For example, if the desired VCO frequency = 275MHz, the comparison frequency is 12*5kHz and a two-modulus prescaler of 464/65 is being used, then
6 N = 275310 3 = 223103 12*5310 Now, N = MP1A, which can be rearranged as N/P = M1A/P. In our example we have P = 64, therefore
R=
107 = 400 2312*53103
Thus, the `R' register would be programmed to 400 expressed in binary. The total division ratio would then be 23400 = 800 since the total division ratio of the `R' counter plus the 42 stage is from 6 to 4094 in steps of 2.
VCO Divider Chain
The synthesised frequency of the voltage controlled oscillator (VCO) will depend on the division ratios of the `M' and `A' counters, the ratio of the external two-modulus prescaler (P/P11)and the comparison frequency .
A 223103 = M1 64 64 such that M = 343 and A /64 = 0*75. Now, M is programmed to the integer part = 343 and A is programmed to the fractional part364 i.e., A = 0*75364 = 48. NB The minimum ratio N that can be used is P 22P (=4032 in our example) for all contiguous channels to be available. To check: N = 343364148 = 22000, which is the required division ratio and is greater than 4032 ( = P 22P ).
CLOCK
tCH
tCL
ENABLE
tEH
tES tDS
tEH tDH
tES
DATA
Fig. 5 Timing diagram showing timing periods required for correct operation
4
NJ88C25
1 CLOCK
2
3
4
5
(17)28
(18)29
(19)30
ENABLE DATA A6 A5 A4 A3 A2 (M2)R2 (B1)R1 (B0)R0
Fig.6 Timing diagram showing programming details
PHASE COMPARATORS
Noise output from a synthesiser loop is related to loop gain: KPD KVCO N where KPD is the phase detector constant (volts/rad), KVCO is the VCO constant (rad/sec/volt) and N is the overall loop division ratio. When N is large and the loop gain is low, noise may be reduced by employing a phase comparator with a high gain. The sample and hold phase comparator in the NJ88C25 has a high gain and uses a double sampling technique to reduce spurious outputs to a low level. A standard digital phase/frequency detector driving a threestate output,PDB, provides a `coarse' error signal to enable fast switching between channels. The PDB output is active until the phase error is within the sample and hold phase detector window, when PDB becomes high impedance. Phase-lock is indicated at this point by a low level on LD. The sample and hold phase detector provides a `fine' error signal to give further phase adjustment and to hold the loop in lock. An internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the `fine' error signal, PDA. When in phase lock, this output would be typically at (VDD2VSS)/2 and any offset from this would be proportional to phase error. The relationship between this offset and the phase error is the phase comparator gain, KPDA, which is programmable with an external resistor, RB, and a capacitor, CAP. An internal 50pF capacitor is used in the sample and hold comparator.
5
NJ88C25
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 * NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * UNITED KINGDOM & SCANDINAVIA Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1992 Publication No. DS3280 Issue No. 1.3 May 1992
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