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FastEdgeTM Series CY2DP3110
1 of 2:10 Differential Clock/Data Fanout Buffer
Features
* Ten ECL/PECL differential outputs * One ECL/PECL differential or single-ended inputs (CLKA) * One HSTL differential or single-ended inputs (CLKB) * Hot-swappable/-insertable * 50 ps output-to-output skew * 150 ps device-to-device skew * 400 ps propagation delay (typical) * 1.2 ps RMS period jitter (max.) * 1.5 GHz Operation (2.7 GHz maximum toggle frequency) * PECL and HSTL mode supply range: VCC = 2.5V 5% to 3.3V5% with VEE = 0V * ECL mode supply range: VE E = -2.5V 5% to -3.3V5% with VCC = 0V * Industrial temperature range: -40C to 85C * 32-pin TQFP package * Temperature compensation like 100K ECL * Pin-compatible with MC100ES6111
Functional Description
The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3110 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL single-ended signal to 10 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-F capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point. Since the CY2DP3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3110 delivers consistent performance over various platforms
Block Diagram
V BB
Pin Configuration
Q1 Q1#
VCC CLKA CLKA#
Q2 Q2#
VEE
VCC CLKB CLKB#
Q3 Q3# Q4 Q4#
VCC CLK_SEL CLKA CLKA# VBB CLKB CLKB# VEE
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
VCC Q0 Q0# Q1 Q1# Q2 Q2# VCC
Q0 Q0#
CY2DP3110
CLK_SEL
VEE
VBB
Q7 Q7# Q8 Q8# Q9 Q9#
Cypress Semiconductor Corporation Document #: 38-07469 Rev.*G
*
3901 North First Street
*
San Jose, CA 95134
VCC Q9# Q9 Q8# Q8 Q7# Q7 VCC
Q6 Q6#
9 10 11 12 13 14 15 16
VEE
Q5 Q5#
24 23 22 21 20 19 18 17
Q3 Q3# Q4 Q4# Q5 Q5# Q6 Q6#
* 408-943-2600 Revised July 28, 2004
FastEdgeTM Series CY2DP3110
Pin Definitions[1, 2, 3]
Pin 2 3 4 5 6 7 8 1,9,16, 25,32 31,29,27,24,22,20,18, 15,13,11 30,28,26,23,21,19,17, 14,12,10 Table 1. Control CLK_SEL 0 1 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations CLKB, CLKB# input pair is active. CLKB can be driven with HSTL compatible signals with respective power configurations Operation Name CLK_SEL CLKA CLKA# VBB CLKB, CLKB# VEE VCC Q(0:9) Q#(0:9) I/O I,PD I,PD[1] Type ECL/PECL Input Clock Select. ECL/PECL Differential Input Clocks. Description
I,PD/PU ECL/PECL Differential Input Clocks. O I,PD I,PD/PU -PWR +PWR O O Bias HSTL HSTL Power Power Reference Voltage Output. Alternate Differential Input Clocks. Alternate Differential Input Clocks. Negative Power Supply. Positive Power Supply.
ECL/PECL ECL/PECL Differential Output Clocks. ECL/PECL ECL/PECL Differential Output Clocks.
Governing Agencies
The following agencies provide specifications that apply to the CY2DP3110. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name JEDEC Specification JESD 020B (MSL) JESD 8-6 (HSTL) JESD 51 (Theta JA) JESD 8-2 (ECL) JESD 65-B (skew,jitter) 883E Method 1012.1 (Thermal Theta JC)
Mil-Spec
Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either -3.3V or -2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
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FastEdgeTM Series CY2DP3110
Absolute Maximum Ratings
Parameter VCC VEE TS TJ ESDh MSL Description Positive Supply Voltage Negative Supply Voltage Temperature, Storage Temperature, Junction ESD Protection Moisture Sensitivity Level Assembled Die Condition Non-Functional Non-Functional Non-Functional Non-Functional Human Body Model 2000 3 50 Min. -0.3 -4.6 -65 Max. 4.6 0.3 +150 150 Unit V V C C V N.A. gates
Gate Count Total Number of Used Gates
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter IBB LUI TA OJc OJa IEE CIN LIN VIN VTT VOUT IIN Description Output Reference Current Latch Up Immunity Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient Maximum Quiescent Supply Current Input pin capacitance Pin Inductance Input Voltage Output Termination Voltage Output Voltage Input Current[7] Relative to VCC[6] Relative to VCC[6] Relative to VCC[6] VIN = VIL, or VIN = VIH -0.3 -0.3 VCC - 2 VCC + 0.3 l150l Condition Relative to VBB Functional, typical Functional Functional Functional VEE pin -40 35[4] 76[4] 130[5] 3 1 VCC + 0.3 100 +85 Min. Max. |200| Unit uA mA C C/W C/W mA pF nH V V V uA
PECL/HSTL DC Electrical Specifications
Parameter VCC VCMR VX VOH VOL VIH VIL VBB[3] Description Operating Voltage PECL Input Differential Cross Point Voltage[8] Condition 2.5V 5%, VEE = 0.0V 3.3V 5%, VEE = 0.0V Differential operation Min. 2.375 3.135 1.2 0.68 VCC - 1.25 VCC - 1.995 VCC -1.995 VCC - 1.165 VCC - 1.945
[11]
Max. 2.625 3.465 VCC 0.9 VCC - 0.7 VCC - 1.5 VCC - 1.3 VCC - 0.880 [11] VCC - 1.625
Unit V V V V V V V V V
HSTL Input Differential Crosspoint Volt- Standard Load Differential age[9] Operation Output High Voltage Output Low Voltage VCC = 3.3V 5% VCC = 2.5V 5% Input Voltage, High Input Voltage, Low Output Reference Voltage IOH = -30 mA[10] IOL = -5 mA[10] Single-ended operation Single-ended operation Relative to VCC[6]
VCC - 1.620 VCC - 1.220 V Notes: 4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH - VOL) (number of differential outputs used); IEE does not include current going off chip. 6. where VCC is 3.3V5% or 2.5V5% 7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. Refer to Figure 1 9. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2. 10. Equivalent to a termination of 50 to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 11. VIL will operate down to VEE; VIH will operate up to VCC
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FastEdgeTM Series CY2DP3110
ECL DC Electrical Specifications
Parameter VEE VCMR VOH VOL VIH VIL VBB[3] Description Negative Power Supply ECL Input Differential cross point voltage[8] Output High Voltage Output Low Voltage VEE = -3.3V 5% VEE = -2.5V 5% Input Voltage, High Input Voltage, Low Output Reference Voltage Condition -2.5V 5%, VCC = 0.0V -3.3V 5%, VCC = 0.0V Differential operation IOH = -30 mA[10] IOL = -5 mA[10] Single-ended operation Single-ended operation Min. -2.625 -3.465 VEE + 1.2 -1.25 -1.995 -1.995 -1.165 -1.945 [11] - 1.620 Max. -2.375 -3.135 0V -0.7 -1.5 -1.3 -0.880 [11] -1.625 - 1.220 Unit V V V V V V V
AC Electrical Specifications
Parameter VPP VCMRO FCLK TPD VDIF Vo tsk(0) tsk(PP) TPER tsk(P) TR,TF Description Output Common Voltage Range (typ.) Input Frequency Propagation Delay CLKA or CLKB to Output pair[13] HSTL Differential Input Voltage[12] Output Voltage (peak-to-peak; see Figure 2) Output-to-output Skew Part-to-Part Output Skew Output Period Jitter (rms)[14] Output Pulse Skew[15] 50% duty cycle Standard load PECL, ECL = 660 MHz HSTL < 1GHz Duty Cycle Standard Load Differential Operation < 1 GHz 660 MHz [13], See Figure 3 660 MHz [13] 660 MHz [13] 660 MHz [13], See Figure 3 660 MHz 50% duty cycle Differential 20% to 80% - 280 280 0.4 0.375 - - - - 0.08 Condition Min. 0.1 VCC - 1.425 1.5 650 750 1.9 - 50 150 1.2 50 0.3 Max. 1.3 Unit V V GHz ps ps V V ps ps ps ps ns PECL/ECL Differential Input Voltage[8] Differential operation
Output Rise/Fall Time (see Figure 2)
Notes: 12. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew 13. 50% duty cycle; standard load; differential operation 14. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points. 15. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
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FastEdgeTM Series CY2DP3110
Timing Definitions
VCC
VCM R M ax = VCC
V IH
VPP
V P P ra n g e 0 .1 V - 1 .3 V
VCM R
V IL
V C M R M in = V E E + 1 .2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
VCC
V C C = 3 .3 V
V IH V D IF = > = 0 .4 V m in
V X m a x = 0 .9 V
V D IF
VX
V IL
VEE
V E E = 0 .0 V
V X M in = 0 .6 8
Figure 2. HSTL Differential Input Waveform Definitions
tr, tf, 2 0 -8 0 %
VO
Figure 3. ECL/LVPECL Output
In p u t C lo c k
VPP
TPLH, TPD O u tp u t C lo c k TPHL
VO
tS K (O )
A n o th e r O u tp u t C lo c k
Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
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FastEdgeTM Series CY2DP3110
Test Configuration
Standard test load using a differential pulse generator and differential measurement instrument.
VTT R T = 50 ohm P u ls e G e n e ra to r Z = 50 ohm
5" VTT
R T = 50 ohm
Zo = 50 ohm R T = 50 ohm VTT DUT C Y2DP3110
Zo = 50 ohm
5"
R T = 50 ohm
VTT
Figure 5. CY2DP3110 AC Test Reference
Applications Information
Termination Examples
CY2DP3110
VCC
5"
VTT R
T
= 50 ohm
Zo = 50 ohm
5"
R VTT
T
= 50 ohm
VEE
Figure 6. Standard LVPECL - PECL Output Termination
CY2DP3110
VCC
5"
VTT R T = 50 ohm
Zo = 50 ohm
5"
VTT R T = 50 ohm
V B B (3 .3 V ) VEE
Figure 7. Driving a PECL/ECL Single-ended Input
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FastEdgeTM Series CY2DP3110
CY2DP3110
V C C = 3 .3 V
5"
3 .3 V 120 ohm
LVDS
Zo = 50 ohm
5"
33 ohm ( 2 p la c e s )
120 ohm 3 .3 V
51 ohm ( 2 p la c e s )
VEE = 0V
L V P E C L to LVDS
Figure 8. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface
VDD-2 X
VCC Y
Z
One output is shown for clarity
Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, "PECL Translation, SAW Oscillators, and Specs" for other signalling standards and supplies.
Ordering Information
Part Number CY2DP3110AI CY2DP3110AIT 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40 to 85C Industrial, -40 to 85C
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FastEdgeTM Series CY2DP3110
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
Dimensions in mm
51-85088-*B
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
FastEdgeTM Series CY2DP3110
Document History Page
Document Title: CY2DP3110 FastEdgeTM Series 1 of 2:10 Differential Clock/Data Fanout Buffer Document Number: 38-07469 REV. ** *A ECN NO. 121284 126251 Issue Date 11/12/02 04/15/03 Orig. of Change RGL RGL New Data Sheet Added VBB in the block diagram Corrected specs that does not match EROS/IROS Changed VOHMIN in PECL Output table to VCC-1.2V Shifted table on ECL levels to match PECL Added power-up requirements to absolute maximum conditions Changed title (ComLink to FastEdge) Changed operation value from 3.0 GHz to 1.5 GHz in features Modified Note 21: reduced swing value from up to 3 GHz to 2.2 GHz Specified TTB value from TBD to 250 ps Specified Vo (pp) values from TBDs to 0.34 ps(min) at < 1.5 GHz, 0.30 ps (typ) at 2.2 GHz Changed Jitter value from 10 ps to 1 ps (intrinsic) Corrected the "VCCO" to "VCC" in the Pin Configuration diagram. Description of Change
*B *C
127696 128731
06/12/03 08/04/03
RGL RGL
*D *E
130299 227708
11/19/03 See ECN
RGL
RGL/GGK Changed the max. Dissipation, Junction to ambient from 100 to 70C/W Added Junction Temperature(TJ) parameter of 150C max Replaced ICC calculation with power calculation in the footnote RGL/GGK Provided data for TBD's to match the device RGL/GGK Changed VOH and VOL to match the Char Data
*F *G
229393 247626
See ECN See ECN
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