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| WF4M16-XDTX5 HI-RELIABILITY PRODUCT 2x2Mx16 5V FLASH MODULE FEATURES ADVANCED* s Access Time of 90, 120, 150ns s Packaging: * 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213). Fits standard 56 SSOP footprint. s Sector Architecture * 32 equal size sectors of 64KBytes per each 2Mx8 chip * Any combination of sectors can be erased. Also supports full chip erase. s Minimum 100,000 Write/Erase Cycles Minimum s Organized as two banks of 2Mx16; User Configurable as 4 x 2Mx8 s Commercial, Industrial, and Military Temperature Ranges s 5 Volt Read and Write. 5V 10% Supply. s Low Power CMOS s Data Polling and Toggle Bit feature for detection of program or erase cycle completion. s Supports reading or programming data to a sector not being erased. s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation, Separate Power and Ground Planes to improve noise immunity s RESET pin resets internal state machine to the read mode. s Ready/Busy (RY/BY) output for direction of program or erase cycle completion. * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. Note: For programming information refer to Flash Programming 16M5 Application Note. FIG. 1 PIN CONFIGURATION FOR WF4M16-XDTX5 56 CSOP PIN DESCRIPTION NC RESET A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 A0 NC CS3 CS4 I/O2 I/O10 I/O3 I/O11 GND TOP VIEW CS1 A12 A13 A14 A15 NC CS2 NC A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY OE WE NC I/O13 I/O5 I/O12 I/O4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O0-15 Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Ready/Busy Reset BLOCK DIAGRAM I/O0-7 RESET WE OE A0-20 RY/BY 2M x 8 2M x 8 2M x 8 2M x 8 I/O8-15 A0-20 WE CS1-4 OE VCC GND RY/BY RESET CS1 CS2 CS3 CS4 NOTE: 1. RY/BY is an open drain output and should be pulled-up to Vcc with an external resistor. 2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1 and CS3 both active. CS2 and CS4 control the same data bus. Reads cannot be done with CS2 and CS4 both active. 3. Address compatible with Intel 2M8 56 SSOP. November 1999 Rev.3 1 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com WF4M16-XDTX5 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Short Circuit Output Current Endurance - Write/Erase Cycles (Mil Temp) Data Retention (Mil Temp) Symbol VT PT Tstg IOS Ratings -2.0 to +7.0 8 -65 to +125 100 100,000 min 20 Unit V W C mA cycles years Parameter OE capacitance WE capacitance CS capacitance Data I/O capacitance Address input capacitance CAPACITANCE (TA = +25C) Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 45 45 15 25 45 Unit pF pF pF pF pF This parameter is guaranteed by design but not tested. RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Operating Temperature (Mil.) Operating Temperature (Ind.) Symbol VCC VSS VIH VIL TA TA Min 4.5 0 2.0 -0.5 -55 -40 Max 5.5 0 VCC + 0.5 +0.8 +125 +85 Unit V V V V C C DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage Symbol ILI ILOx32 ICC1 ICC2 ICC3 VOL VOH VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5 CS = VIL, OE = VIH, VCC = 5.5 VCC = 5.5, CS = VIH, f = 5MHz IOL = 12.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 0.85xVcc 3.2 4.2 Min Max 10 10 82 122 8.0 0.45 Unit A A mA mA mA V V V NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH. 2. Icc active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 2 WF4M16-XDTX5 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (VCC = 5.0V, TA = -55C to +125C) Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Sector Erase (2) Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. tOEH 10 tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS 0 50 44 256 10 Symbol Min tWC tCS tWP tAS tDS tDH tAH tWPH 90 0 45 0 45 0 45 20 300 15 0 50 44 256 10 -90 Max Min 120 0 50 0 50 0 50 20 300 15 0 50 44 256 -120 Max Min 150 0 50 0 50 0 50 20 300 15 -150 Max ns ns ns ns ns ns ns ns s sec s s sec sec ns Unit AC CHARACTERISTICS - READ-ONLY OPERATIONS (VCC = 5.0V, TA = -55C to +125C) Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select High to Output High Z (1) Output Enable High to Output High Z (1) Output Hold from Addresses, CS or OE Change, whichever is First 1. Guaranteed by design, not tested. Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 90 90 90 40 20 20 0 -90 Max Min 120 120 120 50 30 30 0 -120 Max Min 150 150 150 55 35 35 -150 Max ns ns ns ns ns ns ns Unit 3 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com WF4M16-XDTX5 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Programming Operation (1) Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. tOEH 10 Symbol Min tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL 0 44 256 10 tWC tWS tCP tAS tDS tDH tAH tCPH 90 0 45 0 45 0 45 20 300 15 0 44 256 10 -90 Max Min 120 0 50 0 50 0 50 20 300 15 0 44 256 -120 Max Min 150 0 50 0 50 0 50 20 300 15 -150 Max ns ns ns ns ns ns ns ns s sec s sec sec ns Unit FIG. 2 AC TEST CIRCUIT Current Source I OL AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level D.U.T. VZ Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V 1.5V Output Timing Reference Level C eff = 50 pf (Bipolar Supply) I OH Current Source NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 4 WF4M16-XDTX5 FIG. 3 AC WAVEFORMS FOR READ OPERATIONS tDF tOH Addresses Stable tRC tOE tACC tCE WE OE Addresses 5 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com Outputs CS High Z Output Valid High Z WF4M16-XDTX5 FIG. 4 WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED tOH tDF tRC tOE PA Data Polling tAH tWHWH1 PA tAS tWPH tDH 5555H tGHWL tWC tWP tCS A0H PD D7 DOUT Addresses WE OE CS tDS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 6 5.0 V Data tCE WF4M16-XDTX5 FIG. 5 AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS SA 2AAAH 5555H 2AAAH 5555H tWPH tAS 5555H tWP AAH tDS tGHWL tCS tDH 55H tAH 80H AAH 55H 10H/30H Addresses WE OE CS Data NOTE: 1. SA is the sector address for Sector Erase. 7 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com VCC tVCS WF4M16-XDTX5 FIG. 6 AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS SA 2AAAH 5555H 2AAAH 5555H tWPH tAS 5555H tWP AAH tDS tGHWL tCS tDH 55H tAH 80H AAH 55H 10H/30H Addresses WE OE CS Data White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 8 VCC tVCS WF4M16-XDTX5 FIG. 7 ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS PA Data Polling tAH tWHWH1 PA tAS tGHEL tCP tCPH tDH A0H 5555H tWC tWS PD WE OE CS tDS Addresses D7 DOUT NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 9 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 5.0 V Data WF4M16-XDTX5 PACKAGE 213: 56 LEAD, DUAL CAVITY CERAMIC SOP 23.63 (0.930) 0.25 (0.010) 21.59 (0.850) TYP 3.50 (0.138) 0.83 (0.032) 0.18 (0.007) 0.03 (0.001) 1.58 (0.062) TYP 0.51 (0.020) 0.13 (0.005) 16.13 (0.635) 0.13 (0.005) 12.96 (0.510) 0.13 (0.005) 10.93 (0.430) 0.13 (0.005) 0.51 (0.020) TYP + PIN 1 IDENTIFIER 0.80 (0.031) TYP 0.25 (0.010) 0.05 (0.002) SEE DETAIL "A" 4.57 (0.180) MAX 0.51 (0.020) TYP R 0.18 (0.007) 0 / -4 DETAIL "A" ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES FIG. 8 ALTERNATE PIN CONFIGURATION FOR WF4M16W-XDTX5 56 CSOP PIN DESCRIPTION I/O0-15 NC RESET A10 A9 A8 A0 A1 A2 A3 A4 A5 A6 GND A7 VCC I/O9 I/O1 I/O8 I/O0 NC NC CS3 CS4 I/O2 I/O10 I/O3 I/O11 GND TOP VIEW CS1 A11 A12 A13 A14 NC CS2 A20 A19 A18 A17 A16 A15 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY OE WE NC I/O13 I/O5 I/O12 I/O4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power Supply Ground Ready/Busy Reset BLOCK DIAGRAM I/O0-7 RESET WE OE A0-20 RY/BY 2M x 8 2M x 8 2M x 8 2M x 8 I/O8-15 A0-20 WE CS1-4 OE VCC GND RY/BY RESET CS1 CS2 CS3 CS4 NOTE: 1. RY/BY is an open drain output and should be pulled-up to Vcc with an external resistor. 2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1 and CS3 both active. CS2 and CS4 control the same data bus. Reads cannot be done with CS2 and CS4 both active. 3. Address compatible with Intel 1M16 56 SSOP, with the addition of A20 at pin 8. Also refer to Note 2. White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com 10 WF4M16-XDTX5 ORDERING INFORMATION W F 4M16 - XXX DT X 5 X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5=5V DEVICE GRADE: M = Military, 883 Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C PACKAGE TYPE: DT = 56 Lead Dual Cavity CSOP (Package 213) fits standard 56 SSOP footprint ACCESS TIME (ns) ORGANIZATION, 2M x 16 User configurable as 4 x 2M x 8 Flash WHITE ELECTRONIC DESIGNS CORP. 11 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com |
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