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6 GHz Fractional-N Frequency Synthesizer ADF4156
FEATURES
RF bandwidth to 6 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/ ADF4153 and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADISimPLL Cycle slip reduction for faster lock times
GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (-) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.
APPLICATIONS
CATV equipment Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP RSET
ADF4156
REFIN x2 DOUBLER 5-BIT R COUNTER /2 DIVIDER VDD DGND LOCK DETECT MUXOUT OUTPUT MUX SDOUT VDD RDIV NDIV THIRD ORDER FRACTIONAL INTERPOLATOR FRACTION REG MODULUS REG INTEGER REG N COUNTER CURRENT SETTING RFCP4 RFCP3 RFCP2 RFCP1 RFINA RFINB + PHASE FREQUENCY DETECTOR - REFERENCE
CHARGE PUMP CSR
CP
HIGH Z
CE CLOCK DATA LE
32-BIT DATA REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. 0
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ADF4156 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Impedance ..................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description........................................................................... 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 RF INT Divider............................................................................. 8 INT, FRAC, MOD, and R Relationship ..................................... 8 RF R Counter ................................................................................ 8 Phase Frequency Detector (PFD) and Charge Pump.............. 9 MUXOUT and LOCK Detect..................................................... 9 Input Shift Registers ..................................................................... 9 Program Modes ............................................................................ 9 Register Maps.................................................................................. 10 FRAC/INT Register, R0............................................................. 11 PHASE REGISTER, R1.............................................................. 12 MOD/R Register, R2 .................................................................. 13 Function Register, R3................................................................. 15 CLK Div Register, R4 ................................................................. 16 Reserved Bits............................................................................... 16 Initialization Sequence .............................................................. 16 RF Synthesizer: A Worked Example ........................................ 17 Modulus....................................................................................... 17 Reference Doubler and Reference Divider ............................. 17 12-Bit Programmable Modulus................................................ 17 Cycle Slip Reduction for Faster Lock Times........................... 17 Spur Mechanisms ....................................................................... 18 Spur Consistency and Fractional Spur Optimization ........... 18 PHASE RESYNC ........................................................................ 19 Low Frequency Applications .................................................... 19 Filter Design--ADIsimPLL....................................................... 19 Interfacing ................................................................................... 20 PCB Design Guidelines for Chip Scale Package .................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 22
REVISION HISTORY
5/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADF4156 SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 , unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 3 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD NOISE CHARACTERISTICS Normalized Phase Noise Floor 4 Phase Noise Performance 5 5800 MHz Output 6
1 2
B Version 0.5/6.0
Unit GHz min/max
Test Conditions/Comments 1 -10 dBm min to 0 dBm max; for lower frequencies, ensure slew rate (SR) > 400 V/s For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 25 V/s Biased at AVDD/2 2
10/250 0.4/AVDD 10 100 32
MHz min/max V p-p min/max pF max A max MHz max
5 312.5 2.5 2.7/10 1 2 2 2 1.4 0.6 1 10 1.4 VDD - 0.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 32 -211 -89
mA typ A typ % typ k min/max nA typ % typ % typ % typ V min V max A max pF max V min V min A max V max V min/V max V min/V max mA max dBc/Hz typ dBc/Hz typ
Programmable With RSET = 5.1 k With RSET = 5.1 k Sink and source current 0.5 V < VCP < VP - 0.5 0.5 V < VCP < VP - 0.5 VCP = VP/2
Open-drain output chosen; 1 k pull-up to 1.8 V CMOS output chosen IOL = 500 A
26 mA typical
@ VCO output @ 5 kHz offset, 25 MHz PFD frequency
Operating temperature for B version: -40C to +85C. AC coupling ensures AVDD/2 bias. 3 Guaranteed by design. Sample tested to ensure compliance. 4 This figure can be used to calculate phase noise for any application. Use the formula -213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 5 The phase noise is measured with the EVAL-ADF4156EB1 evaluation board and the Agilent E5500 phase noise system. 6 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 5800 MHz; N = 232; loop B/W = 20 kHz, ICP = 313 A; lowest noise mode.
Rev. 0 | Page 3 of 24
ADF4156
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 , unless otherwise noted. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width
Timing Diagram
t4
CLOCK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t7
LE
t1
LE
t6
05863-002
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 24
ADF4156 ABSOLUTE MAXIMUM RATINGS
TA = 25C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted. Table 3.
Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Maximum Junction Temperature Rating -0.3 V to +4 V -0.3 V to +0.3 V -0.3 V to +5.8 V -0.3 V to +5.8 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +125C 150C 260C 40 sec 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
THERMAL IMPEDANCE
Table 4. Thermal Impedance
Package Type TSSOP LFCSP_VQ (Paddle Soldered) JA 112 30.4 Unit C/W C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 24
ADF4156 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET CP CPGND AGND RFINB RFINA AVDD REFIN
1 2 3 4 5 6 7 8 16 15
VP DVDD MUXOUT LE DATA CLOCK CE
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TOP VIEW (Not to Scale)
ADF4156
14 13 12 11 10 9
CPGND AGND AGND RFINB RFINA
1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
CP RSET VP DVDD DVDD
TOP VIEW (Not to Scale)
ADF4156
15 14 13 12 11
MUXOUT LE DATA CLOCK CE
6 7 8 9 10
DGND
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP 1 LFCSP 19 Mnemonic RSET Description Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is 25.5 ICPmax = RSET
2 3 4 5 6 7
20 1 2, 3 4 5 6, 7
CP CPGND AGND RFINB RFINA AVDD
8 9 10 11 12 13 14 15
8 9, 10 11 12 13 14 15 16, 17
REFIN DGND CE CLOCK DATA LE MUXOUT DVDD
16
18
VP
where: RSET = 5.1 k. ICP max = 5 mA. Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn, drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor, typically 100 pF. Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V 10%. AVDD must have the same voltage as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the five latches. The control bits are used to select the latch. Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Rev. 0 | Page 6 of 24
AVDD AVDD REFIN DGND DGND
05863-004
ADF4156 TYPICAL PERFORMANCE CHARACTERISTICS
PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 A, phase noise measurements taken on the Agilent E5500 phase noise system.
10 5 0 6.00 5.95 CSR ON 5.90 5.85 CSR OFF 5.80 5.75 5.70 5.65 -100
-10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9
05863-017
P = 4/5
P = 8/9
FREQUENCY (GHz)
-5
POWER (dBm)
0
100
200
300
400
500
600
700
800
900
FREQUENCY (GHz)
TIME (s)
Figure 5. RF Input Sensitivity
0 -20 -40
Figure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHz with CSR On and Off
5.95 5.90 5.85 5.80 5.75 5.70 CSR ON
05863-018 05863-022
LOW NOISE MODE RF = 5800.25MHz, PFD = 25MHz, N = 232, FRAC = 2, MOD = 200, 20kHz LOOP BW, ICP = 313A,
PHASE NOISE (dBc/Hz)
-60 -80 -100 -120 -140 -160 -180 1k DSB INTEGRATED PHASE ERROR = 0.73 RMS, PHASE NOISE @ 5kHz = -89.5dBc/Hz, ZCOMM V940ME03 VCO 10k 100k 1M 10M
FREQUENCY (GHz)
CSR OFF
5.65 5.60 -100
100M
0
100
200
300
400
500
600
700
800
900
FREQUENCY (Hz)
TIME (s)
Figure 6. Phase Noise and Spurs, Low Noise Mode
0 -20 -40
Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 57905 MHz with CSR On and Off
6 5 4 3 2 ICP (mA) 1 0 -1 -2 -3 -4
05863-019
LOW SPUR MODE RF = 5800.25MHz, PFD = 25MHz, N = 232, FRAC = 2, MOD = 200, 20kHz LOOP BW, ICP = 313A, DSB INTEGRATED PHASE ERROR = 1.09 RMS, PHASE NOISE @ 5kHz = -83dBc/Hz, ZCOMM V940ME03 VCO
PHASE NOISE (dBc/Hz)
-60 -80 -100 -120 -140 -160 -180 1k
-5 -6 0 1 2 VCP (V) 3 4 5
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 7. Phase Noise and Spurs, Low Spur Mode. (Note that fractional spurs are removed and only the integer boundary spur remains in low spur mode.)
Figure 10. Charge Pump Output Characteristics
Rev. 0 | Page 7 of 24
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05863-021
ADF4156 CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL 100k TO R COUNTER BUFFER
05863-005
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = FPFD x (INT + (FRAC/MOD)) where RFOUT is the output frequency of external voltage controlled oscillator (VCO). FPFD = REFIN x [(1 + D)/(R x (1 + T))] where: REFIN is the reference input frequency. D is the REFIN doubler bit. T is the REFIN divide-by-2 bit (0 or 1). R is the preset divide ratio of binary 5-bit programmable reference counter (1 to 32). INT is the preset divide ratio of binary 12-bit counter (23 to 4095). MOD is the preset fractional modulus (2 to 4095). FRAC is the numerator of the fractional division (0 to MOD-1). (2) (1)
NC REFIN NC SW1 SW3 NO
SW2
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler.
BIAS GENERATOR 1.6V AVDD 2k 2k
RFINA
RFINB FROM RF INPUT STAGE
05863-006
RF N DIVIDER
N = INT + FRAC/MOD TO PFD
N COUNTER
AGND
Figure 12. RF Input Stage
INT REG
THIRD ORDER FRACTIONAL INTERPOLATOR
MOD REG
FRAC VALUE
05863-007
Figure 13. RF INT Divider
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed.
Rev. 0 | Page 8 of 24
ADF4156
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function, and gives a consistent reference spur level.
HI D1 U1 +IN CLR1 Q1 UP
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R counter, a 12-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of five latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2 and C1) in the shift register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 6. Figure 16 shows a summary of how the latches are programmed.
PROGRAM MODES
DELAY U3 CHARGE PUMP CP
Table 6 and Figure 16 through Figure 20 show how to set up the program modes in the ADF4156. A number of settings in the ADF4156 are double buffered. These include the modulus value, phase value, R counter value, reference doubler, reference divide-by-2, and current setting. This means that two events have to occur before the part uses a new value of any of the double buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0. For example, any time that the modulus value has been updated, Register R0 must be written to after this, to ensure that the modulus value is loaded correctly. Table 6. C3, C2, and C1 Truth Table
C3 0 0 0 0 1 Control Bits C2 0 0 1 1 0 C1 0 1 0 1 0 Register Register R0 Register R1 Register R2 Register R3 Register R4
HI
CLR2 DOWN D2 Q2
05863-008
U2 -IN
Figure 14. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M4, M3, M2, and M1 (for details, see Figure 16). Figure 15 shows the MUXOUT section in block diagram form.
THREE-STATE OUTPUT DVDD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT SERIAL DATA OUTPUT CLK DIVIDER OUTPUT R DIVIDER/2 N DIVIDER/2 DGND
05863-009
DVDD
MUX
CONTROL
MUXOUT
Figure 15. MUXOUT Schematic
Rev. 0 | Page 9 of 24
ADF4156 REGISTER MAPS
FRAC/INT REGISTER (R0)
RESERVED DB31 0 MUXOUT CONTROL 12-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC) CONTROL BITS DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
PHASE REGISTER (R1)
RESERVED 12-BIT PHASE VALUE (PHASE) (DB) DBB1 CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
MOD/R REGISTER (R2)
REFERENCE DOUBLER DBB1
DBB1
PRESCALER RESERVED RESERVED
DBB1
DBB1
CSR EN
NOISE MODE
RDIV2 DBB1
CURRENT SETTING
5-BIT R COUNTER
12-BIT MODULUS WORD (DB)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 L2 L1 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(1) C1(0)
FUNCTION REGISTER (R3)
CP THREESTATE PD POLARITY SD RESET COUNTER RESET
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U7 U6 U5 U4 U3 C3(0) C2(1) C1(1)
CLKDIV REGISTER (R4)
CLK DIV MODE CONTROL BITS
05863-010
RESERVED
12-BIT CLOCK DIVIDER VALUE
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0
1DBB
0
0
0
0
0
0
0
0
0
0
M2
M1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
PD
RESERVED
RESERVED
LDP
CONTROL BITS
0
0
0
C3(1) C2(0) C1(0)
= DOUBLE BUFFERED BIT.
Figure 16. Register Summary
Rev. 0 | Page 10 of 24
ADF4156
FRAC/INT REGISTER, R0
With R0[2, 1, 0] set to [0, 0, 0], the on-chip FRAC/INT register is programmed. Figure 17 shows the input data format for programming this register.
12-Bit FRAC Value
These twelve bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1. The FRAC value must be less than the value loaded into the MOD register.
12-Bit INT Value
These twelve bits control what is loaded as the INT value. This determines the overall feedback division factor. It is used in Equation 1 (see the INT, FRAC, MOD, and R Relationship section).
RESERVED DB31 0 MUXOUT CONTROL 12-BIT INTEGER VALUE (INT)
MUXOUT
The on-chip multiplexer is controlled by DB30, DB29, DB28, and DB27 on the ADF4156. See Figure 17 for the truth table.
12-BIT FRACTIONAL VALUE (FRAC) CONTROL BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
M4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
M3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DVDD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT SERIAL DATA OUTPUT RESERVED RESERVED CLK DIVIDER RESERVED RESERVED R DIVIDER/2 N DIVIDER/2 RESERVED
F12 0 0 0 0 . . . 1 1 1 1
F11 0 0 0 0 . . . 1 1 1 1
.......... F2 .......... 0 .......... 0 .......... 1 .......... 1 .......... . .......... . .......... . .......... 0 .......... 0 .......... 1 ......... 1
F1 0 1 0 1 . . . 0 1 0 1
FRACTIONAL VALUE (FRAC) 0 1 2 3 . . . 4092 4093 4094 4095
N12 0 0 0 0 . . . 1 1 1
N11 0 0 0 0 . . . 1 1 1
N10 0 0 0 0 . . . 1 1 1
N9 0 0 0 0 . . . 1 1 1
N8 0 0 0 0 . . . 1 1 1
N7 0 0 0 0 . . . 1 1 1
N6 0 0 0 0 . . . 1 1 1
N5 1 1 1 1 . . . 1 1 1
N4 0 1 1 1 . . . 1 1 1
N3 1 0 0 0 . . . 1 1 1
N2 1 0 0 1 . . . 0 1 1
N1 1 0 1 0 . . . 1 0 1
INTEGER VALUE (INT) 23 24 25 26 . . . 4093 4094 4095
05863-011
Figure 17. FRAC/INT Register (R0) Map
Rev. 0 | Page 11 of 24
ADF4156
PHASE REGISTER, R1
With R1[2, 1, 0] set to [0, 0, 1], the on chip PHASE register is programmed. Figure 18 shows the input data format for programming this register. See the PHASE RESYNC section for more information. In most applications, the phase relationship between the RF signal and the reference is not important. In such applications, the PHASE value can be used to optimize the fractional and subfractional spur levels. See the section, Spur Consistency and Fractional Spur Optimization, for more information. If neither the PHASE resync nor the spurious optimization functions are being used, it is recommended that the PHASE word be set to 1.
12-Bit PHASE Value
These twelve bits control what is loaded as the PHASE word. The word must be less than the MOD value programmed in the MOD/R register (R2). The word is used to program the RF output phase from 0 to 360 o with a resolution of 360o/MOD.
RESERVED
12-BIT PHASE VALUE (PHASE)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
P12 0 0 0 0 . . . 1 1 1 1
P11 0 0 0 0 . . . 1 1 1 1
.......... P2 .......... 0 .......... 0 .......... 1 .......... 1 .......... . .......... . .......... . .......... 0 .......... 0 .......... 1 .......... 1
P1 0 1 0 1 . . . 0 1 0 1
PHASE VALUE (PHASE) 0 1 (RECOMMENDED) 2 3 . . . 4092 4093
05863-012
4094 4095
Figure 18. PHASE Register (R1) Map
Rev. 0 | Page 12 of 24
ADF4156
MOD/R REGISTER, R2
With R1[2, 1, 0] set to [0, 1, 0], the on-chip MOD/R register is programmed. Figure 19 shows the input data format for programming this register. Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4156 above 3 GHz, this must be set to 8/9. The prescaler limits the INT value. With P = 4/5, NMIN = 23. With P = 8/9, NMIN = 75.
Noise and Spur Mode
The noise modes on the ADF4156 are controlled by DB30 and DB29 in the MOD/R register. See Figure 19 for the truth table. The noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so that it resembles white noise rather than spurious noise. As a result, the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. (Wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES)). A wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. For best noise performance, use the lowest noise setting option. As well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings.
RDIV/2
Setting this bit to 1 inserts a divide-by-2 toggle flip-flop between the R counter and PFD, which extends the maximum REFIN input rate.
Reference Doubler
Setting DB20 to 0 feeds the REFIN signal directly to the 5-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 5-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled. The maximum allowable REFIN frequency when the doubler is enabled is 30 MHz.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle in order for cycle slip reduction to work. The charge pump current setting must also be set to a minimum. See the section, Cycle Slip Reduction for Faster Lock Times, for more information.
5-Bit R Counter
The 5-bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 32 are allowed.
Charge Pump Current Setting
DB27, DB26, DB25, and DB24 set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Figure 19).
12-Bit Interpolator MOD Value
This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. Refer to the RF Synthesizer: A Worked Example section for more information.
Prescaler (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input.
Rev. 0 | Page 13 of 24
ADF4156
PRESCALER REFERENCE DOUBLER RESERVED RESERVED CSR EN RDIV2
NOISE MODE
CURRENT SETTING
5-BIT R COUNTER
12-BIT MODULUS WORD
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 L2 L1 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(1) C1(0)
C1 0 1
CYCLE SLIP REDUCTION DISABLED ENABLED
U1 0 1
REFERENCE DOUBLER DISABLED ENABLED
M12 0 0 . . . 1 1 1 1
M11 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
M2 1 1 . . . 0 0 1 1
M1 0 1 . . . 0 1 0 1
INTERPOLATOR MODULUS (MOD) 2 3 . . . 4092 4093 4094 4095
L1 0 0 1 1
L2 0 1 0 1
NOISE MODE LOW NOISE MODE RESERVED RESERVED LOW SPUR MODE P1 0 1
U2 0 1
R DIVIDER DISABLED ENABLED
PRESCALER 4/5 8/9
Figure 19. MOD/R Register (R2) Map
Rev. 0 | Page 14 of 24
05863-013
CPI4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
CPI3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
CPI2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
CPI1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
ICP (mA) 5.1k 0.31 0.63 0.94 1.25 1.57 1.88 2.19 2.5 2.81 3.13 3.44 3.75 4.06 4.38 4.69 5.0
R5 0 0 0 0 . . . 1 1 1 0
R4 0 0 0 0 . . . 1 1 1 0
R3 0 0 0 1 . . . 1 1 1 0
R2 0 1 1 0 . . . 0 1 1 0
R1 1 0 1 0 . . . 1 . 1 0
R COUNTER DIVIDE RATIO 1 2 3 4
29 30 31 32
ADF4156
FUNCTION REGISTER, R3
With R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is programmed. Figure 20 shows the input data format for programming this register. 3. 4. 5. The digital lock detect circuitry is reset. The RFIN input is debiased. The input register remains active and capable of loading and latching data.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4156. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0.
Phase Detector Polarity
DB6 in the ADF4156 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0.
RF Charge Pump Three-State
DB4 puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, 40 consecutive PFD cycles of 10 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 6 ns must occur before digital lock detect is set.
RF Power-Down
DB5 on the ADF4156 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. When a power-down is activated, the following events occur: 1. 2. The synthesizer counters are forced to their load state conditions. The charge pump is forced into three-state mode.
Sigma-Delta (SD) Reset
For most applications, DB14 should be programmed to 0. When DB14 is programmed to 0, the sigma-delta is reset and seeded with the PHASE word on every write to Register 0. This has the effect of producing consistent spur levels. If it is not required that the sigma-delta be reset on each write to Register 0, this bit should be set to 1.
CP THREESTATE
PD POLARITY
SD RESET
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
U12 0 1
SD RESET ENABLED DISABLED
U11 0 1
LDP 10ns 6ns
PD
RESERVED
RESERVED
COUNTER RESET
U7 0 1
LDP
CONTROL BITS
COUNTER RESET DISABLED ENABLED
U10 0 1
PD POLARITY NEGATIVE POSITIVE U8 0 1 CP THREE-STATE DISABLED ENABLED
U9 0 1
POWER DOWN ENABLED
05863-014
DISABLED
Figure 20. Function Register (R3) Map
Rev. 0 | Page 15 of 24
ADF4156
CLK DIV REGISTER, R4
With R3[2,1, 0] set to [1, 0, 0], the on-chip clock divider register (R4) is programmed. Figure 21 shows the input data format for programming this register.
RESERVED BITS
All reserved bits should be set to 0 for normal operation.
INITIALIZATION SEQUENCE
After powering up the part, the correct register programming sequence is: 1. 2. 3. 4. 5. CLK/DIV register (R4) FUNCTION register (R3) MOD/R register (R2) PHASE register (R1) FRAC/INT register (R0)
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for activation of PHASE Resync. See the PHASE RESYNC section for more information.
Clock Divider Mode
These bits must be set to DB[20, 19] = [1, 0] in order to activate PHASE resync, and 0 otherwise.
RESERVED
CLK DIV MODE
12-BIT CLOCK DIVIDER VALUE
RESERVED
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 R4 R3 R2 R1 C3(1) C2(0) C1(0)
M2 0 0 1 1
M1 0 1 0 1
OUTPUT CLK DIV OFF RESERVED RESYNC TIMER ENABLED RESERVED
D12 0 0 0 0 . . . 1 1 1 1
D11 0 0 0 0 . . . 1 1 1 1
.......... D2 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1
D1 0 1 0 1 . . . 0 1 0 1
CLOCK DIVIDER VALUE 0 1 2 3 . . . 4092 4093 4094 4095
Figure 21. CLK DIV Register (R4) Map
Rev. 0 | Page 16 of 24
05863-015
ADF4156
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be programmed: RFOUT = [INT + (FRAC/MOD)] x [FPFD] where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. FPFD = REFIN x [(1 + D)/(R x (1+T))] where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. T is the reference divide-by-2 Bit(0 or 1). R is the RF reference division factor. For example, in a GSM 1800 system, where 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REFIN) is available, and a 200 kHz channel resolution (fRES) is required, on the RF output. MOD = REFIN/fRES MOD = 13 MHz/200 kHz = 65 From Equation 4 FPFD = [13 MHz x (1 + 0)/1] = 13 MHz 1.8 GHz = 13 MHz x (INT + FRAC/65) where INT = 138; FRAC = 30. (5) (6) (4) (3) function. See the Cycle Slip Reduction for Faster Lock Times section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4156 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 5-bit R counter. The following is an example of an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD programming the modulus to divide by 130. This also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD and the modulus can be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus needs to be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). This allows the user to design one loop filter that can be used in both setups without running into stability issues. It is the ratio of the RF frequency to the PFD frequency that affects the loop design. By keeping this relationship constant, the same loop filter can be used in both applications.
MODULUS
The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN sets the modulus to 65. This means that the RF output resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM. With dither off, the fractional spur interval depends on the modulus values chosen. See Table 7 for more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. It is important to note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the - circuit of the N-divider. The reference divide-by-2 divides the reference signal by 2, resulting in a 50% duty cycle PFD frequency. This is necessary for the correct operation of the cycle slip reduction (CSR)
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
As mentioned in the Noise and Spur Mode section, the ADF4156 can be optimized for noise performance. However, in fast-locking applications, the loop bandwidth needs to be wide, and therefore, the filter does not provide much attenuation of the spurs. The cycle slip reduction function on the ADF4156 can be used to get around this issue. Using cycle slip reduction, the loop bandwidth can be kept narrow to attenuate spurs and still obtain fast lock times.
Rev. 0 | Page 17 of 24
ADF4156
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared to the PFD frequency. The phase error at the PFD inputs accumulates too fast for the PLL to correct, and the charge pump temporarily pumps in the wrong direction. This slows down the lock time dramatically. The ADF4156 contains a cycle slip reduction circuit to extend the linear range of the PFD allowing faster lock times without loop filter changes. When the ADF4156 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Stability is maintained because the current is constant and is not a pulsed current. If the phase error increases again to a point where another cycle slip is likely, the ADF4156 turns on another charge pump cell. This continues until the ADF4156 detects that the VCO frequency has gone past the desired frequency. It then begins to turn off the extra charge pump cells one by one until they have all been turned off and the frequency is settled. Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. Setting Bit DB28 in the MOD/R register (R2) to 1 enables cycle slip reduction. Note that a 45% to 55% duty cycle is needed on the signal at the PFD in order for CSR to operate correctly. Table 7. Fractional Spurs with Dither Off
Condition (Dither Off) If MOD is divisible by 2, but not 3 If MOD is divisible by 3, but not 2 If MOD is divisible by 6 Otherwise Repeat Length 2 x MOD 3 x MOD 6 x MOD MOD Spur Interval Channel step/2 Channel step/3 Channel step/6 Channel step
In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum look like broadband noise. This can degrade the in-band phase noise at the PLL output by as much as 10 dB. Therefore, for lowest noise, dither off is a better choice, particularly when the final loop BW is low enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation are interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (which is the whole point of a fractional-N synthesizer) spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, hence the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N synthesizers as the reference offset is far outside the loop bandwidth. However, any reference feed-through mechanism that bypasses the loop can cause a problem. One such mechanism is feed through of low levels of on-chip reference switching noise out through the RFIN pin back to the VCO, resulting in reference spur levels as high as -90 dBc. Care should be taken in the PCB layout to ensure that the VCO is well separated from the input reference to avoid a possible feed through path on the board.
SPUR MECHANISMS
This section describes the three different spur mechanisms that arise with a fractional-N synthesizer and how to minimize them in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third order - modulator (SDM) with a modulus (MOD) that is programmable to any integer value from 2 to 4095. In low spur mode (dither enabled) the minimum allowable value of MOD is 50. The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/MOD. In low noise mode (dither off), the quantization noise from the - modulator appears as fractional spurs. The interval between spurs is fPFD/L, where L is the repeat length of the code sequence in the digital - modulator. For the third-order modulator used in the ADF4156, the repeat length depends on the value of MOD, as listed in Table 7.
SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization noise of the SDM also depends on the particular PHASE word with which the modulator is seeded. Setting the SD reset bit to zero (DB14 in Register 3) ensures that the SDM is seeded with the PHASE word on every write to Register 0. The PHASE word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. Thus, a look-up table of PHASE values corresponding to each frequency can be constructed for use when programming the ADF4156.
Rev. 0 | Page 18 of 24
ADF4156
The evaluation software has a sweep function to sweep the PHASE word so that the user can observe the spur levels on a spectrum analyzer. If a look-up table is not used, keep the PHASE word at a constant value to ensure consistent spur levels on any particular frequency. In the example shown in Figure 22, the PFD reference is 25 MHz and MOD = 125 for a 200 kHz channel spacing. TSYNC is set to 400 s by programming CLK_DIV_VALUE = 80.
LE SYNC (Internal) TSYNC
LAST CYCLE SLIP
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of MOD phase offsets with respect to the input reference; where MOD is the fractional modulus. The PHASE resync feature in the ADF4156 is used to produce a consistent output phase offset with respect to the input reference. This is necessary in applications where the output phase and frequency are important, such as digital beam forming. See the section, PHASE Programmability, for how to program a specific RF output phase when using PHASE resync. PHASE resync is enabled by setting Bit DB20 and Bit DB19 in Register R4 to [1, 0]. When PHASE resync is enabled, an internal timer generates sync signals at intervals of TSYNC given by the following formula: TSYNC = CLK_DIV_VALUE x MOD x TPFD where: TPFD is the PFD reference period. CLK_DIV_VALUE is the decimal value programmed in Bit DB[18:7] of Register R4, and can be any integer in the range of 1 to 4095. MOD is the modulus value programmed in Bit DB[14:3] of Register R1. When a new frequency is programmed, the second sync pulse after the LE rising edge is used to resynchronize the output phase to the reference. The TSYNC time should be programmed to a value that is as least as long as the worst-case lock time. Doing so guarantees that the PHASE resync occurs after the last cycle slip in the PLL settling transient.
FREQUENCY PLL SETTLES TO INCORRECT PHASE PLL SETTLES TO CORRECT PHASE AFTER RESYNC
05863-016
PHASE
-100
0
100
200 300
400 500 600 TIME (s)
700
800
900 1000
Figure 22. PHASE Resync Example
PHASE Programmability
In order to program a specific RF output phase, the PHASE word in Register R1 should be changed. As this word is swept from 0 to MOD, the RF output phase sweeps over a 360o/MOD range in steps of 360o/MOD.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum, however, RF frequencies lower than this can be used providing the minimum slew rate specification of 400 V/s is met. An appropriate LVDS driver can be used to square up the RF signal before it is fed back to the ADF4156 RF input. The FIN1001 from Fairchild Semiconductor is one such LVDS driver.
FILTER DESIGN--ADIsimPLL
A filter design and analysis program is available to help the user to implement PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. In designing the loop filter, the ratio of PFD frequency to loop bandwidth should be kept >200:1. This is to attenuate the SDM noise.
Rev. 0 | Page 19 of 24
ADF4156
INTERFACING
The ADF4156 has a simple SPI(R)-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 29 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 6 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the lead frame chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider
Rev. 0 | Page 20 of 24
ADF4156 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 0.05 MAX 0.02 NOM
0.60 MAX
16 15
PIN 1 INDICATOR
20 1
2.25 2.10 SQ 1.95
6 5
11 10
0.25 MIN 0.30 0.23 0.18
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP
0.50 BSC
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
Rev. 0 | Page 21 of 24
ADF4156
ORDERING GUIDE
Model ADF4156BRUZ 1 ADF4156BRUZ-RL1 ADF4156BRUZ-RL71 ADF4156BCPZ1 ADF4156BCPZ-RL1 ADF4156BCPZ-RL71 EVAL-ADF4156EB1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1
Z = Pb-free part.
Rev. 0 | Page 22 of 24
ADF4156 NOTES
Rev. 0 | Page 23 of 24
ADF4156 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05863-0-5/06(0)
Rev. 0 | Page 24 of 24

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